TA1316AN
Toshiba Bipolar Linear Integrated Circuit Silicon Monolithic
TA1316AN
YCbCr/YPbPr Signal and Sync Processor for Digital TV, Progressive Scan TV and Double
Scan TV
TA1316AN is a component signal and sync processor for Digital
TV, Progressive scan TV and Double scan TV.
TA1316AN provides high performance signal processors in the
luminance and color difference blocks. The sync circuit can
process 525I/P, 625I/P, 750P, 1125I/P, PAL100 Hz and
NTSC120 Hz formats.
TA1316AN provides I2C bus interface, so various functions and
controls are adjustable via the bus.
Features
Weight: 5.55 g (typ.)
Luminance Block
•
Black stretch, DC restoration
•
Dynamic DŽ correction
•
SRT (LTI)
•
Y group delay correction (shoot balance correction)
•
APACON white peak limit
•
White pulse limit (white letter improvement)
•
Hi-bright color
•
Color detail enhancer (CDE)
•
VSM output
Color Difference Block
•
Flesh color correction
•
Dynamic Y/C correction
•
Color SRT (CTI)
•
Color DŽ
•
White peak blue correction
Text Block
•
OSD blending SW
•
ACB (only black level)
•
2 analog RGB inputs
Synchronization Block
•
Horizontal synchronization
(15.75 kHz, 31.5 kHz, 33.75 kHz, 45 kHz)
•
Vertical synchronization
(525I/P, 625I/P, 750P, 1125I/P, PAL 100 Hz, NTSC 120 Hz)
•
2-and 3-level sync. separation circuit
•
Accept both positive and negative HD/VD input
•
Mask for copy-guard signal
•
Vertical blanking
1
2002-10-04
TA1316AN
Y/C VCC 55
Y2 IN
Cb2/Pb2 IN
Cr2/Pr2 IN
3
Cb1/Pb1 IN
29
Cr1/Pr1 IN
Y1 IN
32
2
I L GND
25
2
DEF/DAC GND
19
I L VDD
DEF/DAC VCC
Block Diagram
4
5
8
9
10
CLAMP
Y/C GND 6
SW
YHDPbPr/YCbCrĺ YUV CONVERT
U
V
Y
BLACK
UVĺ IQ
STRETCH
CONVERTER
RGB VCC 40
RGB GND 44
SCL 30
DAC2 36
(ACB PLUSE)
I CBUS
DECODER
SW
IQĺ UV
CONVERTER
DYNAMIC γ
SW
DC REST
DAC2
28
SYNC OUT
SW
DAC1
+
SCP OUT 18
SCP IN 17
H-OUT 26
HORIZONTAL
FREQUENCY 22
SW
EXT
BPP
CP/BPP
H
FREQUENCY
SW
SRT
APACON
WPL
+
CLAMP
PULSE
CP
SW
CP
H-AFC
DARK
DET
1 DARK AREA
DET FILTER
APL
DETECT
56 APL FILTER
YNR
COLOR
SUBCONTRAST
UNI-COLOR
UNICOLOR
SHARPNESS
CONTROL
Y DETAIL
CONTROL
CP
H CURVE 23
CORRECTION
H-BPP
FBP IN 24
2 BPH FILTER
CDE
+
H CURVE
CORRECTION
BLACK PEAK
DETECT
GROUP
DELAY
+
CORRECTION
DL/
COLOR
SRT
H C/D
HVCO
AFC FILTER 20
HD1 IN 16
TINT
EXT
CP
HORIZONTAL
PHASE
SYNC IN 14
SHARPNESS
DELAY LINE
H DUTY
HVCO 21
VP OUT 27
Y/C LEVEL
COMP
BPP
SW
7 MATRIX SW
BLACK LEVEL
CORECTION
FRESH
COLOR
2
SDA 31
CLAMP
CP
FBP/BLK
V-BPP
VP OUT
G-Y
MATRIX
V
FREQUENCY
SW
R-Y
+
53 ABCL IN
WPS
V-BLK
HI-BRIGHT
COLOR
G-Y
COLOR
γ
Yout-γ
HALF TONE
/C MUTE
HALF TONE
EXT
V-BLK
H-BLK
ABCL
AMP
B-Y
ACB
PULSE
CLAMP
PULSE
HD
POLARITY
BRIGHTNESS
WPL
V C/D
HD IN SW
CLAMP
2 × fH
H-RAMP
SYNC
SEPA
RELATIVE
PHASE/
AMPLITUDE
11 COLOR
LIMITER
HPF
HD2 IN 13
V
INTEGRAL
WP BLUE
VD1 IN 15
CP
VD2 IN 12
BLK
VSM
MUTE
CLAMP
OSD
AMP
Y
RGB
MATRIX
CP
RGB OUT
DRIVE
MIXER SW/
BLUE BACK
B OUT 41
OSD
ACL SW
S/H
CUT OFF
RGB
BRIGHTNESS
IK
CLAMP
CP
OR
54 VSM OUT
39 ANALOG
OSD R IN
38 ANALOG
OSD G IN
37 ANALOG
OSD B IN
51 YS1
(ANALOG OSD)
CP
SW
VSM AMP
CLAMP
VD IN SW
R OUT 43
G OUT 42
COLOR
PEAK
DETECT
V-CLP
YM SW
CLAMP
50 YS2
(ANALOG OSD)
2
G S/H
B S/H
34
33
49
52
YM/PMUTE/BLK
R S/H
35
YS3
(ANALOG RGB)
46
ANALOG
B IN
47
ANALOG
G IN
48
ANALOG
R IN
45
IK IN
RGB
CONTRAST
2002-10-04
TA1316AN
Pin Assignment
DARK AREA DET FILTER
1
56
APL FILTER
BPH FILTER
2
55
Y/C VCC
Y1 IN
3
54
VSM OUT
Cb1/Pb1 IN
4
53
ABCL IN
Cr1/Pr1 IN
5
52
YM/P-MUTE/BLK
Y/C GND
6
51
YS 1 (analog OSD)
MATRIX SW
7
50
YS 2 (analog OSD)
Y2 IN
8
49
YS 3 (analog RGB)
Cb2/Pb2 IN
9
48
R S/H
Cr2/Pr2 IN 10
47
G S/H
COLOR LIMITER 11
46
B S/H
VD2 IN 12
45
IK IN
HD2 IN 13
44
RGB GND
43
R OUT
VD1 IN 15
42
G OUT
HD1 IN 16
41
B OUT
SCP IN 17
40
RGB VCC
SCP OUT 18
39
ANALOG OSD R IN
DEF/DAC VCC 19
38
ANALOG OSD G IN
AFC FILTER 20
37
ANALOG OSD B IN
HVCO 21
36
DAC2 (ACB pulse)
HORIZONTAL FREQUENCY SW 22
35
ANALOG R IN
H CURVE CORRECTION 23
34
ANALOG G IN
FBP IN 24
33
ANALOG B IN
DEF/DAC GND 25
32
I L GND
H-OUT 26
31
SDA
VP OUT 27
30
SCL
28
29
I L VDD
SYNC IN 14
TA1316AN
3
2
2
2002-10-04
TA1316AN
Pin Functions
Pin
No.
Pin Name
Function
Interface Circuit
Input Signal/Output Signal
55
Connect filter for detecting
black area.
DC
Voltage value of this pin
controls dynamic γ circuit gain.
1
5 kΩ
50 kΩ
1
DARK AREA DET
FILTER
6
Voltage value of this pin
controls black stretch gain.
2
200 Ω
1 kΩ
DC
5V
BPH FILTER
1 kΩ
2
4.25 V
Connect filter for detecting
black peak.
1 kΩ
4 kΩ
1 kΩ
55
6
4
2002-10-04
TA1316AN
Pin
No.
Pin Name
Function
Interface Circuit
Input Signal/Output Signal
1 Vp-p (including sync) at 100% color bar
55
Inputs Y1 signal via clamp
capacitor.
3
Y1 IN
3
1 kΩ
1 kΩ
Recommended input
amplitude: 1 Vp-p (including
sync) at 100% color bar.
or
5 kΩ
6
55
Inputs Cb1/Pb1 signal via
clamp capacitor.
4
Cb1/Pb1 IN
Recommended input
amplitude: 700 mVp-p at 100%
color bar.
4
1 kΩ
1 kΩ
700 mVp-p at 100% color bar for Cb1/Pb1
5 kΩ
6
5
2002-10-04
TA1316AN
Pin
No.
Pin Name
Function
Interface Circuit
Input Signal/Output Signal
55
Inputs Cr1/Pr1 signal via clamp
capacitor.
5
Cr1/Pr1 IN
5
1 kΩ
1 kΩ
Recommended input
amplitude: 700 mVp-p at 100%
color bar.
100 mVp-p at 100% color bar for Cr1/Pr1
5 kΩ
6
Y/C GND
GND pin for Y/C block.
55
Matrix switching pin for YCbCr
or YPbPr input.
7
MATRIX SW
When pin is not used, connect
0.01 µF capacitor between pin
and GND.
BUS
When YUV INPUT MODE = 00 or 01,
25 µA
Switches matrix according to
voltage value input to this pin
when BUS control “YUV
INPUT MODE” = 00 or 01.
Then, control by pin has
priority over control by BUS
(see table 4).
7
0~0.6 V: YCbCr → Internal YUV
0.9~5 V: YPbPr → Internal YUV
1 kΩ
112 kΩ
6
Open: BUS control
6
6
2002-10-04
TA1316AN
Pin
No.
Pin Name
Function
Interface Circuit
Input Signal/Output Signal
1 Vp-p (including sync) at 100% color bar
55
Inputs Y2 signal via clamp
capacitor.
8
Y2 IN
8
1 kΩ
1 kΩ
Recommended input
amplitude: 1 Vp-p (including
sync) at 100% color bar.
or
5 kΩ
6
55
Inputs Cb2/Pb2 signal via
clamp capacitor.
9
Cb2/Pb2 IN
Recommended input
amplitude: 700 mVp-p at 100%
color bar.
9
1 kΩ
1 kΩ
700 mVp-p at 100% color bar for Cb2/Pb2
5 kΩ
6
7
2002-10-04
TA1316AN
Pin
No.
Pin Name
Function
Interface Circuit
Input Signal/Output Signal
55
Inputs Cr2/Pr2 signal via clamp
capacitor.
10
Cr2/Pr2 IN
10
1 kΩ
1 kΩ
Recommended input
amplitude: 700 mVp-p at 100%
color bar.
700 mVp-p at 100% color bar for Cr2/Pr2
5 kΩ
6
7 µA
55
11
COLOR LIMITER
Connect filter for detecting
color limit.
11
DC
5 kΩ
6
8
2002-10-04
TA1316AN
Pin
No.
Pin Name
Function
Interface Circuit
19
VD2 IN
Inputs vertical sync signal
VD2. Signal input can have
both positive and negative
polarity.
12
Threshold:
0.75 V
1 kΩ
or
45 kΩ
12
Threshold:
0.75 V
25
19
HD2 IN
Inputs horizontal sync signal
HD2. Signal input can have
both positive and negative
polarity.
13
1 kΩ
Threshold:
0.75 V
or
50 kΩ
13
Input Signal/Output Signal
Threshold:
0.75 V
25
9
2002-10-04
TA1316AN
Pin
No.
Pin Name
Function
Interface Circuit
Input Signal/Output Signal
White 100%: 1 Vp-p
1 kΩ
19
SYNC IN
Inputs sync signal via clamp
capacitor.
14
or
1 kΩ
10 µA
1 kΩ
14
25
19
VD1 IN
Inputs vertical sync signal
VD1. Signal input can have
both positive and negative
polarity.
15
1 kΩ
or
45 kΩ
15
Threshold:
0.75 V
25
10
Threshold:
0.75 V
2002-10-04
TA1316AN
Pin
No.
Pin Name
Function
Interface Circuit
19
HD1 IN
16
1 kΩ
Threshold:
0.75 V
or
50 kΩ
16
Inputs horizontal sync signal
HD1. Input signal can have
both positive and negative
polarity.
Input Signal/Output Signal
25
Threshold:
0.75 V
40 kΩ
19
Inputs SCP from up converter.
SCP IN
Input signals are clamp pulse
(CP) and black peak detection
stop pulse (BPP).
17
2.2 V~2.8 V: BPP
5 kΩ
4.7 V~9 V:
CP
50 kΩ
17
25
500 Ω
Outputs SCP.
Output signals are clamp pulse
(CP) and black peak detection
stop pulse (BPP).
SCP OUT
(Note) Don’t use
Horizontal-BPP (H-BPP) for
the timing pulse of picture
period on the screen (e.g.
H-BLK) because H-BPP width
will be changed by the
temperature.
CP: 5.0 V
BPP: 2.5 V
18
0V
200 Ω
2.5 kΩ
18
19
25
11
2002-10-04
TA1316AN
Pin
No.
Pin Name
Function
Interface Circuit
Input Signal/Output Signal
VCC pin for DEF/DAC block.
19
DEF/DAC VCC
To ascertain the correct
voltage for VCC, please refer to
the table entitled Maximum
Ratings.
19
20
AFC FILTER
Connect filter for detecting
AFC.
DC
30 kΩ
20
300 Ω
25
21
HVCO
2 kΩ
Connect ceramic oscillator for
horizontal oscillation.
Use Murata
CSBLA503KECZF30
oscillator.
1 kΩ
19
21
1 kΩ
10 kΩ
25
12
2002-10-04
TA1316AN
Pin
No.
Pin Name
Function
Interface Circuit
Input Signal/Output Signal
1 kΩ
19
HORIZONTAL
FREQUENCY
SW
22
60 kΩ 60 kΩ 15 kΩ
22
When selecting horizontal
frequency by BUS control,
leave pin open. Control by pin
has priority over control by
BUS.
60 kΩ
Horizontal frequency select
pin.
Selects horizontal frequency
according to voltage value
input to this pin.
1 kΩ
30 kΩ
20 pF
When this IC will be used on
CRT, the frequency of H-out
(pin 26) should be controlled
by DC voltage which is divided
from voltage of DEF VCC (pin
19) by resisters.
7.5 V
At BUS control (horizontal frequency):
output voltage value
00 (15.75 kHz): DC 9 V
01 (31.5 kHz): DC 6 V
10 (33.75 kHz): DC 3 V
11 (45 kHz):
DC 0 V
4.5 V
At pin 22 control, horizontal frequency
and input voltage value
16 kΩ
1.5 V
0~1.0 V:
2.0~4.0 V:
5.0~7.0 V:
8.0~9.0 V:
45 kHz
33.75 kHz
31.5 kHz
15.75 kHz
25
When pin is not used, connect
0.01 µF capacitor between pin
and GND.
50 kΩ
23
1 kΩ
DC
6.5 V
130 kΩ
H CURVE
CORRECTION
25 kΩ
23
Corrects curve at high-tension
fluctuation.
Input AC component of
high-tension fluctuation.
65 kΩ
19
25
13
2002-10-04
TA1316AN
Pin
No.
Pin Name
Function
Interface Circuit
Input Signal/Output Signal
19
2.25 V
max: 9 V
FBP IN
Input FBP and H-BLK for
horizontal AFC.
H-AFC threshold: 3.0 V
24
BLK threshold: 1.5 V
500 Ω
1 kΩ
5V
24
25
25
DEF/DAC GND
GND pin for DEF/DAC block.
19
26
H-OUT
Horizontal output pin. Open
collector output.
26
5 kΩ
25
14
2002-10-04
TA1316AN
Pin
No.
Pin Name
Function
Interface Circuit
Input Signal/Output Signal
19
27
VP OUT
When a current is applied to
the pin, external blanking is
carried out by ORing this
signal with the internal
blanking signal.
VP output:
200 µA
Outputs vertical pulse.
27
5V
200 Ω
0V
(Note) When H-POSITION will
be changed, VP width will
change. Use the start phase of
VP.
32
25
Start phase
V-BLK input current: 780 µA~1 mA
19
Outputs 1-bit DAC or
composite SYNC signal after
sync separation.
28
DAC1
(SYNC OUT)
Open-collector output
(The output level for this pin
cannot be guaranteed since
leakage from internal signals
may occur.)
DC or SYNC OUT
28
500 Ω
32
25
2
VDD pin for I L block.
Connect 2 V (typ.).
29
2
I L VDD
Power to pin 29 should be
supplied from pin 19 via zener
diode through resister.
15
2002-10-04
TA1316AN
Pin
No.
Pin Name
Function
Interface Circuit
Input Signal/Output Signal
19
SCL
30
5 kΩ
SCL
SCL pin for I C BUS.
2.25 V
30
2
25
32
19
SDA
2
31
50 Ω
5 kΩ
SDA
SDA pin for I C BUS.
2.25 V
31
ACK
25
32
32
2
I L GND
2
GND pin for I L block.
16
2002-10-04
TA1316AN
Pin
No.
Pin Name
Function
Interface Circuit
Input Signal/Output Signal
40
33
ANALOG B IN
Inputs analog R/G/B signal via
clamp capacitor.
34
ANALOG G IN
35
ANALOG R IN
Recommended input
amplitude: 0.7 Vp-p (no sync)
at 100% white
33
34
35
1 kΩ
1 kΩ
100 IRE: 0.7 Vp-p
1 kΩ
44
40
DC or ACB pulse
36
DAC2
(ACB pulse)
Outputs 1-bit DAC or ACB
pulse
36
500 Ω
Open-collector output
44
17
2002-10-04
TA1316AN
Pin
No.
Pin Name
Function
Interface Circuit
Input Signal/Output Signal
40
37
ANALOG OSD B IN
Inputs analog OSD signal via
clamp capacitor.
38
ANALOG OSD G IN
39
ANALOG OSD R IN
Recommended input
amplitude: 0.7 Vp-p (no sync)
at 100% white
37
38
39
1 kΩ
1 kΩ
100 IRE: 0.7 Vp-p
1 kΩ
44
VCC pin for text/RGB block.
40
RGB VCC
To ascertain the correct
voltage for VCC, please refer to
the table entitled Maximum
Ratings.
41
100 Ω
40
B OUT
Outputs R/G/B signal.
G OUT
43
R OUT
Recommended output
amplitude: 100 IRE = 2.3 Vp-p
Conditions:
41
42
43
200 Ω
UNI-COLOR = max
SUB-CONT = Cent
2.7 mA
42
100 IRE: 2.3 Vp-p
Y IN = 0.7 Vp-p
44
44
RGB GND
GND pin for text/RGB block.
18
2002-10-04
TA1316AN
Pin
No.
Pin Name
Function
Interface Circuit
Input Signal/Output Signal
40
R
G
B
1 Vp-p (typ.)
0 V~3 V
Inputs the feedback signal
from CRT. (BLK level should
be 0 V to 3 V.)
45
IK IN
or RGB VCC
45
When ACB is not used,
connect this pin to the RGB
VCC pin.
1 kΩ
44
40
Sample-and-hold (S/H) pin.
47
G S/H
48
R S/H
In ACB mode connect a 2.2-µF
capacitor. In CUTOFF mode
connect a 0.01-µF capacitor.
46
47
48
500 Ω
1 kΩ
5 kΩ
DC
3 pF
B S/H
3V
46
44
19
2002-10-04
TA1316AN
Pin
No.
Pin Name
Function
Interface Circuit
Input Signal/Output Signal
40
49
YS3
(analog RGB)
Selects input between internal
RGB and external analog RGB
according to voltage value
input to this pin.
49
When analog RGB is selected,
mutes VSM output.
300 Ω
0~0.5 V: Internal
300 Ω
1.5~9 V: Analog RGB, VSM mute
44
Switches between internal
RGB and OSD input signals.
Voltage applied to YS1 and
YS2 adjusts blend ratio of
internal RGB and OSD signals.
YS2
(analog OSD)
When YS1 or YS2 is High,
mutes VSM output.
Blend ratio
YS2 YS1 Int RGB:
OSD RGB
51
YS1
(analog OSD)
L
L
10:0
H
L
7:3
L
H
5:5
H
H
0:10
50
51
0~0.5 V:
300 Ω
Internal
1.1~1.7 V: VSM mute
2.9~9 V:
50 kΩ
50
40
OSD, VSM mute
44
20
2002-10-04
TA1316AN
Pin
No.
Pin Name
Function
Interface Circuit
Input Signal/Output Signal
40
YM/P-MUTE/BLK
Also performs image mute or
blanking.
Internal
1.2~1.8 V: Half-tone
2.7~4.0 V: P-mute
7~9 V:
Blanking
10 kΩ
52
0~0.5 V:
300 Ω
52
80 kΩ
Fast half-tone switch for
internal RGB signal.
44
6.75 V
40
ABL and ACL input pin.
53
ABCL IN
Can set gain and start point for
ABL and dynamic ABL by BUS
control.
30 kΩ
3 kΩ
DC
53
44
21
2002-10-04
TA1316AN
Pin
No.
Pin Name
Function
Interface Circuit
Input Signal/Output Signal
VSM OUT
54
1.6 mA
Mutes output signal using pins
49, 50 and 51.
200 Ω
1 kΩ
54
Outputs Y signal for VSM
which passes through HPF
circuit (primary differential
circuit).
200 Ω
40
6
VCC pin for Y/C block.
55
Y/C VCC
To ascertain the correct
voltage for VCC, please refer to
the table entitled Maximum
Ratings.
55
40 kΩ
Connect filter for correcting DC
restoration.
56
APL FILTER
Leaving this pin open enables
user to monitor Y signal after
black stretch and dynamic γ.
56
1 kΩ
1 kΩ
6
22
2002-10-04
TA1316AN
Bus Control Map
Write Mode
Slave Address: 88H
Sub-Add
D7
00
D6
H-FREQ
D5
D4
D3
D2
H-DUTY
YUV-SW
DAC1
DAC2
01
ACB-MODE
SCP-SW
03
SYNC INPUT-SW
HBP-PHS
CLP-PHS
SYNC SEP-LEVEL
V-BLK PHASE
04
TEST
VERTICAL FREQUENCY
COMPRESSION-BLK PHASE-1
COMPRESSION-BLK PHASE-2
P-MODE1
UNI-COLOR
06
07
D0
HORIZONTAL POSITION
02
05
D1
BRIGHTNESS
OSD-ACL
COLOR
Preset
1000
0000
1000
0000
1000
0000
1000
0000
1000
0000
1000
0000
1000
0000
1000
0000
08
TINT
RGB-ACL
1000
0000
09
PICTURE SHARPNESS
YNR
1000
0000
0A
RGB BRIGHTNESS
DCRR-SW
1000
0000
1000
0000
YUV INPUT MODE
1000
0000
0B
HI BRT
RGB CONTRAST
0C
SUB CONTRAST
WPS
0D
DRIVE GAIN1
DR-R
1000
0000
0E
DRIVE GAIN2
DR-B/G
1000
0000
0F
R CUT OFF
1000
0000
10
G CUT OFF
1000
0000
11
B CUT OFF
1000
0000
1000
0000
12
R-Y/B-Y GAIN
13
R-Y/B-Y PHASE
G-Y/B-Y GAIN
14
COLOR SRT GAIN
15
C.D.E.
G-Y/B-Y PHASE
Y/C GAIN COMP1
1000
0000
CLT
1000
0000
FRESH-COLOR
1000
0000
COLOR γ
C-SRT FREQ
Y/C GAIN COMP2
16
VSM PHASE
VSM GAIN
APACON PEAK FREQ
1000
0000
17
DC REST POINT
DC REST RATE
DC REST LIMIT
1000
0000
18
BLACK STRETCH POINT
1000
0000
1000
0000
19
SHR-TRACKING
APL VS BSP
B.L.C.
WPL-LEVEL
B.D.L
BS-ARE
WPL-FREQ
1A
DYNAMIC ABL POINT
DYNAMIC ABL GAIN
P-MODE2
1000
0000
1B
ABL POINT
ABL GAIN
RGB OUT MODE
1000
0000
1000
0000
APACON WPL
1000
0000
WP BLUE POINT
1000
0000
WP BLUE GAIN
1000
0000
1C
DYNC γ -POINT
1D
OSD BRIGHT
DYNC γ GAIN VS DARK AREA
OSD CONTRAST
1E
Y DETAIL CONTROL
1F
Y GROUP DELAY CORRECTION
STATIC γ -GAIN
Y/C-DL1
Y/C-DL2
Y-OUT γ
Read Mode
Slave Address: 89H
0
D7
D6
D5
D4
D3
D2
D1
D0
POR
IK-IN
RGB-OUT
YUV-IN
H-OUT
VP-OUT
RGB-IN
SYNC-IN
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Bus Control Functions
Write Mode
Parameter
Preset
Explanation
Selects horizontal oscillation frequency.
H-FREQUENCY
00: 15.75 kHz,
01: 31.5 kHz,
10: 33.75 kHz, 11: 45 kHz
33.75 kHz
Control by pin 22 has priority over BUS control. When this IC will be used on CRT,
the frequency of H-out should be controlled by pin 22.
Switches horizontal output duty.
H-DUTY
41%
0: 41%,
1: 47%
Switches YUV input.
INPUT-1
YUV-SW
0: INPUT-1 (Y1/Cb1/Cr1),
1: INPUT-2 (Y2/Cb2/Cr2)
Switches DAC control output.
DAC 1
Open
Don't use this function
Switches DAC control output.
0: On (low),
DAC 2
1: Open (high)
When TEST = 00, controls 1-bit DAC when output is open-collector.
On
When TEST = 01, outputs ACB reference pulse from pin 36.
Selects sync input.
00: Selects HD1/VD1 input.
SYNC INPUT-SW
HD/VD1
01: Selects HD2/VD2 input.
10/11: Selects SYNC input.
Adjusts horizontal picture phase.
HORIZONTAL
POSITION
0000000 (−10.5%)~1111111 (+10.5%)
Center
(Note) When H-POSITION will be changed, VP width (pin 27) will change.
Switches clamp pulse phase.
0: 0.7-µs (2.5%) width with 1.1-µs (3.8%) delay from HD stop phase
CLP-PHS
1: 0.7-µs (2.4%) width with 0.2-µs (0.7%) delay from HD stop phase
1.1-µs delay
While quiescent, 0.8-µs (2.7%) width with 1.2-µs (4.2%) delay from FBP start
phase
Also switches CP phase of SCP-OUT (pin 18).
Sets ACB mode. Selects reference level for convergence.
ACB MODE
00: ACB off (cutoff BUS control), 01: ACB on (5 IRE),
10: ACB on (10 IRE),
ACB on (10 IRE)
11: ACB on (20 IRE)
Switches SCP (sandcastle pulse) mode.
0: Internal mode,
SCP-SW
1: External input mode
Inside IC
Also switches SCP-OUT (pin 18).
(Note) Don’t use H-BPP for the timing pulse, because H-BPP width of internal
mode will be changed by the temperature.
Switches horizontal black peak detection pulse phase.
HBP-PHS
0: ±6.3% of FBP, 1: ±3.5% of FBP
6.3% width
Selects SYNC separation level.
SYNC SEP-LEVEL
min
00: 8.5%, 01: 20%, 10: 30%, 11: 40%
Test mode
When TEST = 00, controls 1-bit DAC when output is open-collector.
TEST
When TEST = 01, outputs H-SYNC from pin 28 and ACB reference pulse from pin 00
36.
Do not use TEST = 10/11 because this is used for IC Shipment Test mode.
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Parameter
Preset
Explanation
Adjusts vertical BLK stop phase.
V-BLK PHASE
00000 (16H) ~11110 (46H) (1 H/STEP),
32 H
11111: Internal V-BLK off
V-FREQUENCY
Vertical free-running frequency. Sets vertical pull-in range (Table 1).
1281 H
COMPRESSION-BLK
PHASE-1/2
Adjusts compression BLK phase. Adjusts BLK at top and bottom (Table 2).
Off
P-MODE1/2
Selects picture mode. Selects between picture mute, half-tone, blue background,
P-MUTE 1
and Y mute (Table 3).
Adjusts unicolor.
UNI-COLOR
min
0000000 (−16.5dB) ~111 (0dB)
Adjusts brightness.
BRIGHTNESS
Center
00000000 (−40 IRE) ~11111111 (+40 IRE)
Turns OSD-ACL on/off.
OSD-ACL
On
0: Off, 1: On
Adjusts color.
COLOR
0000000: Color mute,
C-MUTE
0000001 (−20dB or more) ~1111111 (+4.6dB)
Adjusts tint.
TINT
Center
0000000 (−32 deg) ~1111111 (+32 deg)
Switches analog RGB-ACL sensitivity.
RGB-ACL
0: −6dB,
−6 dB
1: Normal
Adjusts sharpness.
PICTURE-SHARPNESS
Center
0000000 (−10dB or more) ~1111111 (+17dB (at peak FREQ) )
YNR: Turns luminance (Y) noise reduction (NR) on/off.
0: Off, 1: On
YNR
Lower two bits of PICTURE-SHARPNESS (09-D2/D1)
= 00: Trap (at peak FREQ)
= 11: Flat
Off
YNR level is controlled by lower two bits (09-D2) of PICTURE-SHARPNESS.
DL-APACON gain control by PICTURE-SHARPNESS is invalid.
Adjusts RGB brightness.
RGB-BRIGHTNESS
Center
0000000 (−20 IRE) ~1111111 (+20 IRE)
Switches DC restoration rate.
DCRR-SW
100% or more
0: 100% or more,
1: 100% or less
Turns high bright color on/off.
HI BRT
On
0: Off, 1: On
Adjusts RGB contrast.
RGB-CONTRAST
min
0000000 (−16.5dB) ~1111111 (0dB)
Adjusts sub-contrast.
SUB-CONTRAST
Center
00000 (−3.5dB) ~11111 (+2.6dB)
Adjusts WPS level.
WPS
110 IRE
0: 110 IRE
1: 130 IRE
Selects Y/color difference signal input mode.
00: Y/Cb/Cr, 01: Y/Pb/Pr,
YUV INPUT MODE
10: Through,
11: Y/U/V (TA1270)
Control by pin takes priority at 00 and 01 (table 4).
Y/Cb/Cr
(Ref.) Y/Cb/Cr: ITU-R BT 601
Y/Pb/Pr: ITU-R BT 709 (1125/60/2:1)
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Parameter
Preset
Explanation
Adjusts drive gain 1 and drive gain 2.
DRIVE GAIN1/2
Center
0000000 (−5dB) ~1111111 (+3dB)
DR-R
Switches reference RGB drive gain (Table 5).
R
DR-B/G
Adjusts R/G/B cutoff.
1) RGB-OUT when ACB off
R/G/B CUT OFF
Center
00000000 (1.9 V) ~11111111 (2.9 V)
2)SENS-IN when ACB on
00000000 (0.5 Vp-p) ~11111111 (1.5 Vp-p)
Adjusts R-Y/B-Y relative amplitude.
R-Y/B-Y GAIN
Center
0000 (0.54) ~1111 (0.85)
Adjusts R-Y/B-Y relative phase.
R-Y/B-Y PHASE
min
0000 (90 deg) ~1111 (111.5 deg)
Adjusts G-Y/B-Y relative amplitude.
G-Y/B-Y GAIN
Center
0000 (0.28) ~1111 (0.38)
Adjusts G-Y/B-Y relative phase.
G-Y/B-Y PHASE
min
0000 (232 deg) ~1111 (256 deg)
Adjusts color SRT gain.
COLOR SRT GAIN
Center
000 (min) ~111 (max)
Selects color SRT peak frequency.
C-SRT-FREQ
4.3 MHz
00: 4.5 MHz,
COLOR γ
01: 5.8 MHz,
10: 8.5 MHz,
11: Off
Selects color γ correction point.
00: Off, 01: 0.23 Vp-p,
Off
10: 0.40 Vp-p,
11: 0.58 Vp-p
Switches color limiter level.
CLT
0: 1.65 Vp-p,
1.65 Vp-p
1: 2 Vp-p
Adjusts color detail enhancer.
CDE
Center
00: min 11: max
Selects dynamic Y/C compensation.
Y/C GAIN COMP1/2
COMP1,
00: Off,
01: min, 10: mid,
11: max
COMP2,
00: Off,
01: min, 10: mid,
11: max
All off
Selects flesh color.
FRESH-COLOR
00: Off, 01: ±33.7 deg, Normal,
10: ±9.5 deg, High,
Off
11: ±9.5 deg, Normal
Adjusts VSM phase.
−7.5 ns
VSM-PHASE
000 (−37.5 ns) ~101 (normal) ~111 (+15 ns)
Adjusts VSM gain.
VSM GAIN
000: OFF,
001: +3 dB,
Off
111: +19 dB
Selects APACON peak frequency.
APACON PEAK f0
13.5 MHz
00: 13.5 MHz,
01: 9.5 MHz,
10: 7.3 MHz,
11: 4.7 MHz
DC restoration point
DC REST POINT
Center
000: 0%,
111: 51%
Adjusts DC restoration rate.
DC REST RATE
100%
000 (100%) ~111 (135% (65%) )
Selects DC restoration limit point.
DC REST LIMIT
min
00: 57%,
01: 71％,
10: 78%, 11: 78%
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Parameter
Preset
Explanation
Adjusts black stretch point 1.
BLACK STRETCH POINT
Center
000: OFF,
001 (34 IRE) ~111 (53 IRE)
Adjusts black stretch point 2.
APL VS BSP
0 IRE
00 (0 IRE) ~11 (24 IRE) up
Turns black level automatic correction on/off.
B.L.C
Max: 8.5 IRE, black stretch has priority.
Off
0: Off, 1: On
Switches black detection level.
B.D.L.
3 IRE
0: 3 IRE,
1: 0 IRE
Turns black stretch area on/off.
BS-ARE
On
0: On, 1: Off
SHR tracking (adjusts SRT component gain.)
SHR-TRACKING
Center
00 (SRT-GAIN max) ~11 (SRT-GAIN min)
Adjusts white letter improvement amplitude.
WPL-LEVEL
min
000: min 111: max
Adjusts white letter improvement start frequency.
WPL-FREQ
5 MHz
000 (5 MHz) ~111 (16 MHz)
Adjusts dynamic ABL detection voltage.
DYNAMIC ABL POINT
Center
000 (min) ~111 (max)
Adjusts dynamic ABL sensitivity.
DYNAMIC ABL GAIN
min
000 (min) ~111 (max)
Adjusts ABL detection voltage.
ABL POINT
Center
000 (min) ~111 (max)
Adjusts ABL sensitivity.
ABL GAIN
min
000 (min) ~111 (max)
Switches RGB output mode (switch for RGB output mode for test and adjustment).
RGB-OUT MODE
Normal
00: Normal, 01: R only,
DYNCγ-POINT
10: G only,
11: B only
Switches dynamic Y γ point.
00: 20 IRE, 01: 21.5 IRE,
23.5 IRE
10: 23.5 IRE,
11: 25 IRE
Turns dynamic Y γ gain VS dark area on/off.
DYNCγ GAIN VS DARK
AREA
000 (min) ~
min
111 (max (when 25 IRE or below is 25% or more of area ratio, +3dB) )
STATICγ-GAIN
Y-outγ
Turns static Y γ dark area gain on/off.
00: Off (0dB) 11: max (1.5dB, at this time, DYNCγ gain is +1.5dB max)
Turns Y-out γ on/off.
Off
Off
0: Off, 1: On
Adjusts OSD brightness.
OSD BRIGHT
00: 5 IRE,
01: 0 IRE, 10: −5 IRE,
11: −10 IRE
−5 IRE
Adjusts OSD contrast.
OSD-CONTRAST
min
00 (min (−9.5dB) ) ~11 (max (0dB) )
Adjust Y/C relative phase: Y phase before RGB matrix is changed.
Y/C DL1/2
Y/C DL2 = 0 and Y/C DL1 = 0: −10 ns, Y/C DL2 = 0 and Y/C DL1 = 1: −5 ns
−10 ns
Y/C DL2 = 1 and Y/C DL1 = 0: 0 ns, Y/C DL2 = 1 and Y/C DL1 = 1: +5 ns
Adjusts APACON white peak limiter.
APACON WPL
Off
000 (Off) ~111 (Maximum effect of positive limiter)
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TA1316AN
Parameter
Preset
Explanation
Controls Y detail: Adjusts differential signal for frequency other than picture
sharpness.
00000 (min (trap) ) ~11111 (max (+6dB) )
Y DETAIL CONTROL
Center
Peak frequency linked to APACON PEAK FREQ
00: 5.5 MHz,
01: 3.7 MHz,
10: 14.5 MHz,
11: 10 MHz
Adjusts white peak blue point.
WP BLUE POINT
min
000 (60 IRE) ~111 (112 IRE)
Corrects Y group delay.
Y-GROUP DELAY
CORRECTION
0000: Decreases preshoot gain (increases overshoot gain).
Center
1111: Decreases overshoot gain (increases preshoot gain).
Adjusts white peak blue gain.
WP BLUE GAIN
min
000 (min (+2.3 dB) ) ~111 (max (+10 dB) )
Table 1: Vertical Frequency
Data
V-BPP
V PULL-IN Range
Start Phase
Format/V-FREQUENCY, H-FREQUENCY
Stop Phase
000
48~1281H
1100H
1125P/30 Hz (33.75 kHz)
001
48~849H
730H
750P/60 Hz (45 kHz)
010
48~725H
600H
011
48~660H
625P/50 Hz (31.5 kHz)
V-BLK P.
545H
1125I/60 Hz (33.75 kHz)
(C.BLK P.)
100
48~613H
500H
101
48~363H
290H
PAL/SECAM/50 Hz (15.625 kHz),
100 Hz (31.5 kHz)
110
48~307H
240H
NTSC/60 Hz (15.734 kHz),
120 Hz (31.5 kHz)
111
VP-OUT HI
+20 H
525P/60 Hz (31.5 kHz)
Table 2: Compression-BLK Phase
V-FREQUENCY
PHASE-1 (start phase)
000
1088H~1118H
001
720H~750H
010
592H~622H
011
528H~558H
100
488H~518H
101
280H~310H
110
224H~254H
111
PHASE-2 (stop phase)
50H~78H
(0000: C-BLK OFF)
C-BLK OFF
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Table 3: P-Mode
05-D7
1A-D1
1A-D0
MODE
Details
Can mute picture or half-tone main signal using YM pin.
0
0
0
NORMAL 1
Can insert analog RGB-IN using Ys3; OSD-IN using Ys1/Ys2.
Analog RGB-IN > P-Mute
Mutes main signal Y in whole picture using BUS.
0
0
1
Y-MUTE
Can insert analog RGB-IN using Ys3; OSD-IN using Ys1/Ys2.
Analog RGB-IN > P-Mute
Half-tones main signal in whole picture using BUS.
Can insert P-Mute using YM pin.
0
1
0
YM 1
Can insert analog RGB-IN using Ys3.
Blends OSD-IN with main H/T signal using Ys1/Ys2.
Analog RGB-IN > P-Mute
Blue-backs main signal using BUS.
0
1
1
Can insert P-Mute using YM pin.
BB
Can insert analog RGB-IN using Ys3; OSD-IN using Ys1/Ys2.
Analog RGB-IN > P-Mute
Mutes main signal in whole picture using BUS.
1
0
0
P-MUTE 1
Can insert analog RGB-IN using Ys3; OSD-IN using Ys1/Ys2.
Analog RGB-IN > P-Mute
1
0
1
YM2
Cannot be used.
1
1
0
P-MUTE 2
Cannot be used.
1
1
NORMAL 2
Cannot be used.
1
Output priority: main signal < BB < P-MUTE < RGB-IN < OSD-IN
Table 4: YUV INPUT MODE
YUV INPUT MODE
00
Pin 7
MATRIX
LOW
YCbCr → Internal YUV
HIGH
YPbPr → Internal YUV
OPEN
YCbCr → Internal YUV
LOW
YCbCr → Internal YUV
HIGH
YPbPr → Internal YUV
OPEN
YPbPr → Internal YUV
10
Through
11
YUV → Internal YUV
01
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Table 5: DR-R, DR-B/G
0D-D0
0E-D0
Reference Axis
Drive Gain1
Drive Gain2
0
0
R
G
B
0
1
R
G
B
1
0
G
R
B
1
1
B
G
R
Read Mode
Parameter
Explanation
Power-on reset
POR
0: Register preset, 1: Normal
After power-on, 0 is read on first read; 1 on subsequent reads.
IK input detection: detects input to pin 45.
IK-IN
0: NG (no input), 1: OK (input)
RGB-OUT self-check result: detects output from pins 41, 42 and 43.
RGB-OUT
0: NG (no output), 1: OK (output)
Returns OK when signal is detected on all three outputs. If signals are small, does not return
OK.
YUV-IN self-check result: detects input to pins 3, 4 and 5 or pins 8, 9 and 10.
YUV-IN
0: NG (no input), 1: OK (input)
Returns OK when AC signal is detected on all three inputs. If signals are small or are DC
voltage, does not return OK.
H-OUT self-check result: detects output from pin 26.
H-OUT
0: NG (no output), 1: OK (output)
VP-OUT self-check result: detects output from pin 27.
VP-OUT
0: NG (no output), 1: OK (output)
RGB-IN self-check result: detects input to pins 33, 34 and 35.
RGB-IN
0: NG (no input), 1: OK (input)
Returns OK when AC signal is detected on all three inputs. If signals are small or are DC
voltage, does not return OK.
SYNC-IN self-check result: detects input to pin 14.
SYNC-IN
0: NG (no input), 1: OK (input)
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2
Data Transfer Format via I C BUS
Slave Address: 88H
A6
A5
A4
A3
A2
A1
A0
W/R
1
0
0
0
1
0
0
0/1
Start and Stop Condition
SDA
SCL
S
P
Start condition
Stop condition
Bit Transfer
SDA
SCL
Change of SDA allowed
SDA stable
Acknowledge
SDA by transmitter
Bit 9: High-impedance
SDA by receiver
Bit 9 only: Low-impedance
SCL from master
1
8
9
S
Clock pulse for acknowledge
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Data Transmit Format 1
S
Slave address
7 bits
0 A
MSB
S: Start condition
Sub address
8 bits
A
MSB
A: Acknowledge
Transmit data
9 bits
A P
MSB
P: Stop condition
Data Transmit Format 2
S
Slave address
0 A
Sub address
･･････
A
Transmit data
Sub address
A
A
･･････
Transmit data n
A P
Data Receive Format
S
Slave address
7 bits
MSB
1 A
Transmit data 1
8 bits
A
Transmit data 2
A P
MSB
At the moment of the first acknowledge, the master transmitter becomes a master receiver and a slave
transmitter.
The Stop condition is generated by the master.
Details are provided in the Philips I2C specifications.
Optional Data Transmit Format: Automatic Increment Mode
S
Slave address
7 bits
MSB
0 A 1
Sub address
7 bits
A
Transmit data 1
8 bits
MSB
MSB
････
Transmit data 2
8 bits
A P
MSB
In this transmission method, data is set on automatically incremented sub-address from the specified
sub-address.
Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Rights to use these
components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by
Philips.
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Maximum Ratings (Ta = 25°C)
Characteristics
Rating
Symbol
Unit
PCB A
PCB B
PCB C
VCCmax
12
12
12
V
Input pin signal voltage
einmax
9
9
9
Vp-p
Power dissipation
PD (Note1)
Power supply voltage
2551
2717
3378
mW
Power dissipation reduction rate
1/θja
20.4
21.7
27.0
mW/°C
Operating temperature
Topr
−20~65
−20~65
−20~65
°C
Storage temperature
Tstg
−55~150
−55~150
−55~150
°C
min
8.5
8.7
8.7
typ.
8.8
9.0
9.0
max
9.1
9.3
9.3
Power supply voltage
(Pins 19, 40, 55)
V
Note 1: Please see the following Figure.
Note, however, that the conditions apply only to the case where the device is mounted on board A (180 mm
× 125 mm × 1.6 mm, one-sided); board B (329 mm × 249 mm × 1.6 mm, two-sided); or board C (276 mm ×
192 mm × 1.6 mm, six-layered). When mounting the IC, select boards no smaller than these. When using
under the conditions of board A, set the IC’s power supply voltage (pins 19, 40, 55) to 8.8 V (±0.3 V)
Because the IC’s thermal capacity margin is narrow, when designing a set, incorporate heat discharge
features into the design. Note that the power dissipation varies widely depending on the board mounting
conditions.
3378
Printed circuit board B
Printed circuit board C
Power dissipation PD
(mW)
2717
2551
2297
1848
1735
Printed
circuit
board A
0
0
25
65
150
Ambient temperature Ta (°C)
Figure 1
Characteristics of decrease in power dissipation
Note 2: Pins 3, 4, 5, 7, 8, 9, 10, 11, 20, 21, 22, 23, 30, 31, 33, 34, 36, 39, 45, 46, 49, 50, 51, 52 and 53 are
susceptible to damage from surge voltages and should thus be handled with extreme care.
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Note 3: Power supply sequence
At power-on, power should be supplied to the IC’s power supply pins according to the following sequence:
2
first to pin 29 (I L VDD), then to pin 19 (DEF/DAC VCC), and finally to pin 40/pin 55 (RGB VCC/YC VCC).
Power to pin 29 should be supplied from pin 19 via zener diode through resister.
If power is not supplied to all the power pins or if power is not supplied in the above sequence, BUS preset
will be unsettled and the IC may not function properly.
Especially, when the frequency of H-out (pin 26) will be unsettled, H deflection output transistor may be
broken.
When this IC will be used on CRT, the frequency of H-out should be controlled by pin 22.
V
H-out output
DEF/DAC VCC
5.2 V (typ.)
Power-on reset (POR) threshold voltage
for bus operation 3.3 V (typ.)
2
I L VDD
Logic operation 1.5 V (typ.)
t
Figure (Note 3) Timing from immediately after power-on to time
at which H-out is output (at Ta = 25°°C)
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Note 4: VCC condition at Power-OFF
2
At power-off, the last pulse of H-out (pin 26) will become unknown, if I L VDD (pin 29) is over 1.7 V at the
timing of H-out stop.
2
I L VDD should be below 1.7 V when DEF/DAC VCC (pin 19) will be 6.2 V, which is the maximum voltage
when H-out stops.
Refer to Figure (Note 4-1).
V
DEF/DAC VCC (pin 19)
6.2 V
H-out stop voltage (max)
2
I L VDD (pin 29)
Figure (Note 4-1)
H-out stop
Power off
below 1.7 V
t
VCC condition at power-off
If it is not in the condition of Figure (Note 4-1), it is recommended that H-out will be made LOW at power-off
by external control like micro-processor ang so on. Refer to Figure (Note 4-2).
DFF/DAC VCC (Pin 19)
6.2 V
TA1316
DEF VCC
Control signal by micro-processor and so on.
H-out
26
Approximately ten
milli seconds or more
Figure (Note 4-2)
Power OFF
Control signal by
micro-processor and so on.
H-out stop
H-out waveform
t
Example how to stop H-out
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Recommended Operating Conditions
Characteristics
Description
Min
Typ.
Max
Board A (Note1)
8.5
8.8
9.1
Boards B and C (Note1)
8.7
9.0
9.3
Pin 29
1.8
2.0
2.2
Y input level
Pins 3 and 8: 100% color bar, including sync (picture
signal: 0.7 Vp-p)
1.0
Color difference signal input level
Pins 4, 5, 9 and 10: 100% color bar, no sync
0.7
Matrix switching voltage
Pin 7
2.0
3.0
5.0
HD/VD input level
Pins 12, 13, 15 and 16
2.0
5.0
9.0
SYNC input level
Pin 14: 100% color bar, including sync
0.9
1.0
1.1
CP
4.7
5.0
9.0
SCP input level
Pin 17
BPP
2.2
2.5
2.8
15.75 kHz
8.0
9.0
9.0
31.5 kHz
5.0
6.0
7.0
33.75 kHz
2.0
3.0
4.0
45 kHz
0
0
1.0
H-AFC
4.0
5.0
9.0
H-BLK
1.7
2.25
2.8
Pins 19, 40 and 55
Supply voltage (VCC)
Horizontal frequency switching
voltage
FBP input level
Unit
V
Vp-p
V
Vp-p
V
Pin 22
Pin 24
H-OUT input current
Pin 26
9.0
15.0
DAC input current
Pins 28 and 36
0.3
1.0
SCL/SDA pull-up voltage
Pins 30 and 31
3.3
5.0
9.0
V
SDA input current
Pin 31
2
mA
Analog RGB input level
Pins 35, 34 and 33: White 100%
0.7
Analog OSD input level
Pins 37, 38 and 39: White 100%
0.7
YS3 switching voltage
Pin 49
1.5
5.0
9.0
YS1/2 switching voltage
Pins 51 and
50
mA
OSD
2.9
5.0
9.0
VSM MUTE
1.1
1.5
1.7
BLK
7.0
9.0
9.0
P-MUTE
2.7
3.2
4.0
HALF TONE
1.2
1.5
1.8
0.78
1
Vp-p
V
YM switching voltage
External V-BLK input current
Note1:
Pin 52
Pin 27
mA
For the parameter values for boards A, B and C, please refer to the table entitled Maximum Ratings.
Electrical Characteristics (VCC = 9 V/2 V, Ta = 25°C, unless otherwise specified)
Current Dissipation
Symbol
Test
Circuit
Min
Typ.
Max
DEF/DAC VCC
ICC1
21.0
24.2
26.9
RGB VCC
ICC2
55.3
63.6
70.8
I L VDD
ICC3
21.0
24.1
26.8
Y/C VCC
ICC4
39.3
45.3
50.3
Pin Name
2
36
Unit
mA
2002-10-04
TA1316AN
Pin Voltage
Test Condition
(1)
(2)
BUS = Preset
SW1 = B, SW2 = B, SW3 = C, SW4 = B, SW5 = B, SW7 = A, SW8~10 = B, SW14 = B, SW20 = ON,
SW23 = B, SW24 = A, SW26 = A, SW33~35 = A, SW37~39 = A, SW54 = OFF, SW56 = ON
Pin No.
Pin Name
Symbol
Test
Circuit
Min
Typ.
Max
2
BPH FILTER
V2
5.5
5.8
6.1
3
Y1 IN
V3
4.7
5.0
5.3
4
Cb/Pb1 IN
V4
4.7
5.0
5.3
5
Cr/Pr1 IN
V5
4.7
5.0
5.3
7
MATRIX SW
V7
2.0
3.0
4.0
8
Y2 IN
V8
4.7
5.0
5.3
9
Cb/Pb2 IN
V9
4.7
5.0
5.3
10
Cr/Pr2 IN
V10
4.7
5.0
5.3
11
COLOR LIMITER
V11
6.65
6.9
7.15
12
VD2 IN
V12
0
0
0.3
13
HD2 IN
V13
0
0
0.3
14
SYNC IN
V14
1.6
2.0
2.4
15
VD1 IN
V15
0
0
0.3
16
HD1 IN
V16
0
0
0.3
17
SCP IN
V17
3.9
4.4
4.9
20
AFC FILTER
V20
5.8
6.5
7.2
21
HVCO
V21
5.0
5.3
5.6
23
H CURVE CORRECTION
V23
2.2
2.5
2.8
33
ANALOG B IN
V33
3.65
3.95
4.25
34
ANALOG G IN
V34
3.65
3.95
4.25
35
ANALOG R IN
V35
3.65
3.95
4.25
37
ANALOG OSD B IN
V37
3.65
3.95
4.25
38
ANALOG OSD G IN
V38
3.65
3.95
4.25
39
ANALOG OSD R IN
V39
3.65
3.95
4.25
46
B S/H
V46
3.5
4.0
4.5
47
G S/H
V47
3.5
4.0
4.5
48
R S/H
V48
3.5
4.0
4.5
49
YS3
V49
0.0
0.1
0.2
50
YS2
V50
0.0
0.1
0.2
51
YS1
V51
0.0
0.1
0.2
52
YM
V52
0.0
0.1
0.2
53
ABCL IN
V53
5.85
6.1
6.35
54
VSM OUT
V54
4.2
4.4
4.6
56
APL FILTER
V56
4.8
5.0
5.2
37
Unit
V
2002-10-04
TA1316AN
Luminance Block
Characteristics
Y input dynamic range
Black detection level shift
Black stretch amplifier maximum gain
Black stretch start point 1
Black stretch start point 2
Dynamic ABL detection voltage
Dynamic ABL sensitivity
Black level correction
Dynamic Y γ correction point
Dynamic Y γ gain
Static Y γ dark area gain
DC restoration gain
DC restoration start point
DC restoration limit point
Sharpness control peak frequency
Sharpness control range
Symbol
Test
Circuit
Test Condition
Min
Typ.
Max
Unit
DRY
0.7
1.0
1.5
Vp-p
VB
−15
−5
5
VB3
35
45
55
2.5
3.0
3.5
31
34
37
50
53
56
0
5
10
19
24
29
30
50
70
80
100
120
190
220
250
0.005
0.02
0.29
0.32
0.35
7.0
8.5
10
17
20
23
0.5
1.5
2.5
2
3.5
5
3
5
7
2
3
4
dB
dB
(Note P01)
GBS
PBST1
PBST2
PBS1
PBS2
DV001
DV010
DV100
SDAMIN
SDAMAX
BLC
PDGP00
PDGPA
PDGPB
PDGPC
GDG
(Note P09)
(Note P10)
GSG
ADT100
ADT135
ADT65
VDT0
VDT1
PDTL11
PDTL10
PDTL01
PDTL00
(Note P02)
mV
(Note P03)
IRE
(Note P04)
(Note P05)
(Note P06)
(Note P07)
IRE
1.3
1.7
2.2
1.1
1.2
1.2
1.35
1.5
0.55
0.7
0.85
−5
0
5
47
51
55
54
57
61
67
71
75
74
78
82
74
78
82
FAP00
12.2
13.5
14.9
FAP01
8.5
9.5
10.5
FAP10
6.5
7.3
8.1
FAP11
4.2
4.7
5.2
GMAX00
13
16
18
GMIN00
−15
−8
−4
GMAX01
14
17
19
GMIN01
−20
−14
−7
GMAX10
14
17
19
GMIN10
−25
−16
−7
GMAX11
14
18
20
GMIN11
−30
−20
−8
%
MHz
(Note P14)
38
times
%
(Note P13)
IRE
IRE
0.9
(Note P12)
mV
V/V
(Note P08)
(Note P11)
dB
dB
2002-10-04
TA1316AN
Characteristics
Sharpness control center
characteristic
YNR characteristic
Control of SRT response to 2T pulse
input
VSM peak frequency
VSM gain
Threshold voltage of VSM muting
Response time for VSM muting
VSM limit
Delay time from Y input to R output
Y delay time switch
Transfer distortion correction
Symbol
Test
Circuit
GCEN00
GCEN01
GCEN10
Test Condition
(Note P15)
Min
Typ.
Max
7.5
10
12.5
8
11
13
8
11
13
GCEN11
9
12
14
GYNRT00
−15
−8
−4
GYNRF00
−3
−1
1
GYNRT01
−20
−12
−8
GYNRF01
−3
−1
1
GYNRT10
−20
−13
−8
GYNRF10
−2
−0.5
1.5
GYNRT11
−25
−12
−8
GYNRF11
−2
0
2
TSRT00
0.05
0.4
0.7
TSRT01
0.5
1
2
TSRT10
1.5
2
4
TSRT11
3.5
5
7
FVSM
15
19
22.8
GV000
−39
−35
GV001
2
3
4
GV010
5.5
6.5
7.5
GV011
9.5
11
12
GV100
12.5
13.8
15
GV101
14.5
16
17.5
GV110
15.5
16.8
18.5
GV111
17.5
18.6
19.5
VSR49
0.62
0.72
0.85
VSR50
0.62
0.72
0.85
VSR51
0.62
0.72
0.85
TVM49A
0
30
100
TVM49B
0
30
100
TVM50A
0
30
100
TVM50B
0
30
100
TVM51A
0
30
100
TVM51B
0
30
100
VLU
0.58
0.65
0.75
VLD
0.55
0.62
0.75
TYR
96
120
144
YDLA
3
5
7
YDLB
7
10
13
YDLC
11
15
19
GAMIN
−5
−3.2
−2.0
GBMIN
1
2
3.5
GAMAX
0.3
1.0
1.7
GBMA X
−3.0
−1.5
−1.0
(Note P16)
(Note P17)
(Note P23)
39
MHz
V
ns
(Note P20)
(Note P22)
dB
dB
(Note P19)
(Note P21)
dB
dB
(Note P18)
Pins 49, 50 and 51
Unit
Vp-p
ns
ns
dB
2002-10-04
TA1316AN
Characteristics
Color detail enhancer
Y detail frequency
Symbol
Test
Circuit
GCDE00
GCDE01
GCDE10
GCDE11
FYD00
FYD01
FYD10
FYD11
Test Condition
Min
Typ.
Max
5.5
6.8
8
5.5
6.8
8
5.5
6.8
8
5.5
6.8
8
4.4
5.5
6.6
2.9
3.7
4.5
11.6
14.5
17.4
8
10
12
GYDMAX00
6
9
12
GYDMAX01
7
10
13
GYDMAX10
2.5
5.5
8.5
GYDMAX11
3
6
9
3.5
6.5
9.5
4
7
10
GYDCEN10
−2
0.8
2
GYDCEN11
−1
1
2
(Note P24)
APACON white peak limiter
GYDCEN01
(Note P25)
dB
GYDMIN00
0
1.5
3
GYDMIN01
0
2
4
GYDMIN10
−8
−5
−2
GYDMIN11
−18
−15
−12
GWPL1
−10
−7
−4
GWPL2
−7
−4.8
−2
GWPL3
−5
−2.3
−0.5
(Note P26)
40
dB
MHz
GYDCEN00
Y detail control range
Unit
dB
2002-10-04
TA1316AN
Color Difference 1/YUV Input and Matrix Block
Characteristics
Symbol
Test
Circuit
Color difference signal input dynamic
range
DBB
DRR
TRMAX
Test Condition
Min
Typ.
Max
0.7
0.9
1
0.7
0.9
1
25
29
33
−37
−33
−29
27
31
35
−36
−32
−28
0.65
0.72
0.8
TRMIN
TBMAX
TBMIN
VMSW
FB00
3.6
4.5
5.4
FB01
4.6
5.8
7.0
FB10
6.8
8.5
10.2
FR00
3.6
4.5
5.4
FR01
4.6
5.8
7.0
FR10
6.8
8.5
10.2
GSB00CEN
5
8
11
GSB00MAX
9
12
15
GSB01CEN
2
5
8
GSB01MAX
5
8
11
GSB10CEN
1
2
5
GSB10MAX
1
3
6
GSR00CEN
5
8
11
GSR00MAX
9
12
15
GSR01CEN
2
5
8
GSR01MAX
5
8
11
GSR10CEN
1
2
5
GSR10MAX
1
3
6
Delay time from Cb1 input to B output
TB
104
130
156
Delay time from Cr1 input to R output
TR
104
130
156
Color difference signal tint control
characteristic
Matrix fast SW threshold voltage
Color SRT peak frequency
Color SRT gain
Pin 7
Vp-p
°
V
MHz
(Note S01)
41
Unit
dB
ns
2002-10-04
TA1316AN
Characteristics
Color difference signal amplitude
correction
YUV gain
Symbol
Test
Circuit
GCBDY1
Test Condition
Min
Typ.
Max
0.3
0.5
0.7
GCBDY2
0.7
1.0
1.3
GCBDY3
0.7
1.0
1.3
GCBBS1
0.2
0.4
0.6
GCBBS2
−1.0
−0.6
−0.5
GCBBS3
−3.6
−3.3
−3.0
GCRDY1
0.3
0.5
0.7
GCRDY2
1.4
1.6
1.8
GCRDY3
1.4
1.6
1.8
GCRBS1
0.1
0.3
0.5
GCRBS2
−1.2
−1.0
−0.8
GCRBS3
−3.7
−3.3
−2.9
GY00
4.5
5.5
6
GY01
4.5
5.5
6
GY10
4.5
5.5
6
GY11
4.5
5.5
6
GBA
0.2
0.4
0.5
GBB
1.0
1.1
1.3
GBC
1.0
1.1
1.3
GRA
0.8
1.0
1.2
GRB
−1.6
−1.4
−1.2
GRC
−3.4
−3.2
−3.0
(Note S02)
(Note S03)
42
Unit
dB
dB
2002-10-04
TA1316AN
Color Difference 2 Block
Characteristics
Color difference signal contrast
adjustment characteristic
Color adjustment characteristic
R-Y relative phase and amplitude
G-Y relative phase and amplitude
Color difference signal half-tone
characteristic
Color γ characteristic
Color limiter characteristic
High bright color gain
Symbol
Test
Circuit
∆VuCY
∆vcCY+
∆vcCY−
θRMAX
Test Condition
Min
Typ.
Max
Unit
15.5
17.0
18.5
dB
3.6
4.6
5.6
−35
−25
−18
109
111.5
114
θRCNT
98.5
101
103.5
θRMIN
88
90
92
VR/VBMAX
0.82
0.85
0.88
VR/VBCNT
0.68
0.71
0.74
VR/VBMIN
0.51
0.54
0.57
θGMAX
253
256
259
θGCNT
245
248
251
θGMIN
229
232
235
VG/vBMAX
0.35
0.38
0.41
VG/vBCNT
0.30
0.33
0.36
VG/vBMIN
0.25
0.28
0.31
GHTRY
0.47
0.50
0.53
GHTGY
0.47
0.50
0.53
GHTBY
0.47
0.50
0.53
Vγ1
0.09
0.23
0.37
Vγ2
0.26
0.40
0.54
Vγ3
0.44
0.58
0.72
∆γ
0.60
0.70
0.80
CLT0
1.45
1.65
1.85
CLT1
1.80
2.00
2.20
HBC1
0.02
0.04
0.06
(Note A01)
(Note A02)
(Note A03)
(Note A04)
(Note A05)
(Note A06)
43
dB
°
times
°
times
times
Vp-p
Vp-p
times
2002-10-04
TA1316AN
Text Block
Characteristics
AC gain
(Y1in~R/G/B out)
AC gain axial difference
Frequency characteristic
Symbol
Test
Circuit
GR
GG
GB
GG/R
GB/R
GfR
GfG
GfB
Frequency characteristics
GfCb
(Cb1/Cr1in~R/G/B out)
GfCr
Unicolor adjustment characteristic
∆Vu
VbrMAX
VbrCNT
VbrMIN
Vwps1
Vwps2
Vbps
N41
N42
(Y1in~R/G/B out)
Brightness adjustment characteristic
White peak slice level
Black peak slice level
RGB output S/N
Half-tone characteristic
Half-tone ON voltage
Vertical blanking pulse output level
Horizontal blanking pulse output level
Blanking pulse delay time
Sub-contrast variable range
Test Condition
(Note T01)
Flat gain
(−3 dB point at 10 MHz)
(Note T02)
(Note T03)
Min
Typ.
Max
3.39
3.80
4.28
3.39
3.80
4.28
3.39
3.80
4.28
0.94
1.00
1.06
0.94
1.00
1.06
24
30
24
30
24
30
11
14.5
11
14.5
15.5
16.5
17.5
4.10
4.45
4.80
3.05
3.40
3.75
1.95
2.30
2.65
2.30
2.45
2.65
2.70
2.90
3.10
1.05
1.20
1.35
−55
−49
−55
−49
(Note T04)
(Note T05)
(Note T06)
N43
−55
−49
GHT1
0.45
0.50
0.55
GHT2
0.45
0.50
0.55
VHT
0.65
0.85
1.05
VVR
0.30
0.80
1.30
VVG
0.30
0.80
1.30
VVB
0.30
0.80
1.30
VHR
0.30
0.80
1.30
VHG
0.30
0.80
1.30
VHB
0.30
0.80
1.30
tdON
0.00
0.30
tdOFF
0.08
0.30
∆vsu+
2.1
2.6
3.1
∆vsu−
−4.0
−3.5
−3.0
CUT+
0.42
0.47
0.52
CUT−
0.42
0.47
0.52
Cutoff voltage variable range
(Note T07)
Pin 52
(Note T08)
44
Unit
times
MHz
MHz
dB
V
Vp-p
V
dB
times
V
V
V
µs
dB
V
2002-10-04
TA1316AN
Characteristics
Drive adjustment variable range
Output voltage at picture muting
P mute ON voltage
Output voltage at blue back
Pin 53 input impedance
ACL characteristic
ABL point
ABL gain
Symbol
Test
Circuit
DRR1+
Test Condition
Min
Typ.
Max
2.5
3.0
3.5
DRR1−
−5.5
−5.0
−4.5
DRR2+
2.5
3.0
3.5
Unit
DRR2−
−5.5
−5.0
−4.5
DRG1+
2.5
3.0
3.5
DRG1−
−5.5
−5.0
−4.5
DRG2+
2.5
3.0
3.5
DRG2−
−5.5
−5.0
−4.5
DRG3+
2.5
3.0
3.5
DRG3−
−5.5
−5.0
−4.5
DRB1+
2.5
3.0
3.5
DRB1−
−5.5
−5.0
−4.5
DRB2+
2.5
3.0
3.5
DRB2−
−5.5
−5.0
−4.5
DRB3+
2.5
3.0
3.5
DRB3−
−5.5
−5.0
−4.5
MURD
1.5
1.7
1.9
MUGD
1.5
1.7
1.9
MUBD
1.5
1.7
1.9
VMUTE
1.90
2.15
2.40
BBR
1.0
1.2
1.4
BBG
1.0
1.2
1.4
BBB
1.1
1.25
1.4
Vp-p
Zin
24
30
36
kΩ
ACL1
−7.5
−5.5
−3.5
ACL2
−16.0
−14.5
−12.0
ABLP1
0.10
0.15
0.20
ABLP2
−0.01
0.04
0.09
ABLP3
−0.07
−0.02
0.03
ABLP4
−0.17
−0.12
−0.07
ABLP5
−0.27
−0.22
−0.17
ABLP6
−0.36
−0.31
−0.26
ABLP7
−0.44
−0.39
−0.34
ABLP8
−0.50
−0.45
−0.40
ABLG1
−0.06
−0.02
0.00
ABLG2
−0.17
−0.12
−0.07
ABLG3
−0.34
−0.29
−0.24
ABLG4
−0.52
−0.47
−0.42
ABLG5
−0.68
−0.63
−0.59
ABLG6
−0.85
−0.80
−0.75
ABLG7
−1.01
−0.96
−0.91
ABLG8
−1.09
−1.04
−0.99
(Note T09)
Pin 52
V
V
V
(Note T10)
(Note T11)
(Note T12)
(Note T13)
45
dB
dB
V
V
2002-10-04
TA1316AN
Characteristics
RGB output mode
Y-OUT γ characteristic
Blue stretch circuit characteristic
Forced blanking input threshold
voltage
ACB pulse phase and amplitude
IK input amplitude
IK input cover range
Symbol
Test
Circuit
V43R
Test Condition
Min
Typ.
Max
2.15
2.40
2.65
V42R
0.30
0.80
1.30
V41R
0.30
0.80
1.30
V43G
0.30
0.80
1.30
V42G
2.15
2.40
2.65
V41G
0.30
0.80
1.30
V43B
0.30
0.80
1.30
V42B
0.30
0.80
1.30
V41B
2.15
2.40
2.65
γ1
56
66
76
γ2
72
82
92
∆1
0.49
1.24
1.99
∆2
−1.67
−0.92
−0.17
∆3
−4.59
−3.84
−3.09
BSPmin
55.0
60.0
65.0
BSPcnt
92.5
97.5
102.5
BSPmax
107
112
117
BSGmin
1.75
2.25
2.75
BSGcnt
6.4
7.4
8.4
BSGmax
9
10
11
VBLKIN
5.50
6.00
6.50
θACBR
1
θACBG
2
(Note T14)
Unit
V
IRE
(Note T15)
dB
IRE
(Note T16)
Pin 52
θACBB
3
VACB1R
0.04
0.07
0.10
VACB1G
0.04
0.07
0.10
VACB1B
0.04
0.07
0.10
VACB2R
0.16
0.21
0.26
VACB2G
0.16
0.21
0.26
VACB2B
0.16
0.21
0.26
VACB3R
0.41
0.46
0.51
VACB3G
0.41
0.46
0.51
VACB3B
0.41
0.46
0.51
IKR
0.73
0.93
1.13
IKG
0.73
0.93
1.13
IKB
0.73
0.93
1.13
DIKin+
3.00
3.30
3.60
DIKin−
−0.50
−0.30
−0.10
dB
V
H
(Note T17)
(Note T18)
(Note T19)
46
Vp-p
Vp-p
V
2002-10-04
TA1316AN
Characteristics
Analog RGB gain
Analog RGB gain triaxial difference
Analog RGB frequency characteristic
Analog RGB input dynamic range
Analog RGB white peak slice level
Analog RGB black peak limit level
RGB contrast adjustment
characteristic
Analog RGB brightness adjustment
characteristic
Analog RGB mode switch voltage
Analog RGB mode switching transfer
characteristic
Text ACL characteristic
Analog OSD gain
Analog OSD gain triaxial difference
Symbol
Test
Circuit
GTXR
GTXG
GTXB
GTXG/R
GTXB/R
GfTXR
GfTXG
GfTXB
Test Condition
(Note T20)
Min
Typ.
Max
3.03
3.40
3.83
3.03
3.40
3.83
3.03
3.40
3.83
0.94
1.00
1.06
0.94
1.00
1.06
30
35
30
35
30
35
DR35
0.80
1.20
1.50
DR34
0.80
1.20
1.50
DR33
0.80
1.20
1.50
TXVWPSR
2.30
2.55
2.80
TXVWPSG
2.30
2.55
2.80
TXVWPSB
2.30
2.55
2.80
VBPSR
1.05
1.20
1.35
VBPSG
1.05
1.20
1.35
VBPSB
1.05
1.20
1.35
∆vuTXR
15.5
16.5
18.5
∆vuTXG
15.5
16.5
18.5
At −3dB
(Note T21)
(Note T22)
(Note T23)
∆vuTXB
15.5
16.5
18.5
VbrTXmax
3.0
3.2
3.4
VbrTXcnt
2.5
2.7
2.9
VbrTXmin
2.0
2.2
2.4
VTXON
0.65
0.85
1.05
τRYS
15
50
tPRYS
20
50
∆tRYS
0
10
τFYS
10
50
tPRYS
30
50
∆tRYS
0
10
TXACL1
−2.00
−1.00
−0.05
TXACL2
−7.5
−5.5
−3.5
TXACL3
−6.0
−4.0
−2.0
TXACL4
−17
−15
−13
GOSDR
2.95
3.30
3.70
GOSDG
2.95
3.30
3.70
GOSDB
2.95
3.30
3.70
GOSDG/R
0.94
1.00
1.06
GOSDB/R
0.94
1.00
1.06
(Note T24)
Pin 49
(Note T25)
(Note T26)
(Note T27)
47
Unit
times
MHz
Vp-p
Vp-p
V
dB
V
V
ns
dB
times
2002-10-04
TA1316AN
Characteristics
Analog OSD frequency characteristic
Analog OSD input dynamic range
Analog OSD input white peak slice
level
Analog OSD input black peak limit
level
Analog OSD contrast adjustment
characteristic
Analog OSD brightness adjustment
characteristic
Analog OSD mode switch voltage
Symbol
Test
Circuit
GfOSDR
GfOSDG
GfOSDB
DR35
Test Condition
At −3dB
Min
Typ.
Max
35
40
35
40
35
40
0.80
1.20
1.50
0.80
1.20
1.50
DR34
DR33
0.80
1.20
1.50
OSDVWPSR
2.45
2.70
2.95
OSDVWPSG
2.45
2.70
2.95
OSDVWPSB
2.45
2.70
2.95
OSDVBPSR
1.30
1.45
1.60
OSDVBPSG
1.30
1.45
1.60
OSDVBPSB
1.30
1.45
1.60
VUOSDR11
0.58
0.64
0.71
VUOSDG11
0.58
0.64
0.71
VUOSDB11
0.58
0.64
0.71
VUOSDR10
0.47
0.53
0.59
VUOSDG10
0.47
0.53
0.59
VUOSDB10
0.47
0.53
0.59
VUOSDR01
0.32
0.38
0.46
VUOSDG01
0.32
0.38
0.46
VUOSDB01
0.32
0.38
0.46
VUOSDR00
0.21
0.23
0.25
VUOSDG00
0.21
0.23
0.25
VUOSDB00
0.21
0.23
0.25
VbrOSD0
2.20
2.40
2.60
VbrOSD1
2.05
2.25
2.45
VbrOSD2
1.95
2.15
2.35
VbrOSD3
1.80
2.00
2.20
VOSDON1
Pin 51
2.05
2.30
2.55
VOSDON2
Pin 50
2.05
2.30
2.55
(Note T28)
(Note T29)
(Note T30)
Unit
MHz
Vp-p
Vp-p
V
Vp-p
V
(Note T31)
V
48
2002-10-04
TA1316AN
Characteristics
Analog OSD mode switching transfer
characteristic
OSD ACL characteristic
OSD blending characteristic
Crosstalk between inputs
Symbol
Test
Circuit
τRYS1
Test Condition
Min
Typ.
Max
15
50
tPRYS1
20
50
∆tPRYS1
0
10
τFYS1
10
50
tPRYS1
30
50
∆tPRYS1
0
10
τRYS2
15
50
tPRYS2
20
50
∆tPRYS2
0
10
τFYS2
10
50
tPRYS2
30
50
∆tPRYS2
0
10
tROSD
20
50
tPROSD
15
50
∆tPROSD
0
10
τFOSD
20
50
tPROSD
20
50
∆tPROSD
0
10
OSDACL1
0.00
OSDACL2
OSDACL3
OSDACL4
(Note T32)
0.00
−8.0
−5.5
−3.0
−17
−15
−13
α41TV1
−7
−6
−5
α42TV1
−7
−6
−5
α43TV1
−7
−6
−5
α41TV2
−4
−3
−2
α42TV2
−4
−3
−2
α43TV2
−4
−3
−2
α41TV3
−55
−50
α42TV3
−55
−50
α43TV3
−55
−50
α41OSD1
−6.5
−5.5
−4.5
α42OSD1
−6.5
−5.5
−4.5
α43OSD1
−6.5
−5.5
−4.5
α41OSD2
−12.0
−10.5
−9.0
α42OSD2
−12.0
−10.5
−9.0
α43OSD2
−12.0
−10.5
−9.0
α41OSD3
−40
−30
α42OSD3
−40
−30
α43OSD3
−40
−30
−50
−40
(Note T33)
(Note T34)
49
Unit
ns
dB
dB
dB
2002-10-04
TA1316AN
Deflection Block
Parameter
Symbol
Test
Circuit
SPH
HD1PH/2PH
HDDUTY1
HDDUTY2
HDDUTY3
HDDUTY4
Min
Typ.
Max
Unit
(Note HA01)
0.55
0.65
0.75
µs
(Note HA02)
0.58
0.68
0.78
µs
0.5
2.0
62
67
72
99.5
98
47.5
52.5
57.5
VthS00
4
8.5
14
VthS01
14
20
26
VthS10
24
30
36
VthS11
34
40
46
VthHD1/2
0.7
0.8
0.9
∆HSFT−
9.5
10.5
11.5
∆HSFT+
9.5
10.5
11.5
∆H#23
2.9
3.4
3.9
CPS0
3.1
3.8
4.5
CPW0
2.0
2.5
3.0
CPV0
4.7
5.0
5.3
CPS1
0
0.7
1.5
CPW1
1.9
2.4
2.9
CPV1
4.7
5.0
5.3
CPS2
3.2
4.2
5.2
CPW2
2.2
2.7
3.2
CPV2
4.7
5.0
5.3
HBPS0a
4.3
6.3
8.9
HBPS0b
4.3
6.3
8.9
HBPV0
2.2
2.5
2.8
HBPS1a
1.5
3.5
5.9
HBPS1b
1.5
3.5
5.9
HBPV1
2.2
2.5
2.8
V
HBPs45a
6.0
8.5
11.5
%
HBPs45b
6.0
8.5
11.5
%
HBPsv45
2.2
2.5
2.8
%
FBP threshold
VthFBP
2.5
3.0
3.5
V
HVCO oscillation start voltage
VVCO
Monitor pin 21 = VCC
3.5
4.0
4.5
V
H-OUT start voltage
VHON
Monitor pin 26 = VCC
4.5
5.2
6.2
V
Sync input horizontal sync phase
HD 1/2 input horizontal sync phase
Polarity detection range
Sync input threshold amplitude
HD 1/2 input threshold voltage
Horizontal picture phase adjustment
variable range
Curve correction amount
Clamp pulse phase, width and level
Black peak detection pulse phase and
level
Test Condition
(Note HA03)
%
%
(Note HA04)
(Note HA05)
%
(Note HA06)
(Note HA07)
Vp-p
%
%
V
%
(Note HA08)
V
%
V
%
V
%
(Note HA09)
(Note HA10)
50
2002-10-04
TA1316AN
Parameter
H-OUT pulse duty
Symbol
Test
Circuit
TH00A
Min
Typ.
Max
39
41
43
TH01A
38
40
42
TH10A
38
40
42
TH00B
45
47
49
TH01B
44.5
46.5
48.5
TH10B
45
47
49
F00
15.59
15.75
15.91
F01
31.19
31.5
31.82
33.41
33.75
34.09
Horizontal free-running frequency
F11
44.52
45.0
45.48
F00MIN
14.48
14.78
15.08
F00MAX
16.37
16.70
17.03
F01MIN
28.97
29.56
30.15
F01MAX
32.72
33.39
34.06
F10MIN
30.91
31.54
32.17
F10MAX
34.91
35.62
36.33
F11MIN
43.20
44.00
44.80
F11MAX
47.85
48.65
49.45
BH00
176
220
264
BH01
352
440
528
BH10
376
470
564
BH11
520
650
780
V26H
4.8
5.1
5.2
V26L
0.1
0.3
V22L
1.3
1.5
1.7
V22M
4.3
4.5
4.7
V22H
7.3
7.5
7.7
VDAC2H
TEST = (00), DAC2 = (1)
8.5
9.0
VDAC2L
TEST = (00), DAC2 = (0)
0.3
0.7
VPW
4
4.5
5
000
VPt0
1278
1281
1284
001
VPt1
846
849
852
010
VPt2
722
725
728
H-OUT output voltage
Horizontal oscillation frequency pin (pin
22) control voltage threshold
DAC2
VP output pulse width
Hz/0.1 V (Note HB04)
%
kHz
V
V
H
(Note V01)
VPt3
657
660
663
VPt4
610
613
616
101
VPt5
360
363
366
110
VPt6
304
307
310
TVPULL
47
48
49
011
100
Vertical minimum pull-in range
(Note HB03)
(Note HB05)
Unit
kHz
(Note HB02)
Horizontal oscillation control sensitivity
Vertical free-running
(maximum pull-in range)
(Note HB01)
F10
Horizontal oscillation frequency
variable range
DAC switching voltage
Test Condition
(Note V02)
51
H
H
2002-10-04
TA1316AN
Parameter
000
001
010
Vertical black peak detection
pulse
011
100
101
110
Vertical blanking stop phase
High
VP output voltage
Low
Delay time from SYNC input to VP
output
Symbol
Test
Circuit
VBPP0E
VBPP0S
VBPP1E
51
52
53
VBPP1S
729.5
730.5
731.5
VBPP2E
49.5
50.5
51.5
VBPP2S
599.5
600.5
601.5
VBPP3E
49.5
50.5
51.5
VBPP3S
544.5
545.5
546.5
VBPP4E
51
52
53
VBPP4S
499.5
500.5
501.5
VBPP5E
51
52
53
VBPP5S
289.5
290.5
291.5
VBPP6E
51
52
53
VBPP6S
239.5
240.5
241.5
VBLKMIN
15
16
17
VBLKMAX
45
46
47
V27VPH
4.6
5.0
5.4
V27VPL
0.1
0.5
15.75 kHz
10.0
11.6
13.4
31.5 kHz
4.8
5.8
7.6
33.75 kHz
4.4
5.4
7.2
45 kHz
3.1
4.1
5.9
Test Condition
Min
Typ.
Max
51
52
53
Unit
1099.5 1100.5 1101.5
(Note V03)
H
(Note V04)
Pin 27 voltage
52
H
V
µs
2002-10-04
TA1316AN
Parameter
000
001
010
Compression BLK1
(start phase)
011
100
101
110
000
001
010
Compression BLK2
011
(stop phase)
100
101
110
External vertical blanking insert
current
Symbol
Test
Circuit
CBLK1000min
Test Condition
Min
Typ.
Max
1087
1088
1089
CBLK1000max
1117
1118
1119
CBLK1001min
719
720
721
CBLK1001max
749
750
751
CBLK1010min
591
592
593
CBLK1010max
621
622
623
CBLK1011min
527
528
529
CBLK1011max
557
558
559
CBLK1100min
487
488
489
CBLK1100max
517
518
519
CBLK1101min
279
280
281
CBLK1101max
309
310
311
CBLK1110min
223
224
225
CBLK1110max
253
254
255
CBLK2000min
49
50
51
CBLK2000max
77
78
79
CBLK2001min
49
50
51
CBLK2001max
77
78
79
CBLK2010min
49
50
51
CBLK2010max
77
78
79
CBLK2011min
49
50
51
CBLK2011max
77
78
79
CBLK2100min
49
50
51
CBLK2100max
77
78
79
CBLK2101min
49
50
51
CBLK2101max
77
78
79
CBLK2110min
49
50
51
CBLK2110max
77
78
79
IEXTBLK
520
625
780
Pin 27, current
53
Unit
H
H
µA
2002-10-04
TA1316AN
Test Conditions for Luminance
Common Test Conditions for Luminance
(1)
(2)
(3)
(4)
SW4 = SW5 = B, SW7 = OPEN, SW8~SW10 = B, SW20 = ON, SW23 = B, SW33∼SW39 = A, SW54 = 54 = ON
After sending bus control data with preset values, set ACB MODE to off (00) and SYNC INPUT-SW to sync input (10).
Input sync signal [signal in sync with input signal used for testing, except for sweep signal] to pin 14 (SYNC IN). Set horizontal frequency to that of pin 14.
Set pin 7 to open, Y/color difference signal input mode (YUV INPUT MODE) to Through (10), SYNC SEP-LEVEL to 20% (01) and vertical free-running frequency
to 307H (110).
Test Conditions
Note No.
P01
Parameter
Black detection level shift
Test Method (test conditions: VCC = 9 V/2 V, Ta = 25° ± 3°C)
SW mode
SW1
SW2
SW3
B
C
C
SW56
OPEN (1) Connect external power supply (PS) to pin 3 and monitor pins 2 and 56.
(2) Set black stretch point 1 to off (000) and black detection level (BDL) to 0 IRE (1).
(3) Increase PS voltage from 4.95 V in 1-mV steps. When pin 2 picture period (High) goes Low, measure pin 56
DC differential VB.
(4) Set black detection level (BDL) to 3 IRE (0).
(5) Repeat step (3) above and measure pin 56 DC differential VB3.
Pin 56 waveform
VB, VB3
Pin 2 waveform
P02
Black stretch amplifier maximum gain
B
A
A
OPEN (1) Set SW2 to A (maximum gain) and input 500-kHz sine wave to TPA.
(2) Adjust signal amplitude to 0.1 Vp-p using pin 3.
(3) Set black stretch point 1 to off (000) and measure pin 56 amplitude VA.
(4) Set black stretch point 1 to 001 (black stretch on) and measure pin 56 amplitude VB.
(5) Calculate GBS using the following formula.
GBS = 20 × "og (VB ÷ VA) [dB]
54
2002-10-04
TA1316AN
Test Conditions
Note No.
P03
Parameter
Black stretch start point 1
Test Method (test conditions: VCC = 9 V/2 V, Ta = 25° ± 3°C)
SW mode
SW1
SW2
SW3
B
A
C
SW56
OPEN (1) Set SW2 to A (maximum gain) and black stretch start point 1 to off (000).
(2) Connect external power supply (PS) to pin 3, increase voltage from V3, and plot resulting pin 56 voltage
change S1. Define pin 56 voltages when V3 and V3 + 0.7 V are applied as V0 and V100.
(3) Set black stretch start point 1 to 001 (minimum), increase PS voltage from V3 as in (2) above and plot
resulting pin 56 voltage change S2.
(4) Set black stretch start point 1 to maximum (111), repeat step (2) above and plot resulting pin 56 voltage
change S3.
(5) Determine S1 and S2 intersection VBST1 and S1 and S3 intersection VBST2 using the graph below. Calculate
PBST1 and PBST2 using the following formulae.
VZ [V] = V100 [V] − V0 [V]
PBST1 [(IRE)] = [(VBST1 [V] − V56 [V]) ÷ VZ] × 100 (IRE)
PBST2 [(IRE)] = [(VBST2 [V] − V56 [V]) ÷ VZ] × 100 (IRE)
Pin 56
S3
VBST2
S1
VBST1
S2
V56
Pin 3
55
2002-10-04
TA1316AN
Test Conditions
Note No.
P04
Parameter
Black stretch start point 2
Test Method (test conditions: VCC = 9 V/2 V, Ta = 25° ± 3°C)
SW mode
SW1
SW2
SW3
SW56
B
A
A
ON
(1) Set black stretch start point 1 to off (000), picture mute to off (P-MODE: Normal1 (000)) and apply 0 V to #1.
Input TG7 linearity to TPA, adjust amplitude using pin 3 as shown below, set UNI-COLOR to center
(1000000), then measure pin 43 (R OUT) amplitude VP43.
(2) Set black stretch start point 1 to 001 (black stretch on), connect external power supply (PS) to pin 56 and
monitor pin 43 (R OUT).
(3) When black stretch start point 2 data is a minimum (00), determine black stretch start point differential ∆V00
for PS = V56 (APL = 0%) and for PS = V56 + 1.0 V (APL = 100%), as shown below. (Using oscilloscope,
adjust input waveform so that amplitude (gradient) is same as that of output waveform in VAR. Compare
waveforms and determine point where output waveform bends.)
(4) When black stretch start point 2 data is a maximum (11), determine black stretch start point differential ∆V11
as in (3) above.
(5) Calculate using the following formulae.
PBS1 = (∆V00/VP43) × 100
PBS2 = (∆V11/VP43) × 100
LINEARITY
APL 100%
0.7 Vp-p
∆V***
APL 0%
0.3 Vp-p
Pin 3 waveform (linear)
56
Pin 43 (R OUT)
2002-10-04
TA1316AN
Test Conditions
Note No.
P05
Parameter
Dynamic ABL detection voltage
Test Method (test conditions: VCC = 9 V/2 V, Ta = 25° ± 3°C)
SW mode
SW1
SW2
SW3
B
A
C
SW56
OPEN (1) Set ABL GAIN to minimum (000), DYNAMIC ABL GAIN to maximum (111) and black stretch point 1 to off
(000).
(2) Connect external power supply (PS) to pin 53 and decrease voltage from 6.5 V.
(3) When DYNAMIC ABL POINT bus data is 000, 001, 110 and 100, repeat step (2) above. When pin 56 picture
period goes Low, measure PS voltages V000, V001, V010 and V100.
(4) Determine voltage differential between V000 and V001 (∆V001), between V000 and V010 (∆V010), and between
V000 and V100 (∆V100).
DV*** = V000 − V001 (V010, V100)
Pin 56 undetected
Pin 56 detected
Pin 2 waveform
57
2002-10-04
TA1316AN
Test Conditions
Note No.
P06
Parameter
Dynamic ABL sensitivity
Test Method (test conditions: VCC = 9 V/2 V, Ta = 25° ± 3°C)
SW mode
SW1
SW2
SW3
SW56
B
A
C
ON
(1) Set black stretch point 1 to off (000) and connect external power supply (PS) to pin 53.
(2) When DYNAMIC ABL POINT is a minimum (000) and DYNAMIC ABL GAIN is a minimum (000) or a
maximum (111), plot pin 53 voltage characteristic in relation to pin 56 voltage.
(3) Determine gradients SDAMIN and SDAMAX using the graph below.
SDAMIN = ∆Y/∆X SDAMAX = ∆Y/∆X
Pin 56
10%
∆Y
100%
10%
∆X
58
Pin 53
2002-10-04
TA1316AN
Test Conditions
Note No.
P07
Parameter
Black level correction
Test Method (test conditions: VCC = 9 V/2 V, Ta = 25° ± 3°C)
SW mode
SW1
SW2
SW3
B
A
C
SW56
OPEN (1) Set black stretch point 1 to off (000) and monitor pin 56.
(2) Set black level correction (BLC) to on (1), measure ∆V1 (mV) and calculate BLC using the following formula.
(VZ: P09 value)
3
BLC = [∆V1/(VZ × 10 )] × 100 (IRE)
Picture period
∆V1 [mV]
59
2002-10-04
TA1316AN
Test Conditions
Note No.
P08
Parameter
Dynamic Y γ correction point
Test Method (test conditions: VCC = 9 V/2 V, Ta = 25° ± 3°C)
SW mode
SW1
SW2
SW3
A
B
A
SW56
OPEN (1) Connect external power supply (PS1) to pin 3 and (PS2) to TP1. Set PS2 to 0 V.
(2) Set dynamic Y γ point switch (DYNCγ-POINT) to 19 IRE (00), dynamic Y γ gain VS dark area (DYNCγ GAIN
VS DARK AREA) to off (000) and dynamic Y γ dark area gain to off (00).
(3) When PS1 is increased from V3 to V3 + 0.7 V, set V3 to 0 V and plot voltage change in pin 56. (V3 is pin
voltage of pin 3.)
(4) Set DYNCγ GAIN VS DARK AREA to maximum (111), static Y γ dark area gain (STATICγ-GAIN) to maximum
(11) and PS2 to 1 V.
(5) As in step (3) above, increase PS1 from V3 to V3 + 0.7 V and plot pin 56 voltage change.
(6) Set DYNCγ-POINT to 21 IRE (01), 25 IRE (10) and 30 IRE (11), increase PS1 from V3 to V3 + 0.7 V and plot
pin 56 voltage change.
(7) Determine dynamic Y γ point when DYNCγ-POINT is set to 19 IRE (00) as VDGP00 using the graph below.
Also determine dynamic Y γ point when DYNCγ-POINT is set to 21 IRE (01) as VDGP01; to 25 IRE (10) as
VDGP10; to 30 IRE (10) as VDGP11.
(8) Using VDGP01, VDGP10, and VDGP11 thus determined, calculate PDGP00, PDGP01, PDGP10 and PDGP11
using the following formulae.
PDGP00 = (VDGP00/0.7) × 100
PDGP01 = (VDGP01/0.7) × 100
PDGP10 = (VDGP10/0.7) × 100
PDGP11 = (VDGP11/0.7) × 100
PDGPA = PDGP01 − PDGP00
PDGPB = PDGP10 − PDGP00
PDGPC = PDGP11 − PDGP00
Pin 56 voltage [V]
ON
OFF
VDGP***
60
100 IRE
Pin 3 voltage
2002-10-04
TA1316AN
Test Conditions
Note No.
P09
Parameter
Dynamic Y γ gain
Test Method (test conditions: VCC = 9 V/2 V, Ta = 25° ± 3°C)
SW mode
SW1
SW2
SW3
A
B
A
SW56
OPEN (1) Connect external power supply (PS1) to pin 3 and (PS2) to TP1. Set PS2 to 0 V.
(2) Set DYNCγ-POINT to 30 IRE (11), DYNCγ GAIN VS DARK AREA to off (000) and STATICγ-GAIN to off (00).
(3) Set PS1 to V3 and determine pin 56 voltage VDGOFF1.
(4) Set PS1 to V3 + 0.16 V and determine pin 56 voltage VDGOFF2.
(5) Set DYNCγ GAIN VS DARK AREA to maximum (111), PS2 to 1 V and determine pin 56 voltage VGDON.
(6) Calculate GDG using the following formula.
GDG = 20 × "og (VDGON − VDGOFF1/VDGOFF2 − VDGOFF1)
P10
Static Y γ dark area gain
A
B
A
OPEN (1) Connect external power supply (PS1) to pin 3 and (PS2) to TP1. Set PS2 to 0 V.
(2) Set DYNCγ-POINT to 30 IRE (11), DYNCγ GAIN VS DARK AREA to off (000) and STATICγ-GAIN to off (00).
(3) Set PS1 to V3 and determine pin 56 voltage VSGOFF1.
(4) Set PS1 to V3 + 0.16 V and determine pin 56 voltage VSGOFF2.
(5) Set STATICγ GAIN to maximum (11) and determine pin 56 voltage VSGON.
(6) Calculate GSG using the following formula.
GSG = 20 × "og (VSGON − VSGOFF1/VSGOFF2 − VSGOFF1)
61
2002-10-04
TA1316AN
Test Conditions
Note No.
P11
Parameter
DC restoration gain
Test Method (test conditions: VCC = 9 V/2 V, Ta = 25° ± 3°C)
SW mode
SW1
SW2
SW3
SW56
B
B
C
ON
(1) Set picture mute to off (P-MODE: Normal1 (000)), DC restoration start point to minimum (000) and DC
restoration limit point (DC REST LIMIT) to 100% (11) and connect external power supply PS1 to pin 3.
(2) Measure DC level of pin 43 picture period. When use PS1 at V3 as reference, Set PS1 to V3 + 0.7 V and
adjust DC level to 0.7 V using UNI-COLOR.
(3) Set DC REST RATE to minimum (000) and measure VDT1 and VDT2 when pin 3 is at V3 and at V3 + 0.1 V
(see figure below).
(4) Measure VDT3 when pin 3 is at V3 + 0.1 V. Set DC REST RATE to maximum (111) and measure VDT3.
(5) Set DC restoration rate switch (DCRR-SW) to 100% or less (1) and pin 3 to V3 + 0.1 V, and measure VDT4.
Set DC REST RATE to maximum (111) and measure VDT4.
(6) Calculate ADT100, ADT135 and ADT65 using the following formulae.
ADT100 = (VDT2 [V] − VDT1 [V]) ÷ 0.1 [V]
ADT135 = (VDT3 [V] − VDT1 [V]) ÷ 0.1 [V]
ADT65 = 1 − {(VDT2 [V] − VDT4 [V]) ÷ 0.1 [V]}
V3 [V]
Picture period
V3 + 0.1 V
62
Pin 43 waveform
VDT1
VDT2 VDT3
VDT4
2002-10-04
TA1316AN
Test Conditions
Note No.
P12
Parameter
DC restoration start point
Test Method (test conditions: VCC = 9 V/2 V, Ta = 25° ± 3°C)
SW mode
SW1
SW2
SW3
SW56
B
B
C
ON
(1) Set picture mute to off (P-MODE: Normal1 (000)), DC restoration start point to minimum (000) and DC REST
LIMIT to 100% (11), and connect external power supply PS1 to pin 3.
(2) Measure DC level of pin 43 picture period. Use PS1 at V3 as reference. When PS1 is set to V3 + 0.7 V, adjust
DC level to +1.0 V using UNI-COLOR.
(3) Set DC REST RATE to minimum (000), increase PS1 from V3 and plot voltage relationship between pin 56
(DC voltage) and pin 43 (picture period voltage).
(4) Set DC REST RATE to maximum (111), increase PS1 from V3 and plot voltage relationship between pins 56
and 43.
(5) Set DC REST RATE to maximum (111), DC restoration start point to maximum (111), increase PS1 from V3
and plot voltage relationship between pins 56 and 43.
(6) Calculate VDT0 and VDT1 using the following formulae.
VDT0 = [(VSP0 − V56)/1 V] × 100%
VDT1 = [(VSP1 − V56)/1 V] × 100%
Pin 43
DC restoration start point: 000
DC restoration start point: 111
DC restoration rate: 000
VSP0
VSP1
VPC
63
Pin 56
2002-10-04
TA1316AN
Test Conditions
Note No.
P13
Parameter
DC restoration limit point
Test Method (test conditions: VCC = 9 V/2 V, Ta = 25° ± 3°C)
SW mode
SW1
SW2
SW3
SW56
B
B
C
ON
(1) Set picture mute to off (P-MODE: Normal1 (000)), UNI-COLOR to maximum (1111111) and DC restoration
start point to minimum (000), and connect external power supply PS to pin 56.
(2) Set DC REST RATE to maximum (111).
(3) Increase PS from 5 V, monitor pin 43 and plot DC restoration.
(4) Change DC REST LIMIT and repeat step (3) above. Determine VL11, VL10, VL01 and VL00 using the graph
below. Calculate PDTL11, PDTL10, PDTL01 and PDTL00 using the following formulae.
PDTL11 = [(VL11 − V56)/1.0] × 100%
PDTL10 = [(VL10 − V56)/1.0] × 100%
PDTL01 = [(VL01 − V56)/1.0] × 100%
PDTL00 = [(VL00 − V56)/1.0] × 100%
Pin 43
100% (00)
87% (01)
73% (10)
60% (11)
VL11
VL10
64
VL00
VL01
Pin 56
2002-10-04
TA1316AN
Test Conditions
Note No.
P14
Parameter
Sharpness control range
Test Method (test conditions: VCC = 9 V/2 V, Ta = 25° ± 3°C)
SW mode
SW1
SW2
SW3
SW56
B
B
A
ON
(1) Input sine wave (frequency variable) to TPA.
(2) Set pin 3 amplitude to 20 mVP-P.
(3) Set UNI-COLOR to maximum (1111111), SHR-TRACKING to SRT-GAIN minimum (11), APACON peak
frequency (APACON PEAK f0) to 15 M (00) and color detail enhancer (CDE) to center (10).
(4) Set picture mute to off (P-MODE: Normal1 (000)) and monitor pin 43.
(5) Set picture sharpness (PICTURE-SHARPNESS) to center (1000000) and measure amplitude V100 when
input frequency is 100 kHz.
(6) Set PICTURE-SHARPNESS to maximum (1111111) and measure amplitude VMAX00 when input frequency is
FAP00. Calculate GMAX00 using the following formula.
(7) Set PICTURE-SHARPNESS to minimum (0000000) and measure amplitude VMIN00 when input frequency is
FAP00. Calculate GMIN00 using the following formula.
(8) Set APACON PEAK f0 to 8.8 M (01) and measure amplitudes VMAX01 and VMIN01 as in steps (6) and (7)
when input frequency is FAP01. Calculate GMAX01 and GMIN01 using the following formulae.
(9) Set APACON PEAK f0 to 7.5 M (10) and measure amplitudes VMAX10 and VMIN10 as in steps (6) and (7)
when input frequency is FAP10. Calculate GMAX10 and GMIN10 using the following formulae.
(10) Set APACON PEAK f0 to 5 M (11) and measure amplitudes VMAX11 and VMIN11 as in steps (6) and (7) when
input frequency is FAP11. Calculate GMAX11 and GMIN11 using the following formulae.
GMAX*** = 20 × "og (VMAX*** ÷ V100)
GMIN*** = 20 × "og (VMIN*** ÷ V100)
*:
[dB]
[dB]
When using a spectrum analyzer for monitoring, measure gain for low frequency.
65
2002-10-04
TA1316AN
Test Conditions
Note No.
P15
Parameter
Sharpness control center
characteristic
Test Method (test conditions: VCC = 9 V/2 V, Ta = 25° ± 3°C)
SW mode
SW1
SW2
SW3
SW56
B
B
A
ON
(1) Input sine wave (frequency variable) to TPA.
(2) Set pin 3 amplitude to 20 mVP-P.
(3) Set UNI-COLOR to maximum (1111111), SHR-TRACKING to SRT-GAIN minimum (11), APACON peak
frequency (APACON PEAK f0) to 15 M (00) and color detail enhancer (CDE) to center (10).
(4) Set picture mute to off (P-MODE: Normal1 (000)) and monitor pin 43.
(5) Set PICTURE-SHARPNESS to center (1000000) and measure amplitude V100 when input frequency is 100
kHz.
(6) Measure pin 43 amplitude VCEN00 when input frequency is FAP00 with PICTURE-SHARPNESS set to center
(1000000). Calculate GCEN00 using the following formula.
(7) Set APACON PEAK f0 to 8.8 M (01) and measure amplitude VCEN01 as in step (6) when input frequency is
FAP01. Calculate GCEN01 using the following formula.
(8) Set APACON PEAK f0 to 7.5 M (10) and measure amplitude VCEN10 as in step (6) when input frequency is
FAP10. Calculate GCEN10 using the following formula.
(9) Set APACON PEAK f0 to 5 M (11) and measure amplitudes VCEN11 as in step (6) when input frequency is
FAP11. Calculate GCEN11 using the following formula.
GCEN*** = 20 × "og (VCEN*** ÷ V100)
*:
[dB]
When using a spectrum analyzer for monitoring, measure gain for low frequency.
66
2002-10-04
TA1316AN
Test Conditions
Note No.
P16
Parameter
YNR characteristic
Test Method (test conditions: VCC = 9 V/2 V, Ta = 25° ± 3°C)
SW mode
SW1
SW2
SW3
SW56
B
B
A
ON
(1) Input sine wave (frequency variable) to TPA.
(2) Set pin 3 amplitude to 20 mVP-P.
(3) Set UNI-COLOR to maximum (1111111), SHR-TRACKING to SRT-GAIN minimum (11), APACON peak
frequency (APACON PEAK f0) to 15 M (00) and color detail enhancer (CDE) to center (10).
(4) Set picture mute to off (P-MODE: Normal1 (000)) and monitor pin 43.
(5) Set PICTURE-SHARPNESS to center (1000000) and measure amplitude V100 when input frequency is 100
kHz.
(6) Set YNR to on (1) and PICTURE-SHARPNESS to minimum (0000000). Measure pin 43 amplitude VTRAP00
when input frequency is FAP00 and calculate GYNRT00 using the following formula.
(7) When PICTURE-SHARPNESS is set to 0000011 and measure pin 43 amplitude VFLAT00. Calculate
GYNRF00 using the following formula.
(8) Set APACON PEAK f0 to 8.8 M (01) and measure amplitude VTRAP01 as in step (7) when input frequency is
FAP01. Calculate GTRAP01 using the following formula.
(9) Set APACON PEAK f0 to 7.5 M (10) and measure amplitude VTRAP10 as in step (7) when input frequency is
FAP10. Calculate GTRAP10 using the following formula.
(10) Set APACON PEAK f0 to 5 M (11) and measure amplitude VTRAP11 as in step (7) when input frequency is
FAP11. Calculate GTRAP11 using the following formula.
*:
GYNRT** = 20 × "og (VTRAP**/V100)
[dB]
GYNRF** = 20 × "og (VFLAT**/V100)
[dB]
When using a spectrum analyzer for monitoring, measure gain for low frequency.
67
2002-10-04
TA1316AN
Test Conditions
Note No.
P17
Parameter
Control of SRT response to 2T pulse
input
Test Method (test conditions: VCC = 9 V/2 V, Ta = 25° ± 3°C)
SW mode
SW1
SW2
SW3
SW56
B
B
A
ON
(1) Input 2T pulse (0.7 VP-P) signal to TPA and set picture mute to off (P-MODE: Normal1 (000)), UNI-COLOR to
maximum (1111111), and SHR-TRACKING to SRT-GAIN minimum (11), CDE to center (10) and
PICTURE-SHARPNESS to center (1000000).
(2) Set APACON frequency to 15 M (00) and monitor pin 43.
(3) Measure TSRTMIN00 and VSRTMIN00 as shown in the figure below.
(4) Set SHR-TRACKING to SRT-GAIN maximum (00) and measure TSRTMAX00 and VSRTMAX00.
(5) Set APACON frequency to 8.8 M (01), SHR-TRACKING to SRT-GAIN minimum (11) and maximum (00) as in
step (4) above, and measure TSRTMIN01, VSRTMIN01, TSRTMAX01 and VSRTMAX01.
(6) Set APACON frequency to 7.5 M (10), SHR-TRACKING to SRT-GAIN minimum (11) and maximum (00) as in
step (4) above, and measure TSRTMIN10, VSRTMIN10, TSRTMAX10 and VSRTMAX10.
(7) Set APACON frequency to 5 M (11), SHR-TRACKING to SRT-GAIN minimum (11) and maximum (00) as in
step (4) above, and measure TSRTMIN11, VSRTMIN11, TSRTMAX11 and VSRTMAX11.
(8) Calculate using the following formulae.
TSRT00 = 20 × "og [((VSRTMAX00/TSRTMAX00)/(VSRTMIN00/TSRTMIN00)]
TSRT01 = 20 × "og [(VSRTMAX01/TSRTMAX01)/(VSRTMIN01/TSRTMIN01)]
TSRT10 = 20 × "og [(VSRTMAX10/TSRTMAX10)/(VSRTMIN10/TSRTMIN10)]
TSRT11 = 20 × "og [(VSRTMAX11/TSRTMAX11)/(VSRTMIN11/TSRTMIN11)]
T***
20%
V***
100%
20%
68
2002-10-04
TA1316AN
Test Conditions
Note No.
P18
Parameter
VSM gain
Test Method (test conditions: VCC = 9 V/2 V, Ta = 25° ± 3°C)
SW mode
SW1
SW2
SW3
SW56
B
B
A
ON
(1) Input sine wave of frequency FVSM2 to TPA.
(2) Set picture mute to off (P-MODE: Normal1 (000)), and pin 3 amplitude to 0.02 VP-P.
(3) Vary VSM GAIN from off (000) to maximum (111) and measure pin 54 amplitudes V001, V010, V011, V100,
V101, V110 and V111. Set input amplitude to 0.7 VP-P and measure pin 54 amplitude V000 when VSM GAIN is
OFF (000).
(4) Calculate using the following formulae.
GV000 = 20 × "og (V000/0.7) [dB]
GV001 = 20 × "og (V001/0.02) [dB]
GV010 = 20 × "og (V010/0.02) [dB]
GV011 = 20 × "og (V011/0.02) [dB]
GV100 = 20 × "og (V100/0.02) [dB]
GV101 = 20 × "og (V101/0.02) [dB]
GV110 = 20 × "og (V110/0.02) [dB]
GV111 = 20 × "og (V111/0.02) [dB]
69
2002-10-04
TA1316AN
Test Conditions
Note No.
P19
Parameter
Response time for VSM fast muting
Test Method (test conditions: VCC = 9 V/2 V, Ta = 25° ± 3°C)
SW mode
SW1
SW2
SW3
SW56
B
B
A
ON
(1) Input sine wave of frequency FVSM to TPA.
(2) Set picture mute to off (P-MODE: Normal1 (000)), VSM GAIN to 100 and pin 3 amplitude to 0.1 VP-P. Monitor
pin 54.
(3) Input pulse as shown below to pin 49 and determine response times TVM49A and TVM49B.
(4) Likewise input pulse to pin 50 and determine response times TVM50A and TVM50B.
(5) Likewise input pulse to pin 51 and determine response times TVM51A and TVM51B.
Square wave (50 kHz, 2 VP-P)
2V
VSR49 [V]
Pin 49
waveform
0V
TVM49A
TVM49B
Pin 54
waveform
Mute period
70
2002-10-04
TA1316AN
Test Conditions
Note No.
P20
Parameter
VSM limit
Test Method (test conditions: VCC = 9 V/2 V, Ta = 25° ± 3°C)
SW mode
SW1
SW2
SW3
SW56
B
B
A
ON
(1) Input sine wave of frequency FVSM2 to TPA.
(2) Set picture mute to off (P-MODE: Normal1 (000)), VSM GAIN to 111 and pin 3 amplitude to 0.7 VP-P.
(3) Measure pin 54 amplitudes VLU and VLD [VP-P] as shown below.
VLU
VLD
71
2002-10-04
TA1316AN
Test Conditions
Note No.
P21
Parameter
Delay time from Y input to R output
Test Method (test conditions: VCC = 9 V/2 V, Ta = 25° ± 3°C)
SW mode
SW1
SW2
SW3
SW56
B
B
A
ON
(1)
Set picture mute to off (P-MODE: Normal1 (000)), UNI-COLOR to maximum (1111111), SHR-TRACKING to
SRT-GAIN minimum (11) and input 2T pulse signal (STD) to TPA.
(2) Set PICTURE-SHARPNESS to center (1000000).
(3) Determine TYR by monitioring pins 43 and 3 as shown below.
2T pulse (STD)
Pin 3
50%
50%
Pin 43
72
TYR
2002-10-04
TA1316AN
Test Conditions
Note No.
P22
Parameter
Y delay time change
Test Method (test conditions: VCC = 9 V/2 V, Ta = 25° ± 3°C)
SW mode
SW1
SW2
SW3
SW56
B
B
A
ON
(1)
Set picture mute to off (P-MODE: Normal1, 000), UNI-COLOR to maximum (1111111) and SHR-TRACKING
to SRT-GAIN minimum (11), and input T2 pulse signal (approx. 0.7 Vp-p) to TPA.
(2) Set picture sharpness to center (1000000).
(3) Monitor pin 3 and pin 43, and determine the time difference YDL00 for each signal at the 50% point as shown
below.
(4) Set Y/C-DL1 to +5 ns (1) and determine YDL01.
(5) Set Y/C-DL1 to +0 ns (0) and Y/C-DL2 to +10 ns (1), and determine YDL10.
(6) Set Y/C-DL1 to +5 ns (1) and Y/C-DL2 to +10 ns (1), and determine YDL11.
(7) Determine YDLA, YDLB and YDLC as follows:
YDLA = YDL01 − YDL00
T2 pulse signal
approx. 0.7 Vp-p
YDLB = YDL10 − YDL00
YDLC = YDL11 − YDL00
#43
#3
50%
50%
YDL00
YDL01
YDL10
YDL11
73
2002-10-04
TA1316AN
Test Conditions
Note No.
P23
Parameter
Transfer distortion correction
Test Method (test conditions: VCC = 9 V/2 V, Ta = 25° ± 3°C)
SW mode
SW1
SW2
SW3
SW56
B
B
A
ON
(1) Input multi-burst signal (frequency equivalent to 4.2 MHz) of signal A to TPA. Set picture mute to off
(P-MODE: Normal1 (000)), UNI-COLOR to maximum (1111111), SHR-TRACKING to SRT-GAIN minimum
(11) and CDE to minimum (00).
(2) Set PICTURE-SHARPNESS to
flat (near DEC[24]), APACON
PEAK f0 to 5 M (11) and monitor
pin 43.
Signal
A
(3) Input sine wave signal A (approx.
4.2 MHz) becomes signal B on
pin 43 as shown at right.
Determine SA and SB.
SA
(4) When Y-GROUP DELAY
CORRECTION is set to minimum
(0000), signal A becomes signal
C on pin 43. Determine SAMIN
and SBMIN.
Signal
B
SB
(5) When Y-GROUP DELAY
CORRECTION is set to
maximum (1111), signal A
becomes signal D on pin 43.
Determine SAMAX and SBMAX.
(6) Calculate using the following formulae.
Signal
C
SAMIN
GAMIN = 20 × "og (SAMIN/SA) [dB]
SBMIN
GBMIN = 20 × "og (SBMIN/SB) [dB]
GAMAX = 20 × "og (SAMAX/SA)
[dB]
GBMAX = 20 × "og (SBMAX/SB)
[dB]
SAMAX
Signal
D
SAMAX
Note: The input sine wave starts and ends within the picture period. It is like a burst signal, not a continuous wave.
74
2002-10-04
TA1316AN
Test Conditions
Note No.
P24
Parameter
Color detail enhancer
Test Method (test conditions: VCC = 9 V/2 V, Ta = 25° ± 3°C)
SW mode
SW1
SW2
SW3
SW56
B
B
A
ON
(1) Set picture mute to off (P-MODE: Normal1 (000)), UNI-COLOR to maximum (1111111), SHR-TRACKING to
SRT-GAIN minimum (11), COLOR to center (1000000), color limiter level (CLT) to 2 Vp (1) and C-SRT-FREQ
to 4.5 M (10). Input SWEEP signal to TPA and set pin 3 amplitude to 20 mVP-P. Set SW4 to A. Input signal
(pin 4 amplitude: 0.2 VP-P) to TP4 as shown in the figure below.
(2) Set PICTURE-SHARPNESS to center (1000000) and Y DETAIL CONTROL to center (10000), and monitor
pin 41 using a spectrum analyzer.
(3) Set low-frequency area to 0dB when CDE is set to minimum (00) and measure peak level GCDEMIN.
(4) Set low-frequency area to 0dB when CDE is set to maximum (11) and measure peak level GCDEMAX.
(5) Calculate using the following formula.
GCDE00 = GCDEMAX00 − GCDEMIN00
(6) Set APACON PEAK f0 to 15 M (00), 8.8 M (01), 7.5 M (10) and 5 M (11), and measure peak levels GCDE00,
GCDE01, GCDE10 and GCDE11.
Output gain [dB]
max
0.2 Vp-p
min
0 dB
BLK period
Picture period
Input frequency [MHz]
75
2002-10-04
TA1316AN
Test Conditions
Note No.
P25
Parameter
Y detail control range
Test Method (test conditions: VCC = 9 V/2 V, Ta = 25° ± 3°C)
SW mode
SW1
SW2
SW3
SW56
B
B
A
ON
(1) Set picture mute to off (P-MODE: Normal1 (000)), UNI-COLOR to maximum (1111111), SHR-TRACKING to
SRT-GAIN minimum (11) and CDE to center (10). Input SWEEP signal to TPA.
(2) Set pin 3 amplitude to 20 mVP-P.
(3) Set PICTURE-SHARPNESS to minimum (0000000) and Y DETAIL CONTROL to maximum (11111), and
monitor pin 43 using a spectrum analyzer.
(4) Set low-frequency area to 0dB. Set APACON PEAK f0 to 15 M (00), 8.8 M (01), 7.5 M (10) and 5 M (11), and
measure peak levels GYDMAX00, GYDMAX01, GYNMAX10 and GYDMAX11.
(5) Set Y DETAIL CONTROL to center (10000) and measure peak levels GYDCEN00, GYDCEN01, GYDCEN10 and
GYDCEN11.
(6) Set Y DETAIL CONTROL to minimum (00000) and measure peak levels GYDMIN00, GYDMIN01, GYNDIN10
and GYDMIN11.
76
2002-10-04
TA1316AN
Test Conditions
Note No.
P26
Parameter
APACON white peak limiter
Test Method (test conditions: VCC = 9 V/2 V, Ta = 25° ± 3°C)
SW mode
SW1
SW2
SW3
SW56
B
B
A
ON
(1) Set picture mute to off (P-MODE: Normal1 (000)), UNI-COLOR to 1101000, SHR-TRACKING to SRT-GAIN
maximum (00) and CDE to maximum (11). Input T pulse signal (0.7 VP-P) to TPA.
(2) Set PICTURE-SHARPNESS to maximum (111111) and APACON PEAK f0 to 5 M (11), and monitor pin 43.
(3) When APACON white peak limiter is off (000), measure positive spike amplitude VWPLOFF1.
(4) When APACON white peak limiter is at maximum (111), measure positive spike amplitude VWPLMAX1.
(5) Set UNI-COLOR to center (1000000). When APACON white peak limiter is off (000) and at maximum (111),
measure positive spike amplitudes VWPLOFF2 and VWPLMAX2.
(6) Set UNI-COLOR to minimum (0000000). When APACON white peak limiter is off (000) and at maximum
(111), measure positive spike amplitudes VWPLOFF3 and VWPLMAX3.
(7) Calculate using the following formulae.
GWPL1 = 20 × "og (VWPLMAX1/VWPLOFF1)
[dB]
GWPL2 = 20 × "og (VWPLMAX2/VWPLOFF2)
[dB]
GWPL3 = 20 × "og (VWPLMAX3/VWPLOFF3)
[dB]
VWPLMAX
77
VWPLOFF
2002-10-04
TA1316AN
Test Conditions for Color Difference Signal 1/YUV Input and Matrix
Common Test Conditions for Color Difference Signal 1/YUV Input and Matrix
(1)
(2)
(3)
(4)
SW1 = B, SW2 = B, SW20 = ON, SW33∼SW39 = A, SW54 = OPEN, SW56 = OPEN
Send BUS control data with preset values.
Set ACB MODE to off (0) and high bright color (HI BRT) to off (0).
Input sync signal [signal in sync with input signal for testing, except for SWEEP signal] to pin 14 (SYNC IN) and set SYNC-INPUT to (10).
Test Conditions
Note No.
S01
Parameter
Color SRT gain
Test Method (test conditions: VCC = 9 V/2 V, Ta = 25° ± 3°C)
SW mode
SW3
SW4
SW5
C
A
A
SW8
SW9
SW10
B
B
B
SW7
OPEN (1) Set Y mute to on (P-MODE: Y-MUTE (001)), YUV INPUT MODE to Through (10), BRIGHTNESS to center
(10000000), COLOR to center (1000000) and UNI-COLOR to maximum (1111111).
―
(2) Input 2T pulse signal to TP4 and set pin 4 amplitude to 350 mVP-P.
―
(3) Monitor pin 41 output waveform. When C-SRT-FREQ is 5 MHz (00), measure edge gradients SB00MIN,
SB00CEN and SB00MAX when COLOR SRT GAIN is at minimum (000), center (100) and maximum (111) as
in shown in the figure below. Set SB00MIN to 0 dB, determine GSB00CEN = 20 × "og (SB00CEN/SB00MIN)
and GSB00MAX = 20 × "og (SB00MAX/SB00MIN).
(4) Repeat step (3) above, setting C-SRT-FREQ to 6.7 MHz (01) and 10 MHz (10), and measure edge gradients
when COLOR SRT GAIN is at minimum (000), center (100) and maximum (111). Determine GSB01CEN,
GSB10CEN, GSB01MAX and GSB10MAX.
(5) Input 2T pulse signal to TP5 and set pin 5 amplitude to 350 mVP-P.
(6) Monitor pin 43 output waveform. When C-SRT-FREQ is 5 MHz (00), measure edge gradients SR00MIN,
SR00CEN and SR00MAX when COLOR SRT GAIN is at minimum (000), center (100) and maximum (111) as
shown in the figure below. Set SR00MIN to 0dB, determine GSR00CEN = 20 × "og (SR00CEN/SR00MIN)
and GSR00MAX = 20 × "og (SR00MAX/SR00MIN).
(7) Repeat step (3) above,
setting C-SRT-FREQ to
6.7 MHz (01) and 10
MHz (10), and measure
edge gradients when
COLOR SRT GAIN is at
minimum (000), center
(100) and maximum
(111). Determine
GSR01CEN, GSR10CEN,
GSR01MAX and
GSR10MAX.
78
T***
Gradient
S*** = V***/T***
10%
V***
100%
10%
2002-10-04
TA1316AN
Test Conditions
Note No.
S02
Parameter
Color difference signal amplitude
correction
Test Method (test conditions: VCC = 9 V/2 V, Ta = 25° ± 3°C)
SW mode
SW3
SW4
SW5
C
A
A
SW8
SW9
SW10
B
B
B
SW7
OPEN (1) Input 100-kHz sine wave to TP4 and set pin 4 amplitude to 0.2 VP-P.
SW56 (2) Set Y mute to OFF (P-MODE: Normal1 (000)), YUV INPUT MODE to Through (10), BRIGHTNESS to center
(10000000), COLOR to center (1000000), UNI-COLOR to maximum (1111111), Y/C GAIN COMP1 to
OPEN
minimum (00), Y/C GAIN COMP2 to minimum (00), black stretch point 1 to off (000), dynamic Y γ point to 30
IRE (11) and SW1 to A. Apply 0 V to TP1 using external power supply PS1 and 5.16 V to pin 3 using PS2.
(3) Monitor pin 41 output waveform and measure amplitude VBDY0.
(4) Set Y/C GAIN COMP1 to maximum (11) and measure pin 41 amplitude VBDY1.
(5) Set DYNCγ GAIN VS DARK AREA to maximum (111), STATICγ-GAIN to maximum (11) and external power
supply PS1 to 1 V, and measure pin 41 amplitude VBDY2.
(6) Set Y/C GAIN COMP2 to maximum (11) and measure pin 41 amplitude VBDY3.
(7) Set Y/C GAIN COMP1 to minimum (00), Y/C GAIN COMP2 to minimum (00), DYNCγ GAIN VS DARK AREA
to minimum (000), STATICγ-GAIN to minimum (00), PS1 to 0 V, PS2 to 5 V and SW2 to A. Measure pin 41
amplitude VBBS0.
(8) Set Y/C GAIN COMP1 to maximum (11) and measure pin 41 amplitude VBBS1.
(9) Set black stretch point 1 to maximum (111) and measure pin 41 amplitude VBBS2.
(10) Set Y/C GAIN COMP2 to maximum (11) and measure pin 41 amplitude VBBS3.
(11) Calculate using the following formulae.
GCBDY1 = 20 × "og (VBDY1/VBDY0) GCBDY2 = 20 × "og (VBDY2/VBDY0)
GCBDY3 = 20 × "og (VBDY3/VBDY0) GCBBS1 = 20 × "og (VBBS1/VBBS0)
GCBBS2 = 20 × "og (VBBS2/VBBS0) GCBBS3 = 20 × "og (VBBS3/VBBS0)
(12) Input 100-kHz sine wave to TP5, set pin 5 amplitude to 0.2 VP-P, repeat steps (2) to (11) above and
determine GCRDY1, GCRDY2, GCRDY3, GCRSB1, GCRSB2 and GCRSB3.
79
2002-10-04
TA1316AN
Test Conditions
Note No.
S03
Parameter
YUV gain
Test Method (test conditions: VCC = 9 V/2 V, Ta = 25° ± 3°C)
SW mode
SW3
SW4
SW5
A/C
A/B
A/B
SW8
SW9
SW10
B
B
B
SW7
OPEN (1) Set picture mute to off (P-MODE: Normal1 (000)), BRIGHTNESS to maximum (11111111), COLOR to center
(1000000) and UNI-COLOR to maximum (1111111).
―
(2) Set SW3 to A, and SW4 and SW5 to B; input a 100-kHz sine wave to TPA and set pin 3 amplitude to 0.2
―
VP-P.
(3) Set SW56 to open, YUV INPUT MODE to Y/Cb/Cr (00), Y/Pb/Pr (01), Through (10) and Y/U/V (11). Measure
pin 56 amplitudes, VY00, VY01, VY10 and VY11.
(4) Set SW3 to C, and SW4 to A and SW5 to B, input 100-kHz sine wave to TP4 and set pin 4 amplitude to 0.2
VP-P.
(5) Set YUV INPUT MODE to Y/Cb/Cr (00), Y/Pb/Pr (01), Through (10) and Y/U/V (11). Measure pin 41
amplitudes VB00, VB01, VB10 and VB11.
(6) Set SW3 to C, and SW4 and SW5 to A; input a 100-kHz sine wave to TP5 and set pin 5 amplitude to 0.2
VP-P.
(7) Set YUV INPUT MODE to Y/Cb/Cr (00), Y/Pb/Pr (01), Through (10) and Y/U/V (11). Measure pin 43
amplitudes VR00, VR01, VR10 and VR11.
(8) Calculate using the following formulae.
GY00 = 20 × "og (VY00/0.2) GY01 = 20 × "og (VY01/0.2)
GY10 = 20 × "og (VY10/0.2) GY11 = 20 × "og (VY11/0.2)
GBA = 20 × "og (VB01/VB00) GBB = 20 × "og (VB10/VB00)
GBC = 20 × "og (VB11/VB00)
GRA = 20 × "og (VR01/VR00) GRB = 20 × "og (VR10/VR00)
GRC = 20 × "og (VR11/VR00)
80
2002-10-04
TA1316AN
Test Conditions for Color Difference Signal 2
Test Conditions
Note No.
Parameter
SW3
A01
Color difference signal
contrast adjustment
characteristic
Test Method (test conditions: VCC = 9 V/2 V, Ta = 25° ± 3°C)
SW mode
C
SW4
SW5
SW33
SW34
SW35
SW37
SW38
SW39
A
A
A
A
A
A
A
A
or
or
(2) Input signal 3 (f0 = 100 kHz, picture period amplitude = 0.23 VP-P) to pin 5.
B
B
(3) Vary UNI-COLOR to maximum (7F), center (40) and minimum (00) and
measure pin 43 picture period amplitudes VuCYMAX, VuCYCNT and VuCYMIN.
(1) Set BRIGHTNESS to maximum and sub-address (12) data to F0.
(4) Determine in decibels amplitude ratio ∆VuCY of UNI-COLOR maximum to
minimum.
(5) Repeat steps (2) and (4) changing input to pin 4 (picture period amplitude = 0.2
VP-P), and measure pin 41 output.
A02
Color adjustment
characteristic
C
A
A
or
or
(2) Input signal 3 (f0 = 100 kHz, picture period amplitude = 0.115 VP-P) to pin 5.
B
B
(3) Vary COLOR to maximum (7F), center (40) and minimum (01), and measure
pin 43 picture period amplitudes VCCYMAX, VCCYCNT and VCCYMIN.
A
A
A
A
A
A
(1) Set BRIGHTNESS to maximum and sub-address (12) data to F0.
(4) Determine in decibels amplitude ratio ∆VCCY of maximum and minimum to
COLOR center.
(5) Repeat steps (2) and (4), changing input to pin 4 (picture period amplitude = 0.1
VP-P), and measure pin 41 output.
81
2002-10-04
TA1316AN
Test Conditions
Note No.
Parameter
SW3
A03
Color difference signal
half-tone characteristic
Test Method (test conditions: VCC = 9 V/2 V, Ta = 25° ± 3°C)
SW mode
C
SW4
SW5
SW33
SW34
SW35
SW37
SW38
SW39
A
A
A
A
A
A
(1) Input signal 3 (f0 = 100 kHz, picture period amplitude = 0.2 VP-P) to pin 5.
A
A
or
or
(2) Measure pin 43 output picture period amplitude vHTARY.
B
B
(3) Apply 1.5 V to pin 52 from external power supply.
(4) Measure pin 43 output picture period amplitude vHTBRY.
(5) Determine GHTRY = vHTBRY/vHTARY.
(6) Repeat steps (1) to (5) above, changing pin to pin 42, and determine GHTGY =
vHTBGY/vHTAGY.
(7) Input signal to pin 4, measure pin 4 and determine GHTBY = vHTBBY/vHTABY.
82
2002-10-04
TA1316AN
Test Conditions
Note No.
A04
Parameter
Color γ characteristic
Test Method (test conditions: VCC = 9 V/2 V, Ta = 25° ± 3°C)
SW mode
SW3
SW4
SW5
SW33
SW34
SW35
SW37
SW38
SW39
C
B
A
A
A
A
A
A
A
(1) Input signal 2 to pin 5.
(2) Increase signal 2 amplitude A. When sub-address (14) data starts with γ
correction, determine pin 43 output signal amplitudes Vγ1, Vγ2 and Vγ3. Graph
the results in the following cases:
(01) − γ off
(03) − γ1 on
(05) − γ2 on
(07) − γ3 on
(3) Determine Vγ where γ starts applying and gradient ratio ∆γ at γ on when
linearity at off is (1).
Pin 43 output amplitude
γOFF
Vγ
γON
Pin 5 input
amplitude
83
2002-10-04
TA1316AN
Test Conditions
Note No.
A05
A06
Parameter
Test Method (test conditions: VCC = 9 V/2 V, Ta = 25° ± 3°C)
SW mode
SW3
SW4
SW5
SW33
SW34
SW35
SW37
SW38
SW39
Color limiter
characteristic
C
B
A
A
A
A
A
A
A
High bright color gain
C
(1) Input signal 2 (picture period amplitude = 0.4 VP-P) to pin 4.
(2) When sub-address (14) data is 00 and 01, measure pin 43 output signal picture
period amplitudes CLT0 and CLT1.
B
A
A
A
A
A
A
A
(1) Input signal 2 (picture period amplitude = 0.2 VP-P) to pin 4.
(2) Adjust COLOR and set pin 41 output picture period amplitude to 1.2 VP-P.
(3) When sub-address (0B) data is 80, measure pin 41 output signal picture period
amplitude V41.
(4) Calculate using the following formula.
84
HBC1 = (1.2 − v41)/1.2
2002-10-04
TA1316AN
Test Conditions for Text
Common Test Conditions for Text
(1)
(2)
Unless otherwise specified, measure bus data using preset values.
Set the following data:
Sub-address (00) to data (02)
Sub-address (05) to data (7F)
Sub-address (09) to data (40)
Sub-address (0B) to data (7F)
Sub-address (0C) to data (82)
Sub-address (12) to data (F0)
Sub-address (19) to data (F8)
Sub-address (1A) to data (E0)
Sub-address (1B) to data (E0)
Sub-address (1D) to data (78)
Sub-address (1E) to data (87)
Test Conditions
Note
No.
T01
Parameter
AC gain
Test Method (test conditions: VCC = 9 V/2 V, Ta = 25° ± 3°C)
SW mode
SW3
SW4
SW5
SW33
SW34
SW35
SW37
SW38
SW39
A
B
B
A
A
A
A
A
A
(1) Input signal 1 (f0 = 100 kHz, amplitude of picture period voltage = 0.2 VP-P) to pin 3.
(2) Measure pins 41, 42 and 43 picture period amplitudes V41, V42 and V43.
(3) Determine AC gain using the following formulae.
GR = V43/0.2 GG = V42/0.2 GB = V41/0.2
T02
Unicolor
adjustment
characteristic
A
B
B
A
A
A
A
A
A
(1) Input signal 1 (f0 = 100 kHz, amplitude of picture period voltage = 0.2 VP-P) to pin 3.
(2) Vary UNI-COLOR data to maximum (7F), center (40) and minimum (00), and measure pin 43
picture period amplitudes VuMAX, VuCNT and VuMIN.
(3) Determine amplitude ratio ∆Vu of VuMAX to VuCNT (in decibels).
T03
T04
Brightness
adjustment
characteristic
A
White peak
slice level
C
B
B
A
A
A
A
A
A
(1) Input signal 2 to pin 3 and set pin 43 picture period amplitude to 1 VP-P.
(2) Vary BRIGHTNESS to maximum (7F), center (80) and minimum (00), and measure pin 43
voltages VbrMAX, VbrCNT and VbrMIN.
B
B
A
A
A
A
A
A
(1) Set SUB-CONTRAST to maximum.
(2) Apply external power supply to pin 3 and increase voltage from 5.8 V.
(3) When pin 43 picture period is clipped, measure pin 43 picture period amplitude voltage VWPS1.
(4) Repeat steps from (1) to (3) above (for VWPS2), changing sub-address (0C) data to 06.
85
2002-10-04
TA1316AN
Test Conditions
Note
No.
T05
T06
Parameter
Test Method (test conditions: VCC = 9 V/2 V, Ta = 25° ± 3°C)
SW mode
SW3
SW4
SW5
SW33
SW34
SW35
SW37
SW38
SW39
Black peak
slice level
C
B
B
A
A
A
A
A
A
RGB output
S/N
C
(1) Apply external power supply to pin 3 and gradually decrease voltage from 5.8 V.
(2) When picture period is clipped, measure Vbps voltage for pins 41, 42 and 43.
B
B
A
A
A
A
A
A
(1) Adjust BRIGHTNESS so that pin 41 picture period voltage is 2.4 V.
(2) Set COLOR to minimum.
(3) Measure pins 41, 42 and 43 picture period noise levels n41, n42 and n43 (VP-P) using
oscilloscope.
(4) Calculate S/N.
N41 = −20 × "og [2.3/(0.2 × n41)]
N42 = −20 × "og [2.3/(0.2 × n42)]
N43 = −20 × "og [2.3/(0.2 × n43)]
T07
Half-tone
characteristic
A
B
B
A
A
A
A
A
A
(1) Input signal 1 (f0 = 100 kHz, amplitude of picture period voltage = 0.2 VP-P) to pin 3.
(2) Measure pin 41 picture period amplitude v41A.
(3) Apply 1.5 V to pin 52 from external power supply.
(4) Measure pin 41 picture period amplitude v41B.
(5) Determine GHT1 = v41B/v41A.
(6) Stop applying voltage to pin 52, set sub-address (1A) data to E2 and measure pin 41 picture
period amplitude v41C.
(7) Determine GHT2 = v41C/v41A.
86
2002-10-04
TA1316AN
Test Conditions
Note
No.
T08
Parameter
Blanking pulse
delay time
Test Method (test conditions: VCC = 9 V/2 V, Ta = 25° ± 3°C)
SW mode
SW3
SW4
SW5
SW33
SW34
SW35
SW37
SW38
SW39
C
B
B
A
A
A
A
A
A
(1)
Apply signal shown in Figure (A) to pin 24 (BLK IN) and determine tdON and tdOFF from
output signal from pins 41, 42 and 43 (Figure (B)).
63.5 µs
(A) Signal applied
to pin 24
tdON
tdOFF
(B) Output signal
from pins 41,
42 and 43.
87
2002-10-04
TA1316AN
Test Conditions
Note
No.
T09
Parameter
Drive
adjustment
variable range
Test Method (test conditions: VCC = 9 V/2 V, Ta = 25° ± 3°C)
SW mode
SW3
SW4
SW5
SW33
SW34
SW35
SW37
SW38
SW39
A
B
B
A
A
A
A
A
A
(1) Input signal 1 (f0 = 100 kHz, picture period amplitude = 0.2 VP-P) to pin 3.
(2) Change sub-address (0D) data to maximum (FE), center (80) and minimum (00), and
measure pin 42 picture period amplitude.
(3) Determine in decibels amplitude ratios of maximum and minimum to drive center (DRGG1+,
DRG1−).
(4) Repeat steps (1) to (3) above, changing sub-address (0E) data to instead, and determine in
decibels pin 41 picture period amplitude ratios (DRB1+, DRB2−).
(5) Repeat steps (1) to (3) above, changing sub-address (0E) data to center (81), and determine
in decibels pin 42 picture period amplitude ratios (DRG2+, DRG2−).
(6) Repeat steps (1) to (3) above, changing sub-address (0E) data to maximum (FF), center (81)
and minimum (01), and determine in decibels pin 41 amplitude ratios (DRB2+, DRB2−).
(7) Repeat steps (1) to (3) above, changing sub-address (0D) data to maximum (FF), center (81)
and minimum (01), and determine in decibels pin 43 amplitude ratios (DRR1+, DRR1−).
(8) Repeat steps (1) to (3) above, setting sub-address (0D) data to 81 and changing sub-address
(0E) data, and determine in decibels pin 41 picture period amplitude ratios (DRB3+, DRB3−).
(9) Repeat steps (1) to (3) above, setting sub-address (0E) data to 81 and changing sub-address
(0D) data to maximum (FF), center (81) and minimum (01), and determine in decibels pin 42
picture period amplitude ratios (DRG3+, DRG3−).
(10) Repeat steps (1) to (3) above, setting sub-address (0D) data to 81 and changing sub-address
(0E) data to maximum (FF), center (81) and minimum (01), and determine in decibels pin 43
picture period amplitude ratios (DRR2+, DRR2−).
88
2002-10-04
TA1316AN
Test Conditions
Note
No.
T10
Parameter
Pin 53 input
impedance
Test Method (test conditions: VCC = 9 V/2 V, Ta = 25° ± 3°C)
SW mode
SW3
SW4
SW5
SW33
SW34
SW35
SW37
SW38
SW39
C
B
B
A
A
A
A
A
A
(1) Connect external power supply, voltmeter and ammeter as shown below. Adjust voltage so
that current value is 0.
(2) Increase pin 53 voltage by 0.2 V and measure current value of ammeter Iin.
(3) Determine Zin53 = 0.2 V/Iin (Ω).
53
−
A
+
Ammeter (µA)
T11
ACL
characteristic
C
B
B
A
A
A
A
A
A
V
Voltmeter
(1) Input signal 1 (f0 = 100 kHz, picture period amplitude = 0.2 VP-P) to pin 3.
(2) Measure pin 43 picture period amplitude vACL1.
(3) Apply external power supply (pin 53 DC voltage − 0.5 V) to pin 53 and measure pin 43
picture period amplitude vACL2.
(4) Apply external power supply (pin 53 DC voltage − 1 V) to pin 53 and measure pin 43 picture
period amplitude vACL3.
(5) Calculate using the following formulae.
ACL1 = −20 × "og (vACL2/vACL1)
ACL2 = −20 × "og (vACL3/vACL1)
89
2002-10-04
TA1316AN
Test Conditions
Note
No.
T12
Parameter
ABL point
Test Method (test conditions: VCC = 9 V/2 V, Ta = 25° ± 3°C)
SW mode
SW3
SW4
SW5
SW33
SW34
SW35
SW37
SW38
SW39
C
B
B
A
A
A
A
A
A
(1) Measure pin 53 DC voltage VABL1.
(2) Set sub-address (1B) data to 1C.
(3) Apply external power supply to pin 53 and decrease voltage from 6.5 V. When pin 43 voltage
starts changing, measure pin 53 voltage VABL2.
(4) Repeat step (3) above, making the following changes:
Set sub-address (1B) data to 3C, 5C, 7C, 9C, BC, DC and FC and measure the following
voltages on pin 53: VABL3, VABL4, VABL5, VABL6, VABL7, VABL8 and VABL9.
T13
ABL gain
C
B
B
A
A
A
A
A
A
(5) ABLP1 = VABL2 − VABL1
ABLP5 = VABL6 − VABL1
ABLP2 = VABL3 − VABL1
ABLP6 = VABL7 − VABL1
ABLP3 = VABL4 − VABL1
ABLP7 = VABL8 − VABL1
ABLP4 = VABL5 − VABL1
ABLP8 = VABL9 − VABL1
(1) Apply external power supply of 6.5 V to pin 53.
(2) Set sub-address (1B) data to 00.
(3) Set BRIGHTNESS to maximum.
(4) Apply external power supply of 4.5 V to pin 53.
(5) Repeat step (3) above, making the following changes:
Set sub-address (1B) data to 00, 04, 08, 0C, 10, 14, 18 and 1C and measure the following
voltages on pin 53: VABL11, VABL12, VABL13, VABL14, VABL15, VABL16, VABL17 and
VABL18.
(6) ABLG1 = VABL11 − VABL10
ABLG2 = VABL12 − VABL10
ABLG3 = VABL13 − VABL10
ABLG4 = VABL14 − VABL10
ABLG5 = VABL15 − VABL10
ABLG6 = VABL16 − VABL10
ABLG7 = VABL17 − VABL10
ABLG8 = VABL18 − VABL10
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2002-10-04
TA1316AN
Test Conditions
Note
No.
T14
Parameter
RGB output
mode
Test Method (test conditions: VCC = 9 V/2 V, Ta = 25° ± 3°C)
SW mode
SW3
SW4
SW5
SW33
SW34
SW35
SW37
SW38
SW39
C
B
B
A
A
A
A
A
A
(1) Adjust BRIGHTNESS so that pin 43 picture period voltage becomes 2.4 V.
(2) Set sub-address (1B) data to 01.
(3) Measure picture period voltages V43R, V42R and V41R on pins 43, 42 and 41 respectively.
(4) Repeat step (3) above, changing sub-address (1B) data to 02, and measure picture period
voltages V43G, V42G and V41G on pins 43, 42 and 41 respectively.
(5) Repeat step (3), changing sub-address (1B) data to 03, and measure picture period voltages
V43B, V42B and V41B on pins 43, 42 and 41 respectively.
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2002-10-04
TA1316AN
Test Conditions
Note
No.
T15
Parameter
Y-OUT γ
characteristic
Test Method (test conditions: VCC = 9 V/2 V, Ta = 25° ± 3°C)
SW mode
SW3
SW4
SW5
SW33
SW34
SW35
SW37
SW38
SW39
A
B
B
A
A
A
A
A
A
(1) Input ramp waveform to pin 3 and adjust input amplitude so that pin 43 picture period
amplitude becomes 2.3 VP-P.
(2) Set sub-address (1C) data to 01.
(3) Adjust input amplitude so that pin 43 picture period amplitude becomes 2.3 VP-P.
(4) According to the figure below, determine in decibels Y-OUT γ correction start points γ1 and γ2
and gradient ratios ∆1, ∆2 and ∆3, which are ratios of gradient at γ-on to gradient at γ-off.
Output amplitude (Y-OUT)
100 IRE
∆3
γ2
∆2
γ1
2.3 Vp-p
∆1
Note: Solid line: γ-off
Dotted line: γ-on
Input amplitude
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2002-10-04
TA1316AN
Test Conditions
Note
No.
T16
Parameter
Blue stretch
circuit
characteristic
Test Method (test conditions: VCC = 9 V/2 V, Ta = 25° ± 3°C)
SW mode
SW3
SW4
SW5
SW33
SW34
SW35
SW37
SW38
SW39
A
B
B
A
A
A
A
A
A
(1) Input ramp signal of 0.7 VP-P to pin 3.
(2) Set SUB-CONTRAST to maximum.
(3) Set sub-address (1F) data to 04.
(4) Set sub-address (1E) data to 00 and determine blue stretch start point BSPmin using pin 41
in the figure below.
(5) Repeat step (4) above, changing sub-address (1E) data to 04 and 07. Determine blue stretch
start points BSPCNT and BSPmax.
(6) Set sub-address (1E) data to 04.
(7) Determine in decibels ratio of gradient at blue stretch on to gradient at blue stretch off, using
pin 41 as shown in the figure below.
(8) Repeat step (7) above, changing sub-address (1F) data to 00 and 07, and determine in
decibels gradient ratios BSGmin and BSGmax.
Note: The blue stretch start point is determined as an IRE value by setting the amplitude from the
output signal pedestal level to the positive side to be 2.3 VP-P = 100 IRE.
Blue stretch on
Output amplitude (Pin 41 output)
Blue stretch off
Blue stretch start point
Input amplitude
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2002-10-04
TA1316AN
Test Conditions
Note
No.
T17
Parameter
ACB pulse
phase and
amplitude
Test Method (test conditions: VCC = 9 V/2 V, Ta = 25° ± 3°C)
SW mode
SW3
SW4
SW5
SW33
SW34
SW35
SW37
SW38
SW39
A
B
B
A
A
A
A
A
A
or
(1) Input signal 1 (f0 = 100 kHz, picture period amplitude = 0.2 VP-P) to pin 3. Adjust DRIVE
GAIN 1/2 so that pin 41/42 picture period amplitude is equal to that of pin 43.
(2) Measure voltage of pins 46, 47 and 48 and apply measured voltages from external power
supply to pins.
C
(3) Set sub-address (02) data to 40.
(4) Determine ACB pulse phase by referencing signal waveform output from pins 43, 42 and 41
as shown in Figure 1 below.
Note: The first picture period after V-BLK ends and FBP input falls is 1H. After each H-BLK, the
phase is 2H, 3H and so on.
ACB pulse amplitude
V-BLK period
Figure 1 RGB output
1H
2H
3H
4H
Figure 2 FBP input (pin 24)
(5) Determine ACB pulse amplitudes VACB1R, VACB1G and VACB1B by referencing signal
waveform output from pins 43, 42 and 41. (Amplitude is based on picture period level at no
input.)
(6) Repeat step (5) above, setting sub-address (02) data to 80, and measure VACB2R, VACB2G
and VACB2B.
(7) Repeat step (5) above, setting sub-address (02) data to C0, and measure VACB3R,
VACB3G and VACB3B.
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2002-10-04
TA1316AN
Test Conditions
Note
No.
T18
Parameter
IK input
amplitude
Test Method (test conditions: VCC = 9 V/2 V, Ta = 25° ± 3°C)
SW mode
SW3
SW4
SW5
SW33
SW34
SW35
SW37
SW38
SW39
A
B
B
A
A
A
A
A
A
or
(1) Input signal 1 (f0 = 100 kHz, picture period amplitude = 0.2 VP-P) to pin 3. Adjust DRIVE
GAIN 1/2 so that pin 41/42 picture period amplitude is equal to that of pin 43.
(2) Set sub-address (02) data to 40.
C
(3) Determine voltage amplitudes while ACB pulse is being applied to pin 45 input signal as
shown in Figure 1 of T19 above.
At 1H = IKR, at 2H = IKG and at 3H = IKB
T19
IK input cover
range
C
B
B
A
A
A
A
A
A
(1) Input signal 1 (f0 = 100 kHz, picture period amplitude = 0.2 VP-P) to pin 3 and adjust DRIVE
GAIN 1/2 so that pin 41/42 picture period amplitude is equal to that of pin 43.
(2) Set sub-address (02) data to 40.
(3) Determine DC voltage of pin 45 during V-BLK (#45VBLK).
(4) Apply external voltage via 10 kΩ and gradually increase the voltage from 0 V.
(5) Determine DC voltage of pin 45 during V-BLK when picture period amplitude of pin 43 has
just started decreasing (#45VBLK+).
(6) Reset the external voltage to 0 V and gradually decrease from 0 V.
(7) Determine DC voltage of pin 45 during V-BLK when picture period amplitude of pin 43 has
just started increasing (#45VBLK−).
(8) DIKin+ = (#45VBLK+) − (#45VBLK)
DIKin− = (#45VBLK−) + (#45VBLK)
T20
Analog RGB
gain
A
B
B
A
A
A
or
or
or
B
B
B
A
A
A
(1) Input signal 1 (f0 = 100 kHz, picture period amplitude = 0.2 VP-P) to pin 3 and adjust DRIVE
GAIN 1/2 so that pin 41/42 picture period amplitude is equal to that of pin 43.
(2) Apply 5 V from external power supply to pin 49.
(3) Input signal 1 (f0 = 100 kHz, picture period amplitude = 0.2 VP-P) to pin 35.
(4) Measure picture period amplitude v43R on pin 43.
(5) Repeat steps (3) and (4), making the following changes.
Input signal 1 to pin 34 and measure pin 42 output (v42G).
Input signal 1 to pin 33 and measure pin 41 output (v41B).
(6) Calculate using the following formulae.
GTXR = v43R/0.2 GTXG = v42G/0.2 GTXB = v41B/0.2
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2002-10-04
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Test Conditions
Note
No.
T21
Parameter
Analog RGB
white peak
slice level
Test Method (test conditions: VCC = 9 V/2 V, Ta = 25° ± 3°C)
SW mode
SW3
SW4
SW5
SW33
SW34
SW35
SW37
SW38
SW39
A
B
B
A
A
A
A
A
A
(1) Apply 5 V from external power supply to pin 49.
(2) Set RGB CONTRAST to maximum (7F).
(3) Apply external power supply to pin 35. Gradually increase voltage from 3.0 V DC. When pin
43 output is clipped, measure picture period amplitude.
(4) Repeat step (3), making the following changes:
Input to pin 34 and measure pin 42 output; input to pin 33 and measure pin 41 output.
T22
Analog RGB
black peak
limit level
A
B
B
A
A
A
A
A
A
(1) Apply 5 V from external power supply to pin 49.
(2) Set RGB CONTRAST to maximum (7F).
(3) Apply external power supply to pin 35. Gradually increase voltage from 4.5 V DC. When pin
43 output is clipped, measure picture period amplitude.
(4) Repeat step (3), making the following changes:
Input to pin 34 and measure pin 42 output; input to pin 33 and measure pin 41 output.
T23
RGB contrast
adjustment
characteristic
A
B
B
A
A
A
or
or
or
(2) Input signal 1 (f0 = 100 kHz, picture period amplitude = 0.2 VP-P) to pin 35.
B
B
B
(3) Change RGB CONTRAST to maximum (7F), center (40) and minimum (00), and measure
picture period amplitude output VuTXR (max, CNT and min) on pin 43.
A
A
A
(1) Apply 5 V from external power supply to pin 49.
(4) Determine in decibels amplitude ratios of maximum and minimum to center.
(5) Repeat steps (3) and (4), making the following changes:
Input to pin 34 and measure picture period amplitude output on pin 42.
Input to pin 33 and measure picture period amplitude output on pin 41.
T24
Analog RGB
brightness
adjustment
characteristic
A
B
B
A
A
A
or
or
or
(2) Apply 5 V from external power supply to pin 49.
B
B
B
(3) Adjust signal 2 amplitude (A) so that pin 43 picture period amplitude becomes 0.5 VP-P.
A
A
A
(1) Input signal 2 to pins 33, 34 and 35.
(4) Change RGB BRIGHTNESS to maximum (FE), center (80) and minimum (00), and measure
picture period voltage output VbrTX (max, CNT and min) on pins 43, 42 and 41 respectively.
T25
Analog RGB
mode
switching
transfer
characteristic
C
B
B
A
A
A
A
A
A
(1) Set RGB BRIGHTNESS to maximum (FE).
(2) Input signal 4 (signal amplitude = 1.5 VP-P) to pin 49.
(3) Measure input/output transfer characteristic using pin 43 in Figure T-2.
(4) Repeat steps (2) and (3) above, making the following changes:
Input to pin 34 and measure pin 42; input to pin 33 and measure pin 41.
(5) Determine maximum inter-axial rise/fall transfer delay time, using the data measured above.
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Test Conditions
Note
No.
T26
Parameter
Text ACL
characteristic
Test Method (test conditions: VCC = 9 V/2 V, Ta = 25° ± 3°C)
SW mode
SW3
SW4
SW5
SW33
SW34
SW35
SW37
SW38
SW39
A
B
B
A
A
B
A
A
A
(1) Apply 5 V from external power supply to pin 49.
(2) Input signal 1 (f0 = 100 kHz, picture period amplitude = 0.2 VP-P) to pin 35.
(3) Measure pin 43 picture period amplitude vTXACL1.
(4) Apply external power supply (pin 53 DC voltage − 0.5 V) to pin 53 and measure picture
period amplitude output vTXACL2 on pin 43.
(5) Apply external power supply (pin 53 DC voltage − 1.0 V) to pin 53 and measure picture
period amplitude output vTXACL3 on pin 43.
(6) TXACL1 = −20 × "og (vTXACL2/vTXACL1)
TXACL2 = −20 × "og (vTXACL3/vTXACL1)
(7) Repeat steps (5) and (6), setting sub-address (10) data to 01 to ascertain TXACL3 and
TXACL4.
T27
Analog OSD
gain
A
B
B
A
A
A
A
A
A
or
or
or
B
B
B
(1) Input signal 1 (f0 = 100 kHz, picture period amplitude = 0.2 VP-P) to pin 3 and adjust DRIVE
GAIN 1/2 so that pin 41/42 picture period amplitude is equal to that of pin 43.
(2) Apply 5 V from external power supply to pins 50 and 51.
(3) Input signal 1 (f0 = 100 kHz, picture period amplitude = 0.2 VP-P) to pin 39.
(4) Adjust output picture period amplitude v43R on pin 43.
(5) Repeat steps (3) and (4), making the following changes:
Input to pin 38 and measure picture period amplitude output on pin 42 (v42G).
Input to pin 37 and measure picture period amplitude output on pin 41 (v41B).
(6) Calculate using the following formulae.
GOSDG = v42G/0.2
GOSDR = v43R/0.2
T28
Analog OSD
white peak
slice level
A
B
B
A
A
A
A
A
A
GOSDB = v41B/0.2
(1) Apply 5 V from external power supply to pins 50 and 51.
(2) Apply external power supply to pin 39 and gradually increase voltage from 4.5 V DC. When
pin 43 output is clipped, measure picture period amplitude.
(3) Repeat step (2), making the following changes:
Input to pin 38 and measure picture period amplitude output on pin 42.
Input to pin 37 and measure picture period amplitude output on pin 41.
T29
Analog OSD
black peak
limit level
A
B
B
A
A
A
A
A
A
(1) Apply 5 V from external power supply to pins 50 and 51.
(2) Apply external power supply to pin 39 and gradually decrease voltage from 4.5 V DC. When
pin 43 output is clipped, measure picture period amplitude.
(3) Repeat step (2), making the following changes.
Input to pin 38 and measure picture period amplitude output on pin 42.
Input to pin 37 and measure picture period amplitude output on pin 41.
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2002-10-04
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Test Conditions
Note
No.
T30
Parameter
Analog OSD
contrast
adjustment
characteristic
Test Method (test conditions: VCC = 9 V/2 V, Ta = 25° ± 3°C)
SW mode
SW3
SW4
SW5
SW33
SW34
SW35
SW37
SW38
SW39
A
B
B
A
A
A
A
A
A
(1) Apply 5 V from external power supply to pins 50 and 51.
or
or
or
(2) Input signal 1 (f0 = 100 kHz, picture period amplitude = 0.2 VP-P) to pin 39.
B
B
B
(3) Change OSD-CONTRAST to (11), (10), (01) and (00) and measure picture period amplitude
outputs VuOSDR (11), (10), (01) and (00) on pin 43.
(4) Repeat steps (2) and (3), making the following changes:
Input to pin 38 and measure picture period amplitude outputs VuOSDG (11), (10), (01) and
(00) on pin 42.
Input to pin 37 and measure picture period amplitude outputs VuOSDB (11), (10), (01) and
(00) on pin 41.
T31
Analog OSD
brightness
adjustment
characteristic
C
B
B
A
A
A
A
A
A
(1) Apply 5 V from external power supply to pins 50 and 51.
(2) Change OSD BRIGHT (sub-address 1D) to (38), (78), (B8) and (F8) and measure picture
period voltage outputs on pins 43, 42 and 41.
Data (38) − VbrOSD0
Data (78) − VbrOSD1
Data (B8) − VbrOSD2
Data (F8) − VbrOSD3
T32
Analog OSD
mode
switching
transfer
characteristic
C
B
B
A
A
A
A
A
A
(1) Set OSD BRIGHT to maximum (11).
(2) Input signal 4 (signal amplitude = 4.5 VP-P) to pin 50.
(3) Measure input/output transfer characteristic, using pin 43 as shown in Figure T-2.
(4) Repeat steps (2) and (3) above, and measure pins 42 and 41.
(5) Determine maximum inter-axial rise/fall transfer delay time, using the data measured above.
(6) Repeat steps (1) to (5), inputting signal 4 (signal amplitude = 4.5 VP-P) to pin 51, and
measure.
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2002-10-04
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Test Conditions
Note
No.
T33
Parameter
OSD ACL
characteristic
Test Method (test conditions: VCC = 9 V/2 V, Ta = 25° ± 3°C)
SW mode
SW3
SW4
SW5
SW33
SW34
SW35
SW37
SW38
SW39
A
B
B
A
A
A
A
A
B
(1) Set sub-address (07) data to 01.
(2) Apply 5 V from external power supply to pins 50 and 51.
(3) Input signal 1 (f0 = 100 kHz, picture period amplitude = 0.2 VP-P) to pin 39.
(4) Measure picture period amplitude vOSDACL1 on pin 43.
(5) Apply external power supply (pin 53 DC voltage − 0.5 V) to pin 53 and measure picture
period amplitude vOSDACL2 on pin 43.
(6) Apply external power supply (pin 53 DC voltage − 1 V) to pin 53 and measure picture period
amplitude vOSDACL3 on pin 43.
(7) OSDACL1 = −20 × "og (vOSDACL2/vOSDACL1)
OSDACL2 = −20 × "og (vOSDACL3/vOSDACL1)
(8) Repeat steps (5) and (6) above, changing sub-address (07) data to 00, and measure
OSDACL3 and OSDACL4.
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2002-10-04
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Test Conditions
Note
No.
T34
Parameter
OSD blending
characteristic
Test Method (test conditions: VCC = 9 V/2 V, Ta = 25° ± 3°C)
SW mode
SW3
SW4
SW5
SW33
SW34
SW35
SW37
SW38
SW39
A
B
B
A
A
A
A
A
B
(1) Input signal 1 (f0 = 100 kHz, picture period amplitude = 0.2 VP-P) to pin 3.
↓
↓
↓
↓
(2) Measure picture period amplitudes v41a, v42a and v43a on pins 41, 42 and 43 respectively.
C
B
B
B
(3) Apply 5 V from external power supply to pin 51.
(4) Measure picture period amplitudes v41b, v42b and v43b on pins 41, 42 and 43 respectively.
(5) Determine in decibels v41b amplitude in relation to v41a; v42b amplitude in relation to v42a;
v43b amplitude in relation to v43a: α41TV1, α42TV1 and α43TV1.
(6) Repeat steps (3) to (5), applying 5 V from external power supply to pin 50, and measure
α41TV2, α42TV2 and α43TV2.
(7) Repeat steps (3) to (5), applying 5 V from external power supply to pins 50 and 51, and
measure α41TV3, α42TV3 and α43TV3.
(8) Set to SW3 to C; SW37, SW38, Sw39 to B.
(9) Input signal 1 (f0 = 100 kHz, picture period amplitude = 0.2 VP-P) to pins 37, 38 and 39.
(10) Apply 5 V from external power supply to pins 50 and 51.
(11) Measure picture period amplitudes v41c, v42c and v43c on pins 41, 42 and 43 respectively.
(12) Apply 5 V from external power supply to pin 50.
(13) Measure picture period amplitudes v41d, v42d and v43d on pins 41, 42 and 43 respectively.
(14) Determine in decibels v41d amplitude in relation to v41c; v42d amplitude in relation to v42c;
v43d amplitude in relation to v43c: α41OSD1, α42OSD1 and α43OSD1.
(15) Repeat steps (12) to (14), applying 5 V from external power supply to pin 51, and measure
α41OSD2, α42OSD2 and α43OSD2.
(16) Repeat steps (12) to (14), applying 5 V from external power supply to pins 50 and 51, and
measure α41OSD3, α42OSD3 and α43OSD3.
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Test Conditions for Deflection
Common Test Conditions for Sync Signal
(Unless otherwise specified, VCC = 9 V/2 V, Ta = 25°C, BUS data = preset values.)
(Unless otherwise specified, SW3 = A, SW14 = A, SW20 = on, SW22 = open, SW23 = B, SW24a = B,
SW24b = open and SW26 = B.)
Note
No.
Parameter
HA01 Sync input horizontal
sync phase
Test Method
(1) Input signal a (as shown in figure below) to TPA. Set sub-address (00) data to 82H.
(2) Determine phase difference S1PH from pin 14 (SYNC IN) input waveform and pin 20 (AFC
filter) waveform.
29.36 µs
Signal a
0.285 V
0.593 µs
SPH
Pin 20 waveform
HA02 HD 1/2 input
(1) Set sub-address (00) data to 40H.
horizontal sync phase
(2) Input signal b (as shown in figure below) to TP16.
(3) Determine phase difference HD1PH from pin 16 (HD1 IN) input waveform and pin 20 (AFC
filter) waveform.
(4) Input signal b to TP13 and set sub-address (00) data to 41H.
(5) Determine phase difference HD2PH as in step (3) above.
31.75 µs
Signal b
1.5 V
2.35 µs
HD1PH, HD2PH
Pin 20 waveform
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Note
No.
Parameter
HA03 Polarity detection
range
Test Method
(1) Set sub-address (00) data to 40H.
(2) Input signal b (as shown in figure below) to TP16.
(3) Decrease signal b duty from 10% (to shorter negative polarity period) and determine signal b
duty (HDDUTY1) when pin 16 input signal phase no longer locks with that of pin 26 (H-OUT).
(4) Increase signal b duty from 10% (to longer negative polarity period) and determine signal b
duty (HDDUTY2) when pin 24 (FBP IN) phase changes in relation to signal b.
(5) Further increase signal b duty (to longer negative polarity period) and determine signal b duty
(HDDUTY3) when pin 16 input signal phase no longer locks with that of pin 26 (H-OUT).
(6) Decrease signal b duty from 90% (to shorter negative polarity period) and determine signal b
duty (HDDUTY4) when pin 24 (FBP IN) phase changes in relation to signal b.
31.75 µs
Signal b
1.5 V
A
B
Duty = A/B × 100% (0%~100%)
HA04 Sync input threshold
amplitude
(1)
Set sub-address (00) to 82H and TEST mode to 01.
(2) Apply external voltage via 20 kΩ to pin 14.
(3) Set external voltage to 0 V and monitor pin 14 pin voltage SYNC_TIP_00.
Also check that pin 28 pin voltage is L.
(4) By increasing external voltage SYNC_OFF_00, monitor pin 14 SYNC IN pin voltage when pin
28 DAC1 pin voltage becomes H.
(5) Determine SYNC input level at SYNC separation level 00 as follows:
Vths00 = (SYNC_OFF_00 − SYNC_TIP_00) /0.286 × 100
(6) Set SYNC separation level from 01 to 10 to 11, and determine Vths01, Vths10 and Vths11.
Vths01 = (SYNC_OFF_01 − SYNC_TIP_01) /0.286 × 100
Vths10 = (SYNC_OFF_10 − SYNC_TIP_10) /0.286 × 100
Vths11 = (SYNC_OFF_11 − SYNC_TIP_11) /0.286 × 100
1H
0.08H
Pin 14
40 IRE
(= 286
mVp-p)
Sync Sepa level
Sync Tip level
Pin 28
(SYNC output Mode)
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2002-10-04
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Note
No.
Parameter
HA05 HD 1/2 input
threshold voltage
Test Method
(1) Set sub-address (00) data to 40H.
(2) Input signal b (as shown in figure below) to TP16.
(3) Increase signal b amplitude from 0 VP-P. When pin 26 (H-OUT) phase locks with that of signal
b, determine signal b amplitude VthHD1.
(4) Input signal b (as shown in figure below) to TP13 and set sub-address (00) data to 41H.
(5) Measure as in step (3) above, and determine signal amplitude VthHD2.
31.75 µs
Signal b
VthDH
2.35 µs
HA06 Horizontal picture
phase adjustment
variable range
(1) Set sub-address (00) data to 40H.
(2) Input signal b (as shown in figure below) to TP16.
(3) Change sub-address (01) data from 80H to 00H and measure pin 26 (H-OUT) waveform
phase change ∆HSFT−.
(4) Change sub-address (01) data from 80H to FEH and measure pin 26 (H-OUT) waveform
phase change ∆HSFT+.
31.75 µs
Signal b
1.5 V
2.35 µs
Pin 26 waveform
Data: 00H
∆HSFT−
Pin 26 waveform
Data: 80H
∆HSFT+
Pin 26 waveform
Data: FEH
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2002-10-04
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Note
No.
Parameter
HA07 Curve correction
Test Method
(1) Set sub-address (00) data to 40H.
(2) Input signal b (as shown in figure below) to TP16.
(3) Connect external power supply to pin 23 (H CURVE CORRECTION). Apply 1.5 V and 3.5 V to
pin 23 and measure the output waveform phase change ∆H#23 on pin 26 (H-OUT).
31.75 µs
Signal b
1.5 V
2.35 µs
Pin 26 waveform
(pin 23 voltage: 1.5 V)
∆H#23
Pin 26 waveform
(pin 23 voltage: 3.5 V)
HA08 Clamp pulse phase,
width and level
(1) Set sub-address (00) data to 40H.
(2) Input signal b (as shown in figure below) to TP16.
(3) Determine clamp pulse phase CPS0, width CPPW0 and output level CPV0 on pin 18 (SCP
OUT) in relation to signal b.
(4) Set sub-address (01) data to 81H. Determine CPS1, CPPW1 and CPV1 as in step (3) above.
(5) Apply no signal input to TP16.
(6) Determine pin 18 clamp pulse phase CPS2, width CPPW2 and output level CPV2 in relation to
pin 24.
31.75 µs
Signal b
1.5 V
2.35 µs
CPS0/1
Pin 18 waveform
CPV0/1
CPW0/1
Pin 24 waveform
CPS2
Pin 18 waveform
CPV2
CPW2
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2002-10-04
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Note
No.
Parameter
Test Method
HA09 Black peak detection (1) Set sub-address (00) data to 40H.
pulse phase and level
(2) Set SW24A to open.
(3) Input signal c (as shown in figure below) to pin 24 (FBP IN).
(4) Determine pin 18 (SCP OUT) black peak detection pulse phase HBPS0a and HBPS0b in
relation to signal c.
(5) Determine output level HBPSV0 from pin 18 (SCP OUT) output waveform.
(6) Set sub-address (02) data to 90H.
(7) Measure as in steps (4) and (5), and determine phases HBPS1a and HBPS1b, and output level
HBPSV1.
(8) Change sub-address (00) data to C0H and sub-address (02) data to 80H, and determine
phases HBPS45a and HBPS45b, and output level HBPSV45.
31.5 µs
4.13 µs
2V
Signal c
0V
HBPS0a/S1a/S45a
HBPS0b/S1b/S45b
Pin 18 waveform
HBPSV0/SV1/SV45
HA10 FBP threshold
(1) Set sub-address (00) data to 40H.
(2) Input signal b (as shown in figure below) to TP16.
(3) Increase amplitude of FBP signal input to pin 24 (FBP IN) from 0 VP-P. When signal b and pin
26 (H-OUT) phases are locked, measure pin 24 input amplitude (VthFBP).
31.75 µs
1.5 V
2.35 µs
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2002-10-04
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Note
No.
Parameter
HB01 H-OUT pulse duty
Test Method
(1) No signal input.
(2) Measure T1 and T2 (as shown in figure below) from pin 26 (H-OUT) output waveform when
sub-address (00) data is 80H and A0H. Determine duties TH00A and TH00B using the
following formula:
TH = T1/(T1 + T2) × 100 %
(3) Set sub-address (00) data to 81H, A1H, 82H and A2H, measure as in step (2) above, and
determine duties TH01A, TH01B, TH10A and TH10B.
T1
T2
Pin 26 waveform
HB02 Horizontal
free-running
frequency
(1) Set SW20 to open.
(2) Set sub-address (00) data to 00H and measure horizontal free-running frequency F00 from pin
26 (H-OUT) output waveform.
(3) Set sub-address (00) data to 40H, 80H and C0H, measure as in step (2) above, horizontal
free-running frequencies F01, F10 and F11.
HB03 Horizontal oscillation
frequency variable
range
(1) Set sub-address (00) data to 00H.
(2) Connect 10-kΩ resistor between pin 20 and VCC. Measure horizontal frequency F00MIN from
pin 26 (H-OUT) output waveform.
(3) Connect 68-kΩ resistor between pin 20 and GND. Measure horizontal frequency F00MAX from
pin 26 (H-OUT) output waveform.
(4) Set sub-address (00) data to 40H, 80H and C0H, and measure as in steps (2) and (3) above,
horizontal frequencies F01MIN, F01MAX, F10MIN, F10MAX, F11MIN and F11MAX.
HB04 Horizontal oscillation
control sensitivity
(1) Set SW20 to open.
(2) Connect external power supply to TP20. Set sub-address (00) data to 00H.
Apply V20 + 0.05 V and V20 − 0.05 V (see HB01) to TP20, and measure frequencies FA and
FB from pin 26 (H-OUT) output waveform. Calculate frequency change rate (BH00) using the
following formula.
(3) Set sub-address (00) data to 40H, 80H and C0H, measure as in step (2) above, and calculate
frequency change rates BH01, BH10 and BH11.
HB05 H-OUT output voltage (1) Set SW20 to open.
(2) Measure high (V15H) and low (V15L) voltages of pin 26 (H-OUT) output waveform.
106
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TA1316AN
Note
No.
V01
Parameter
Test Method
VP output pulse width (1) Input signal d (as shown in figure below) to TP16 and signal e (as shown in figure below) to
pin 24 (FBP IN).
Vertical free-running
(maximum pull-in
(2) Measure VP output pulse width (VPW ) from TP27 output waveform.
range)
(3) Measure VP pull-in range (VPt0) from TP27 output waveform.
(4) Set sub-address (03) data to 01H, 02H, 03H, 04H, 05H and 06H and measure, as in step (4)
above, pull-in ranges VPt1, VPt2, VPt3, VPt4, VPt5 and VPt6.
2.35 µs
29.63 µs
Signal d
(TP16 input signal)
4V
5.6 µs
9V
Signal e
(pin 24 input waveform)
GND
Pin 24
input waveform
TP27 waveform
VPw
VPt
V02
Minimum vertical
pull-in range
(1) This is same as step (1) for V01.
(2) Input signal f (as shown in figure below) to TP15.
(3) Increase signal f cycle from 30H. Measure cycle (TVPULL) when phase locks with that of
TP27.
Signal f (TP15
input waveform)
3H
TVPULL
Pin 24
input waveform
TP27 waveform
107
2002-10-04
TA1316AN
Note
No.
V03
Parameter
Vertical black peak
detection pulse
Test Method
(1) This is same as step (1) for V01.
(2) Input signal f (as shown in figure below) to TP15.
(3) Measure phase differences VBPP0E and VBPP0S from TP18 output waveform.
(4) Set sub-address (03) data to 01H, 02H, 03H, 04H, 05H and 06H, and measure as in step (3)
above, phase differences VBPP1E, VBPP1S, VBPP2E, VBPP2S, VBPP3E, VBPP3S, VBPP4E,
VBPP4S, VBPP5E, VBPP5S, VBPP6E and VBPP6S.
Signal f (TP15
input waveform)
3H
262.5H~1125H
Pin 24
input waveform
VBPPS
VBPPE
TP18 waveform
V04
Vertical blanking stop (1) This is same as step (1) for V01.
phase
(2) Input signal f (as shown in figure below) to TP15.
(3) Set sub-address (03) data to 00H and F0H, and measure blanking stop phases VBLKMIN and
VBLKMAX from pin 43 output waveform.
Signal f (TP15
input waveform)
3H
1125H
Pin 24
input waveform
VBLK
Pin 43 waveform
108
2002-10-04
TA1316AN
(1)
Video signal
63.5 µs
Frequency f0 sine wave
(2)
Input signal 1
(3)
Input signal 2
Amplitude A
Frequency f0 sine wave
(4)
Input signal 3
Figure T-1
Test Signals for Text/Color Difference Signal 2
109
2002-10-04
TA1316AN
63.5 µs
20 µs
20 µs
20 µs
20 ns
20 ns
(1) Input signal 4
50%
tPR
(2)
tPF
0%
10%
50%
90%
100%
τR
τF
tPR
(3)
tPF
0%
10%
50%
90%
100%
τR
Figure T-2
τF
Test Pulses for Text/Color Difference Signal 2
110
2002-10-04
1000 pF
14
2
3
13
4
TP13
TP14a
A
12
5
11
6
TP15
TP16
10
7
111
TP17
9
8
15.75 kHz
TP18
16
1
1000 pF
TP14b
B
SW14
1200 pF
15
14
TC4538BP
2
3
TP20 TP21
13
4
12
5
DEF/DAC GND
H-OUT
VP OUT
DAC1
(SYNC OUT)
24
25
26
27
28
#23
11
6
A
TP23b
B
A
10
7
#24
TP23a
B
C
B
A
9
8
31.5/33.75 kHz
#26
1
31
#30
16
30
#27
1200 pF
15
1000 pF
14
TC4538BP
2
3
13
0.1 µF
100 µF
470 Ω
10 kΩ
TP30
2.0 V
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
470 Ω
#31
I L VDD
32
SCL
SDA
33
2
2
I L GND
ANALOG B IN
#33
30 kΩ
FBP IN
100 µF
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
B
1/2W 240 Ω
SW33
SW37
SW34
SW38
SW35
SW39
300 pF
6.8 V
100 kΩ
0.01 µF
100 Ω
100 Ω
100 Ω
TP31
1 kΩ
#22
34
5.1 kΩ
H CURVE
CORRECTION
#34
3.9 kΩ
#21
35
SW26
HORIZONTAL
FREQUENCY SW
23
DAC2 (ACB pluse)
#35
B A
10 kΩ
#20
36
SW24b
#18
#36
1 µF
HVCO
22
ANALOG OSD B IN
37
B A
SW24A 10 kΩ
ANALOG G IN
AFC FILTER
21
ANALOG OSD G IN
#37
100 Ω
DEF/DAC VCC
20
ANALOG OSD R IN
38
SW23
ANALOG R IN
SCP OUT
19
RGB VCC
#38
15 kΩ 15 kΩ 15 kΩ
#17
39
470 Ω
SCP IN
18
B OUT
#39
CSBLA503KECZF30
#16
40
1 kΩ
HD1 IN
17
G OUT
#40
10 µF
VD1 IN
16
R OUT
41
100 Ω
SYNC IN
15
RGB GND
HD2 IN
#41
100 Ω
#15
100 Ω
100 Ω
100 Ω
0.1 µF
0.1 µF
0.1 µF
0.01 µF
10 kΩ
10 kΩ
470 Ω
9V
12
4
5
51 kΩ
TP12
#14
42
A
51 kΩ
1200 pF
#13
#42
TP33
10 µF
15
#12
43
B
TP34
50 kΩ 7.5 kΩ
TP10
#43
0.01 µF
B
#11
100 Ω
14
IK IN
VD2 IN
13
44
B S/H
COLOR LIMITER
12
45
1 µF 3 kΩ SW20
B A
#45
B A
TP35
5.1 kΩ 50 kΩ
1
#46
TP37
51 kΩ
16
30 kΩ
A
#10
2.2 µF
11
46
G S/H
Cr2/Pr2 IN
10
47
TP38
10 µF
A
TP9
#47
B A
50 kΩ 7.5 kΩ
TP5
#9
0.1 µF
9
48
R S/H
Cb2/Pb2 IN
#48
SW10
B
0.1 µF
YS 3 (analog RGB)
Y2 IN
8
49
TP39
51 kΩ
10 µF
#8
B A
SW9
A
SW8
7
50
A
0.01 µF
B
0.1 µF
YS 2 (analog OSD)
MATRIX SW
100 µF
0.01 µF
3 kΩ
SW54
10µF
SW56
LED
5.1 kΩ 50 kΩ
B
#7
SW7
YS 1 (analog OSD)
Y/C GND
6
51
YM/P-MUTE/BLK
Cr1/Pr1 IN
5
52
ABCL IN
Cb1/Pb1 IN
#53
1 µF NP
B A
0.1 µF
0.1 µF
#5
SW INPUT
0.1 µF
4
53
VSM OUT
Y1 IN
3
54
Y/C VCC
BPH FILTER
2
55
APL FILTER
DARK AREA DET
FILTER
1
56
51 kΩ
TPB
#49
10 µF
TPA
#50
50 kΩ 7.5 kΩ
C
33 kΩ
TP4
SW5
A
#51
5.1 kΩ 50 kΩ
B
56 kΩ
A
#4
2 kΩ
3.9 kΩ
C
#3
#52
51 kΩ
10 µF
#2
5.1 kΩ
TP1
SW4
B
#54
75 Ω
SW3
A
20 kΩ
SW1
#55
0.1 µF
0.1 µF
1 µF
#1
2 kΩ
3.9 kΩ
30 pF
20 kΩ
SW2
#56
5.1 kΩ
75 Ω
A
1 µF
100 kΩ
2 kΩ
1 µF
TA1316AN
Test Circuit
VCC (9 V)
#29
29
TA1316AN
#28
TP27
B
C
VCC (9 V)
TPC
TC4538BP
11
10
9
TPD
6
7
8
45 kHz
2002-10-04
Cr/Pr1-IN
10 µF
Cr/Pr2-IN
Cb/
Pb2-IN 10 µF
10 µF
112
A
B
ANALOG R IN
ANALOG G IN
HVCO
HORIZONTAL
FREQUENCY SW
H CURVE
CORRECTION
FBP IN
DEF/DAC GND
H-OUT
VP OUT
20
21
22
23
24
25
26
27
VP-OUT
TA1316AN
47 µH
31
H-FREQ
Tr.
0.01 µF
470 Ω
470 Ω
0.1 µF
0.1 µF
0.1 µF
30 kΩ
0.1 µF
0.1 µF
0.1 µF
0.01 µF
100 µF
100 Ω
100 Ω
100 Ω
6.8 V
300 pF
30 kΩ
0.01 µF
0.01 µF
0.01 µF
47 µH
IK IN
ABCL
47 µH
VSM-OUT
B-OUT
G-OUT
R-OUT
2.0 V
ANALOG B-IN
ANALOG G-IN
ANALOG R-IN
DAC2-OUT
OSD B-IN
OSD G-IN
OSD R-IN
SDA
I L VDD
2
SCL
SDA
32
H-OUT
2
33
I L GND
ANALOG B IN
34
1 kΩ
10 kΩ
35
FBP-IN
DAC2 (ACB pluse)
ANALOG OSD B IN
36
CURVE CORR
470 Ω
CSBLA503KECZF30
AFC FILTER
19
ANALOG OSD G IN
37
M 0.01 µF
○
3 kΩ
DEF/DAC VCC
38
1 µF
0.01 µF
18
ANALOG OSD R IN
39
0.1 µF
1 kΩ
SCP OUT
17
RGB VCC
40
560 Ω
SCP IN
16
B OUT
41
1.5 kΩ
100 µF
HD1 IN
15
G OUT
42
SCP-OUT
VD1 IN
14
R OUT
43
SCP-IN
SYNC IN
13
44
HD1-IN
1 µF
12
45
RGB GND
HD2 IN
11
46
VD1-IN
HD2-IN
VD2 IN
10
47
IK IN
COLOR LIMITER
9
48
B S/H
Cr2/Pr2 IN
8
49
G S/H
Cb2/Pb2 IN
7
50
R S/H
YS 3 (analog RGB)
Y2 IN
6
51
1 kΩ
3.9 kΩ
SYNC-IN 10 µF
5.1 kΩ
2.2 µF
M
0.1 µF
○
M
0.1 µF
○
M
0.1 µF
○
YS 2 (analog OSD)
MATRIX SW
Ys3
VD2-IN
Matrix SW
0.01 µF
100 kΩ
0.01 µF
100 µF
2.2 µF
Ys2
75 Ω
1 kΩ
3.9 kΩ
YS 1 (analog OSD)
Y/C GND
5
52
YM/P-MUTE/BLK
Cr1/Pr1 IN
4
53
ABCL IN
Cb1/Pb1 IN
3
54
VSM OUT
Y1 IN
2
55
Y/C VCC
BPH FILTER
1
56
APL FILTER
DARK AREA DET
FILTER
Ys1
1 kΩ
10 µF
5.1 kΩ
75 Ω
Y2-IN 10 µF
1 kΩ
75 Ω
M
0.1 µF
○
M
0.1 µF
○
M
0.1 µF
○
1 µF
1 µF
YM
75 Ω
1 kΩ
1 kΩ
3.9 kΩ
10 µF
75 Ω
5.1 kΩ
75 Ω
Y1-IN
1 kΩ
Cb/Pb1-IN
75 Ω
TA1316AN
Application Circuit
VCC
VCC
SCL
30
29
28
M : Mylar capacitor
○
Application of H-FREQ switching (31.5 k/33.75 k/45 kHz)
A
31.5 kHz
L
L
33.75 kHz
L
H
3V
45 kHz
H
*
0V
B
Pin 22
Voltage
6V
*: Don’t care
2002-10-04
TA1316AN
ACB Application Circuit
+B
CRT
R
G
CRT
CRT
B
R
G
B
0~3.0 V (DC)
113
20~51 kΩ
1 Vp-p
51~330 pF
45
6.8 V Z
IK IN
CLAMP
2002-10-04
TA1316AN
Package Dimensions
Weight: 5.55 g (typ.)
114
2002-10-04
TA1316AN
RESTRICTIONS ON PRODUCT USE
000707EBA
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of
safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of
such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability
Handbook” etc..
• The TOSHIBA products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or
bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this
document shall be made at the customer’s own risk.
• The products described in this document are subject to the foreign exchange and foreign trade laws.
• The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other
rights of the third parties which may result from its use. No license is granted by implication or otherwise under
any intellectual property or other rights of TOSHIBA CORPORATION or others.
• The information contained herein is subject to change without notice.
115
2002-10-04