TC9446F TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC9446F Audio Digital Processor for Decode of Dolby Digital (AC-3), MPEG2 Audio TC9446F is the various digital signal processor for decoding. It contains the decode processing program which embraced encoding signals, such as Dolby Digital (AC-3)/Pro Logic (Note 1), MPEG2 audio and DTS (Note 2). Decoding of Dolby Digital or MPEG2 audio is made with a single chip. Moreover, an external memory can be connected to the TC9446F to decode DTS. Features • Dolby digital (AC-3) or MPEG2 audio decode • Audio interface Acceptable bit rate upto 640 kbps Weight: 1.57 g (typ.) 4 output port, 2 input port (2 port of LRCK and BCK) DIR (digital audio interface receiver) built-in DIT (digital audio interface transmitter) built-in DIR and DIT are available upto 96 kHz sampling of 2 channel • Operating clock: DLL oscillator upto 6th times for DSP clock • Instruction cycle: 20 ns/1 instruction at 50 MIPS operation • DSP Processor: 24 bit × 24 bit + 51 bit multiplier and adder, 51 bit ALU Data bus: 24 bit × 3 Data RAM: 12 k word Coeficient ROM: 4 k word Program ROM: 12 k word Program RAM: 128 word • MCU interface: Serial interface or I2C bus interface • Others It is possible to connect external RAM, 256 k or 1 M SRAM External interruption input terminal Flag input terminal: 4 inputs General-purpose output port: 8 outputs (The ports can be used as interrupt outputs to MCU and logic control outputs.) incorrect operation detect • Operating Voltage: 3.0 ± 0.3 V • In CMOS structure and high-speed processing • 100 pin flat package design Note 1: “Dolby”, “Pro Logic”, and the double-D symbol are trademarks of Dolby Laboratories. Note 2: “DTS” and “DTS Digital Surround” are registered trademarks of Digital Theater Systems, Inc. Note 3: Since this product has a weak terminal in serge voltage, please advise handling it enough. 1 2002-04-18 TC9446F OE VDD CE IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 VSS AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 VDD AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 Pin Connection 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VSS 81 50 WR PO0 82 49 VSS PO1 83 48 LOCK PO2 84 47 CKO PO3 85 46 VSSA PO4 86 45 CKI PO5 87 44 AMPO PO6 88 43 AMPI PO7 89 42 PLON VDDDL 90 41 VDDA LPFO 91 40 PDO TC9446F DLON 92 39 TSTSUB2 DLCKS 93 38 TSTSUB1 SCKO 94 37 FCONT VSSDL 95 36 TSTSUB0 TEST2 VDDX 100 31 TXO 2 BCKOB TEST1 LRCKOB TEST0 BCKOA VDD LRCKOA SDI1 SDI0 BCKB LRCKB 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 SDO3 9 SDO2 8 SDO1 7 SDO0 6 BCKA 5 VSS 4 LRCKA 3 FI3 2 IRQ 1 FI2 32 FI1 99 FI0 TEST3 XI MIACK 33 MICK 98 MIDIO RX XO MILP VSS 34 MICS 35 97 RST 96 MIMD SCKI VSSX 2002-04-18 TC9446F Block Diagram Program ROM 4 k word × 3 RAM 128 word Program Instruction control IRQ YRAM CROM ERAM 4 k word 4 k word 4 k word 4 k word SDOn Y pointer register Y bus Bus switch Register X0, X1, X2 Y0, Y2, Y3 3 External SRAM interface MX MY MZ AX AY General output port LRCK/BCK RX C pointer register X bus Instruction Decoder 2 Audio Interface DLON 40 bit I bus 4 DLL LPFO X pointer register Interrupt SDIn SCKO SCKI Address Operater ×2 XRAM Timing MAC DIR ALU Flag 17 8 8 4 CE , OE , WR ADn IOn POn FIn LOCK A1 A0 A2 A3 DIT RST TXO MIMD MICS Timer Round/Limiter Round/Limiter MILP MIDIO MICK MCU interface MIACK 3 2002-04-18 TC9446F Pin Functions Pin No. Symbol I/O 1 RST I Reset signal input terminal (L: reset, H: normal operation) 2 MIMD I Mode select input for MCU interface (L: serial, H: I C bus) Pull-down resistor, Schmitt input 3 MICS I Chip select input for MCU interface Schmitt input 4 MILP I Latch pulse input for MCU interface Schmitt input 5 MIDIO I/O Data input and output for MCU interface Schmitt input/ Open-drain output 6 MICK I Clock input for MCU interface Schmitt input 7 MIACK O Acknowledge output for MCU interface 8 FI0 I Flag input 0 Pull-up resistor, Schmitt input 9 FI1 I Flag input 1 Pull-up resistor, Schmitt input 10 FI2 I Flag input 2 Pull-up resistor, Schmitt input 11 FI3 I Flag input 3 Pull-up resistor, Schmitt input 12 IRQ I Interruption input Pull-down resistor, Schmitt input 13 VSS 14 LRCKA I LR clock input-A for audio interface Schmitt input 15 BCKA I Bit clock input-A for audio interface Schmitt input 16 SDO0 O Data output-0 for audio interface 17 SDO1 O Data output-1 for audio interface 18 SDO2 O Data output-2 for audio interface 19 SDO3 O Data output-3 for audio interface 20 LRCKB I LR clock input-B for audio interface Schmitt input 21 BCKB I Bit clock input-B for audio interface Schmitt input 22 SDI0 I Data input-0 for audio interface Schmitt input 23 SDI1 I Data input-1 for audio interface Schmitt input 24 VDD Digital power supply 25 LRCKOA O LR clock output-A for audio interface 26 BCKOA O Bit clock output-A for audio interface 27 TEST0 I Test input-0 (L: test, H: normal operation) Pull-up resistor, Schmitt input 28 TEST1 I Test input-1 (L: test, H: normal operation) Pull-up resistor, Schmitt input 29 LRCKOB O LR clock output-B for audio interface 30 BCKOB O Bit clock output-B for audio interface 31 TXO O SPDIF output 32 TEST2 I Test input-2 (L: test, H: normal operation) Pull-up resistor, Schmitt input 33 TEST3 I Test input-3 (L: test, H: normal operation) Pull-up resistor, Schmitt input 34 RX I SPDIF input Schmitt input 35 VSS Description of Pin Functions 2 Remarks Pull-up resistor, Schmitt input Digital ground Digital ground 4 2002-04-18 TC9446F Pin No. Symbol I/O 36 TSTSUB0 I Test sub input-0 (L: test, H: normal operation) Pull-up resistor, Schmitt input 37 FCONT O Frequency control output for VCO circuit Tri-state output 38 TSTSUB1 I Test sub input-1 (L: test, H: normal operation) Pull-up resistor, Schmitt input 39 TSTSUB2 I Test sub input-2 (L: test, H: normal operation) Pull-up resistor, Schmitt input 40 PDO O Phase detect signal output Tri-state output 41 VDDA Analog power supply 42 PLON I Clock selection input (L: external clock, H: VCO clock) 43 AMPI I Amplifier input for Low pass filter 44 AMPO O Amplifier output for Low pass filter 45 CKI I External clock input 46 VSSA Analog ground 47 CKO O DIR clock output 48 LOCK O VCO lock output 49 VSS Digital ground 50 WR O Write signal output for external SRAM 51 OE O Enable signal output for external SRAM 52 CE O Chip enable signal output for external SRAM 53 VDD Digital power supply 54 IO7 I/O Data I/O-7 for external SRAM Pull-up resistor 55 IO6 I/O Data I/O-6 for external SRAM Pull-up resistor 56 IO5 I/O Data I/O-5 for external SRAM Pull-up resistor 57 IO4 I/O Data I/O-4 for external SRAM Pull-up resistor 58 IO3 I/O Data I/O-3 for external SRAM Pull-up resistor 59 IO2 I/O Data I/O-2 for external SRAM Pull-up resistor 60 IO1 I/O Data I/O-1 for external SRAM Pull-up resistor 61 IO0 I/O Data I/O-0 for external SRAM Pull-up resistor 62 VSS Digital ground 63 AD0 O Address output-0 for external SRAM Pull-up resistor 64 AD1 O Address output-1 for external SRAM Pull-up resistor 65 AD2 O Address output-2 for external SRAM Pull-up resistor 66 AD3 O Address output-3 for external SRAM Pull-up resistor 67 AD4 O Address output-4 for external SRAM Pull-up resistor 68 AD5 O Address output-5 for external SRAM Pull-up resistor 69 AD6 O Address output-6 for external SRAM Pull-up resistor 70 AD7 O Address output-7 for external SRAM Pull-up resistor 71 VDD Digital power supply 72 AD8 O Address output-8 for external SRAM Pull-up resistor 73 AD9 O Address output-9 for external SRAM Pull-up resistor 74 AD10 O Address output-10 for external SRAM Pull-up resistor 75 AD11 O Address output-11 for external SRAM Pull-up resistor 76 AD12 O Address output-12 for external SRAM Pull-up resistor 77 AD13 O Address output-13 for external SRAM Pull-up resistor Description of Pin Functions 5 Remarks Pull-up resistor, Schmitt input 2002-04-18 TC9446F Pin No. Symbol I/O 78 AD14 O Address output-14 for external SRAM Pull-up resistor 79 AD15 O Address output-15 for external SRAM Pull-up resistor 80 AD16 O Address output-16 for external SRAM Pull-up resistor 81 VSS Digital ground 82 PO0 O General output port-0 Pull-up resistor 83 PO1 O General output port-1 Pull-up resistor 84 PO2 O General output port-2 Pull-up resistor 85 PO3 O General output port-3 Pull-up resistor 86 PO4 O General output port-4 Pull-up resistor 87 PO5 O General output port-5 Pull-up resistor 88 PO6 O General output port-6 Pull-up resistor 89 PO7 O General output port-7 Pull-up resistor 90 VDDDL Power supply for DLL circuit 91 LPFO O Low pass filter output for DLL circuit 92 DLON I DLCKS pin 93 DLCKS I Description of Pin Functions DLON pin DLL clock setting “L” “L” SCKI input (DLL = off) “L” “H” 4th times of XI clock “H” “L” 3rd times of XI clock “H” “H” 6th times of XI clock 94 SCKO O ASP clock output 95 VSSDL Ground for DLL circuit 96 SCKI I External system clock input 97 VSSX Ground for crystal oscillator 98 XO O Crystal oscillator output 99 XI I Crystal oscillator input 100 VDDX Remarks Pull-up resistor Pull-up resistor Digital power supply 6 2002-04-18 TC9446F Description of Operation 1. Micro Controller Interface The TC9446F can perform transmission and reception of serial data with a micro controller in the serial mode or the I2C mode. MIMD terminal performs a change in the serial mode and the I2C mode, and input and output of data are performed at MSB first. The use terminal and the function in the serial mode and the I2C mode are shown in Table 1. The bit composition of a 24 bit command is shown in Table 2. Note 4: This data sheet shows the general control method, refer to the program explanation data of an attached sheet for a detailed command list, the control method, etc. Table 1 2 Use Terminal and Function in the Serial Mode and the I C Mode Transmission Mode Terminal 2 Serial Mode (MIMD = L) I C Mode (MIMD = H) Functions Functions Input/Output MICS Input (3-5 V) Chip selection signal input Not used (fixed “L”) MILP Input (3-5 V) Latch pulse signal input Not used (fixed “L”) MIDIO Input (3-5 V)/Output (3 V) Data input/output Data input/output (SDA) MICK Input (3-5 V) Clock input Clock input (SCL) MIACK Output (3 V) Acknowledge signal output and out of control detection output Out of control detection output Note 5: MIDIO terminal needs pull-up resistance for the terminal exterior because of an open-drain output. 2 When using it by I C bus, pull-up resistance is required also for MICK terminal. 2 Note 6: The addresses of an I C bus are write-in address 3Ah and read-out address 3Bh. Table 2 Bit Assign Bit Composition of 24 Bit Command Functions Remarks 16 bit address Refer to the command list of the program explanation data sheet 7 Starting the incorrect operation detection output Starting the incorrect operation detection output by “1” 6 Starting the program RAM boot Starting the program RAM boot by “1” 5 Setting the soft reset Setting the soft reset ON by “1” 4 Setting the Read/Write (R/W) Setting the read by “1” 23-8 “0h”; a word 3-0 ↓ Setting the number of words for transmission “Fh”; 16 words 7 2002-04-18 TC9446F 2. Data Transmission Format 2-1. Serial Mode Setting 2-1-1. Data Transmission Format in the Serial Mode A data transmission format in the serial mode is shown in Figure 1. After the data transmission at the time of the serial mode sets MICS signal to “L”, fundamentally, it checks that MIACK signal is “L” and transmits a 24 bit command at MSB first. However, it cannot transmit at the time of MIACK signal = “H”. Then, the word set up by the 24 bit command which the Read or Write (R/W) of 24 bit data of a number (1-16 word) is performed, and, finally, MICS signal is set to “H”. However, since there is a term when MIACK signal after transmission is set to “H” in a 24 bit command, at the time of Read, command transmission back also needs to check that MIACK signal is set to “L”. Transmission data (1 to 16 words) MICS MIACK MILP MICK MIDIO COMMAND (24 bit) Figure 1 DATA-1 (24 bit) DATA-16 (24 bit) Serial Mode Data Transmission Format 2-1-2. Data Transmission Method in the Serial Transmission Mode 1) Program boot and a program start As for TC9446F, RAM is assigned 128 words of program address 0000h-007Fh, and the interruption vector address is become 0000h-0009h. Therefore, in order to operate TC9446F, it needs to interrupt and a program needs to be booted to a vector address. In addition, a program load needs to be continuously performed to an interruption vector address to store a program in 000Ah-007Fh. In order to perform program boot, the program RAM boot start bit and the soft reset bit in the 24 bit command transmitted after reset need to be set to “H”. (command = 000060h) And, after command transmission, program data (40 bit) is divided into 20 bit of a higher rank/low rank, and it transmits by the low-rank stuffing of 24 bit data in the order of a higher rank (20 bit) and a low rank (20 bit). Since a write-in address is made automatic (+1) from 0000h, if it transmits the required number of words and MICS is set to “H”, program boot will complete it. In addition, the write-in address of program boot always starts from 0000h. A start of a program carries out and transmits the soft reset bit in a 24 bit command to “L”, and is performed by setting MICS to “H”, without performing data transmission. The procedure of program boot and a program start is shown in Figure 2. 8 2002-04-18 TC9446F Reset of Hardware (or reset of software by command) MICS = “L” Checking of MIACK = “L” (waiting for becoming to MIACK = “L” at the MIACK = “H”) Setting “H” for bit of program boot and soft reset bit. Write of the 24 bit command (program boot = 000060h) Write of program data (higher rank 20 bit at address 0000h) Program data is 20 bit lower assign. It is possible to do the program boot for address of 007Fh maximum. Write of program data (low rank 20 bit at address 0000h) Write of program data (higher rank 20 bit at address 0007h) Write of program data (low rank 20 bit at address 0007h) MICS = “H” It finished the program boot. MICS = “L” Checking of MIACK = “L” (waiting for becoming to MIACK = “L” at the MIACK = “H”) Write of the 24 bit command (soft reset off = 000000h) MICS = “H” Program starting Figure 2 Procedure of Program Boot and Program Start 9 2002-04-18 TC9446F 2) Write of 24 bit data The number of words of data written in while data required for the 16 bit address in a 24 bit command is set up and R/W bit is set to “L”, when writing in data from a MCU to TC9446F during program operation is set up. And, 24 bit data of the number required after transmitting a 24 bit command of words is written in. The procedure of the write of 24 bit data is shown in Figure 3. MICS = “L” Checking of MIACK = “L” (at the MIACK = “L”, waiting for becoming to MIACK = “L”) Setting of 16 bit address and umber of the transmission word. Write of 24 bit command (write of data = xxxx0xh) Write of 24 bit data (1) It is possible to write the 24 bit data until 16 word maximum. Write of 24 bit data (2) Write of 24 bit data (n) MICS = “H” It finished to write the data Figure 3 Procedure of Write of 24 Bit Data 10 2002-04-18 TC9446F 3) Read-out of 24 bit data The number of words of data read while data required for the 16 bit address in a 24 bit command is set up and R/W bit is set to “H”, when reading data of TC9446F from a MCU during program operation is set up. And, after transmitting a 24 bit command, MIACK = “L” is checked and 24 bit data of the required number of words is read. MIACK = “L” is checked after command transmission for waiting to set data which should be read to data buffer. The procedure of read-out of 24 bit data is shown in Figure 4. MICS = “L” Checking of MIACK = “L” (waiting for becoming to MIACK = “L” at the MIACK = “H”) A 16 bit address and a transmission word number are set up. Write of 24 bit command (read of data = xxxx1xh) Checking of MIACK = “L” (waiting for becoming to MIACK = “L” at the MIACK = “H”) Read of 24 bit data (1) It is possible to read out the 24 bit data until 16 word maximum. Read of 24 bit data (2) Read of 24 bit data (n) MICS = “H” It finished to read of the data Figure 4 Procedure of Read-Out of 24 Bit Data 11 2002-04-18 TC9446F 4) ON/OFF of soft reset The case where a program is started after program boot, and in restarting a program, it performs ON/OFF of soft reset. ON/OFF of soft reset are performed by carrying out and transmitting the bit of the soft reset in a 24 bit command to “H” (ON) and “L” (OFF). Since data with which ON/OFF of soft reset follow a command is not required, it is made into MICS = “H” after 24 bit command transmission. In addition, in order to return from a incorrect operation state, when turning ON soft reset, a 24 bit command can be transmitted irrespective of the state of MIACK signal. The procedure of ON/OFF of soft reset is shown in Figure 5. MICS = “L” Checking of MIACK = “L” (waiting for becoming to MIACK = “L” at the MIACK = “H”) It is possible to transmit the command data of soft reset ON at MIACK = “H”. Soft reset ON: Bit = “1”. Soft reset OFF: Bit = “0”. Transmission of 24 bit command (soft reset ON/OFF = 0000x0h) MICS = “H” Soft reset ON/OFF Figure 5 Procedure of ON/OFF of Soft Reset 12 2002-04-18 TC9446F 5) Incorrect operation detection Incorrect operation detection of the internal program of TC9446F can be made to perform by setting the incorrect operation detection start bit in a 24 bit command to “H”. As for this incorrect operation detection start bit, the reversal output only of the case of MICS terminal = “H” is carried out from MIACK terminal. And, since this incorrect operation detection start bit is periodically cleared by “L” when an internal program is operating normally, MIACK terminal at the time of MICS terminal = “H” is set to “H” from “L”. However, since it will stop being cleared if an internal program becomes a incorrect operation state, as for MIACK terminal at the time of MICS terminal = “H”, the state of “L” will continue. Thus incorrect operation detection of a program is attained by supervising MIACK terminal at the time of MICS terminal = “H”. Moreover, although it checks that MIACK terminal is “L” after setting MICS terminal to “L” in case a MCU starts access to TC9446F, MCU can judge that an internal program is a incorrect operation state, when the state of MIACK = “H” continues. In addition, when a incorrect operation state is detected, it can return from a incorrect operation state by initializing by transmitting the soft reset command which the reset terminal was set to “L” or was mentioned above. The procedure of incorrect operation detection is shown in Figure 6. MICS = “L” Checking of MIACK = “L” (waiting for becoming to MIACK = “L” at the MIACK = “H”) When not set to “L” with “H”, it is the state of incorrect operation. Transmission of 24 bit command (starting the incorrect operation detection = 000080h) It starts the incorrect operation detection by “1”. MICS = “H” MIACK = “L” Program makes to clear the incorrect operation detection bit MIACK = “L” is continue at incorrect operation, as detection bit isn’t cleared. MIACK = “H” Figure 6 Procedure of Incorrect Operation Detection 13 2002-04-18 TC9446F 2-2. 2 I C Mode Setting 2 2-2-1. Data Transmission Format in I C Mode The foundations of a data transmission format in the I2C mode are shown in Figure 7. Fundamentally, the data transmission at the time of the I2C mode checks that ACK bit is set to “L”, after making I2C Address (write = 3Ah) to transmission. However, at the time of “H”, ACK bit performs Start Condition again, without performing STOP Condition, and transmits I2C Address (3Ah). I2C Transmit 24 bit command after Address transmission. And, at the time of data Write of TC9446F, Write of 24 bit data of the number (1-16 word) of words set up by 24 bit command is performed from a MCU, and, finally, END Condition is transmitted. Moreover, it checks that transmit I2C Address (read = 3Bh) from TC9446F at the time of Read to a MCU, without performing END Condition after 24 bit command transmission, and ACK bit is set to “L”. However, at the time of “H”, ACK bit performs Start Condition again, without performing STOP Condition, and transmits I2C Address (3Bh). The word set up by 24 bit command after checking that ACK bit is “L”. Although Read of 24 bit data of a number (1-16 word) is performed, as for the inside of Read, a MCU needs to set ACK bit to “L” for every 8-bit Read data. And, only ACK bit added to the last 8 bits is set to “H”, and STOP Condition is transmitted. Moreover, at the time of transmission of only a 24 bit command which does not perform R/W of data, END Condition is transmitted after 24 bit command transmission. In addition, in TC9446F, polling of the access demand from a MCU is carried out every about 6 ms at the time of decode processing. Therefore, R/W of data from a MCU need to be performed at the interval of 6 ms or more. At the time of Write-in, Read-out and a command only shows the transmission format to Figure 7 to Figure 10. SDA I2C Address (3Ah) R/W ACK DATA Hi (8 bit) DATA Mid (8 bit) ACK ACK DATA Lo (8 bit) ACK SCL I2C Address 24 bit DATA (1 word to 16 word) START Condition STOP Condition Figure 7 2 Data Transmission Format in the I C Mode 14 2002-04-18 TC9446F (3Ah) START I2C Address 24 bit COMMAND 24 bit Write DATA (1 word to 16 word) W A COMMAND (H) A COMMAND (M) A COMMAND (L) A DATA (H) A DATA (M) A DATA (L) A STOP All of ACK are retarnd to MCU from TC9446F The interval of 6 ms or more is required until next START. Figure 8 (3Ah) START I2C Add. Format at Time of Write 24 bit COMMAND (3Bh) W A COMMAND (H) A COMMAND (M) A COMMAND (L) A START I2C Add. 24 bit Read DATA (1 word to 16 word) R A RD (H) A RD (M) A RD(L) A STOP These of ACK are retarned to MCU from TC9446F These of ACK are retarned to TC9446F from MCU The interval of 6 ms or more is required Figure 9 Format at Time of Read (3Ah) START I2C Address This ACK is MCU set up at “H”. 24 bit COMMAND W A COMMAND (H) A COMMAND (M) A COMMAND (L) A STOP All of ACK are returned to MCU from TC9446F. Figure 10 Format Only a Command at the Time of Transmission. 15 2002-04-18 TC9446F 2 2-2-2. The Data Transmission Method in I C Mode 1) Program boot and a program start As for TC9446F, RAM is assigned 128 words of program address 0000h-007Fh, and the interruption vector address is become 0000h-0009h. Therefore, in order to operate TC9446F, it needs to interrupt at least and a program needs to be booted to a vector address. In addition, a program load needs to be continuously performed to an interruption vector address to store a program in 000Ah-007Fh. In order to perform program boot, the program RAM boot start bit and the soft reset bit in the 24 bit command transmitted after reset need to be set to “H”. (command = 000060h) And after command transmission, program data (40 bits) is divided into 20 bits of a higher rank/low rank, and it transmits by the low-rank stuffing of 24 bit data in the order of a higher rank (20 bits) and a low rank (20 bits). Since a write-in address is made automatic (+1) from 0000h, if it transmits the required number of words and END Condition is transmitted, program boot will complete it. In addition, the write-in address of program boot always starts from 0000h. A start of a program is performed by carrying out and transmitting the soft reset bit in a 24 bit command to “L”, and transmitting END Condition, without performing data transmission. The procedure of program boot and a program start is shown in Figure 11. 16 2002-04-18 TC9446F Reset of hardware (or reset of software by command) START Condition At the time of ACK = “H”, it resumes from START Condition. 2 Transmission of I C Address (3Ah) Checking of ACK bit = “L” The bit of program boot and soft reset is set to “H”. Write of 24 bit command (program boot = 000060h) Write of program data (higher rank 20 bit at address 0000h) Program data is 20 bits of low-rank stuffing. Boot is possible to the address of a maximum of 007Fh. Write of program data (low rank 20 bit at address 0000h) Write of program data (higher rank 20 bit at address 0007h) Write of program data (low rank 20 bit at address 0007h) START Condition The completion of program boot. STOP Condition At the time of ACK = “H”, it resumes from START Condition. 2 Transmission of I C Address (3Ah) Checking of ACK bit = “L” Write of 24 bit command (soft reset OFF = 000000h) STOP Condition Program starting Figure 11 Procedure of Program Boot and Program Start 17 2002-04-18 TC9446F 2) Write of 24 bit data The number of words of data written in while data required for the 16 bit address in a 24 bit command is set up and R/W bit is set to “L”, when writing in data from a MCU to TC9446F during program operation is set up. And, 24 bit data of the number required after transmitting a 24 bit command of words is written in. In addition, completion of internal taking in of write-in data requires the time of about 6 ms of the maximum from END Condition. Therefore, access of a next MCU needs to keep the term for about 6 ms after END Condition transmission. The procedure of the write of 24 bit data is shown in Figure 12. START Condition At the time of ACK = “H”, it resumes from START Condition. 2 Transmission of I C Address (3Ah) Checking of ACK bit = “L” A 16 bit address and a transmission word number are set up. Write of 24 bit command (write of data = xxxx0xh) Write of 24 bit data (1) It is possible to Write in the 24 bit data until 16 word maximum. Write of 24 bit data (2) Write of 24 bit data (n) STOP Condition It is data write-in completion after STOP Condition transmission and within about 6 ms term. Figure 12 Procedure of Write of 24 Bit Data 18 2002-04-18 TC9446F 3) Read of 24 bit data The number of words of data read while data required for the 16 bit address in a 24 bit command is set up and R/W bit is set to “L”, when reading data of TC9446F from a MCU during program operation is set up. And, after transmitting a 24 bit command, I2C Address is set to 3Bh after the term progress for about 6 ms, and it transmits with START Condition. Then, 24 bit data of the required number of words is read. Although ACK bit of a data Read term needs to give “L” from a MCU, it needs to set only ACK bit added to last 8 bit data to “H”. This is because the Basra in of SDA where TC9446F are the master is opened wide and a MCU can transmit STOP Condition. In addition, the term progress for about 6 ms after command transmission is for waiting to set data which should be read to data buffer of TC9446F. The procedure of read-out of 24 bit data is shown in Figure 13. START Condition At the time of ACK = “H”, it resumes from START Condition. 2 Transmission of I C Address (3Ah) Checking of ACK bit = “L” A 16 bit address and a transmission word number are set up. Transmission of 24 bit command (read of data = xxxx1xh) A term is stood by for about 6 ms. START Condition At the time of ACK = “H”, it resumes from START Condition. 2 Transmission of I C Address (3Bh) Checking of ACK bit = “L” Read of 24 bit data (1) It is possible to Write in the 24 bit data until 16 word maximum. Read of 24 bit data (2) Read of 24 bit data (n) The last ACK bit is set to “H”. STOP Condition It finished to read of the data Figure 13 Procedure of Read-Out of 24 Bit Data 19 2002-04-18 TC9446F 4) ON/OFF of soft reset The case where a program is started after program boot, and in restarting a program, it performs ON/OFF of soft reset. ON/OFF of soft reset are performed by carrying out and transmitting the bit of the soft reset in a 24 bit command to “H” (ON) and “L” (OFF). Since data with which ON/OFF of soft reset follows a command is not required, STOP Condition is transmitted after 24 bit command transmission. In addition, in order to return from a incorrect operation state, when turning ON soft reset, it is also possible to transmit a 24 bit command irrespective of the state of ACK bit. The procedure of ON/OFF of soft reset is shown in Figure 14. START Condition At the time of ACK = “H”, it resumes from START Condition. However, it is possible to disregard and carry out command transmission of the ACK bit at the time of a reckless run. 2 Transmission of I C Address (3Ah) Checking of ACK bit = “L” Soft reset ON: Bit = “1”. Soft reset OFF: Bit = “0”. Transmission of 24 bit command (soft reset ON/OFF = 0000x0h) STOP Condition Soft reset ON/OFF Figure 14 Procedure of ON/OFF of Soft Reset 5) Incorrect operation detection Incorrect operation detection of the internal program of TC9446F is judged by the existence of the reaction to the access demand from a MCU. Therefore, R/W of data need to be performed from a MCU to TC9446F at the interval of about 6 ms or more. ACK bit is set to “L”, when the following access demand opens the interval of about 6 ms or more and is performed, since R/W of data were performed between about 6 ms back to the access demand from a MCU when TC9446F were operating normally. However, if TC9446F become a incorrect operation state, even if it is going to stop receiving the access demand from a MCU, it is going to open the interval of about 6 ms or more and MCU is going to make it access again, it will become a state ACK bit is “H” continued. A MCU can perform incorrect operation detection by seeing this ACK bit. That is, since TC9446F are in a incorrect operation state when it is “H” fixation, even if ACK bit passes about 6 ms or more, ACK bit is disregarded, soft reset is turned ON, and each setup of TC9446F is performed again. 20 2002-04-18 TC9446F 3. Setting Procedure Until it Starts Decode Program Operation Setting procedure until it starts operation of the decode program built in TC9446F is shown below. First, 10 words program data is transmitted in the program boot mode after release of the power-on reset at the time of a power-supply injection. However, when there is a program required for others, program data of a maximum of 128 words can be transmitted. And, if the command of soft reset-off is transmitted, a program will begin to operate and decode will be started by transmitting addresses of the write-in command shown in an attached sheet (the program explanation data) after that 9 words of 0000h-0008h. Procedure until it starts operation of a decode program to Figure 15 is shown. Power ON reset Program boot Soft reset OFF Write-in command transmission. (9 word of 0000h to 0008h) (9 word of continuing from 0000h are transmitted.) Starting of decode Figure 15 Procedure to Decode Program Operation Start Note 7: Internal RAM is cleared, in order to muting for output, after transmitting a setup of command 0003h “decode off” in the case of AC-3 decoder program. Please transmit following data after checking that ACK is set to “L” from “H”, since such a case has the time for about 23 ms (maximum) in this processing. If processing of the internal RAM clearance by the “decode off” command is completed, it will return at the waiting time for 1 or less ms. In addition, according to the kind of decode program, please transmit following data after checking that ACK is set to “L” from “H”, since the waiting time which the data transmission at the time of decode on/off takes differs. 21 2002-04-18 TC9446F 4. Read/Write of Command Write and a read of command change with decode programs built in. For details, please refer to program explanation data. 5. Digital Audio Interface (DIR/DIT) 1) A setup of DIR/DIT The digital reception recovery (DIR) for the audio interfaces and the abnormal-conditions transmission (DIT) based on CEI “IEC958 standard” and the JEITA “CP-1201 standard” are built in. DIR corresponds to the input of 96 kHz sampling (2 channels). Please refer to program explanation data about the various contents of a setting of DIR/DIT. 2) VCO oscillation and PLL Since VCO oscillation circuit is built in, PLL circuit can consist of connecting an external low path filter simply. VCO oscillation circuit and the example of composition of PLL are shown in Figure 16. (A) Crystal/XI clock Setting of command registor 48 LOCK 47 Clock output Timing generator Selector XI/CKI selector CKO VDDA 46 VSSA VSSA 45 CKI 44 VCO circuit External clock input (when CKI does not use, it connect to VSS line.) AMPO 43 AMPI VDD/2 L: CKI/XI clock H: VCO clock 42 PLON VSS 41 VDDA Phase detector 40 PDO Frequency detector 37 Demoduration circuit 34 Moduration circuit 31 FCONT DIR input VSSA RX DIT output TXO Figure 16 VCO Oscillation Circuit and Example of Composition of PLL 22 2002-04-18 TC9446F 3) DIR input part When you input a signal into DIR, please be sure to input, as shown in Figure 17 through a signal amplification circuit, a 5 V-3 V conversion circuit, etc. 3V COAXIAL 34 RX DIR (3 V input) VSS VSS 5 V-3 V level shifter 5V OPTICAL VSS Figure 17 4) DIR Input Part Lock detection When VCO circuit locks LOCK terminal and it is operating, “H” level is outputted and “L” level is outputted at the time of the Ann lock. At the time of the Ann lock, latch operation of reception recovery data and channel status is stopped, and it holds last value. If the state of a no error continues the time of the following table, LOCK terminal will be set to “H” level and a reception recovery will be started. Period of error tA LOCK Terminal Data of Receiving Demodulation Channel Status tB Figure 18 Table 3 Internal Operation Timing at Time of Error Release Time After the Lock Detection Operation Sampling Frequency (kHz) Data of Receiving Demodulation tA (ms) Channel Status tB (ms) 32 384.0 288.0 44.1 278.6 209.0 48 256.0 192.0 96 128.0 96.0 23 2002-04-18 TC9446F 5) Non-inputted detection When existence of the edge of the input signal from RX terminal is detected and there is no fixed time edge, VCO oscillation operates by free run. Since VCO oscillation frequency and CKO terminal output are set to about 80 MHz, please change it to an external clock automatically by the internal program at the time of less inputting, or choose XI input by setup of command register. Table 4 6) Non-Inputted Judgment Time of Input Signal Sampling Frequency (kHz) Time of Last Edge (ms) 32 approx. 1000 44.1 approx. 750 48 approx. 700 96 approx. 350 Miss lock detection By comparing the input signal and the oscillation frequency from RX terminal, a Miss lock is detected and the signal for escaping from a miss lock is outputted from FCONT terminal. Higher than objective frequency Objective frequency Lower than objective frequency VDD FCONT Output Hiz VSS Figure 19 Miss Lock Detection Operation Timing 6. DSP Part Clock Generating Circuit It is the circuit which generates a clock required in order to operate a decode program. DLL circuit can generate the DLL clock of a crystal oscillation clock. DLL circuit and a crystal oscillation circuit block are shown in Figure 20. XI (A) CKI/XI selector 99 98 DLL oscilator (*3, *4, *6) XO VSSX 96 SCKI External clock input (when the SCKI does not use, it connect to VSS line.) Selector Clock output 94 SCKO Internal DSP clock Selector 93 DLCKS 92 DLON VSS 91 LPFO VSS Figure 20 Crystal Oscillation Circuit and DLL Circuit Block 24 2002-04-18 TC9446F DLL oscillation clock can be chosen with DLCKS terminal and DLON terminal, as shown in Table 5. Table 5 Setup of DLL Circuit DLCKS Terminal (93 pin) DLON Terminal (92 pin) DLL Oscillation Clock “L” “L” SCKI input (DLL = off) “L” “H” XI input * 4th times “H” “L” XI input * 3rd times “H” “H” XI input * 6th times When DLCKS terminal and DLON terminal are “L”, the external clock input from SCKI terminal is chosen. An internal clock of operation is a half divided clock of the DLL clock, and processing speed can correspond a maximum of 75 MIPS. The clock outputted from DLL circuit should choose a crystal oscillation clock to be set to less than 150 MHz. The example of DLL clock by the crystal oscillation clock is shown in Table 6. Table 6 Crystal Oscillation Clock and DLL Clock Crystal Oscillation Clock 6th Times Clock 4th Times Clock 3rd Times Clock 12.288 MHz (48 kHz*256) 73.728 MHz (36 MIPS operation) 49.152 MHz (24 MIPS operation) 38.864 MHz (18 MIPS operation) 18.432 MHz (48 kHz*384) 110.592 MHz (55 MIPS operation) 73.728 MHz (36 MIPS operation) 55.296 MHz (27 MIPS operation) 24.576 MHz (48 kHz*512) 147.456 MHz (73 MIPS operation) 98.304 MHz (49 MIPS operation) 73.728 MHz (36 MIPS operation) 25.00 MHz (asynchronous) to 150 MHz (75 MIPS operation) 100.00 MHz (50 MIPS operation) 75.00 MHz (37 MIPS operation) 27.00 MHz (asynchronous) Not available 108.00 MHz (54 MIPS operation) 81.00 MHz (40 MIPS operation) 30.0 MHz (asynchronous) Not available to 120 MHz (60 MIPS operation) 90.00 MHz (45 MIPS operation) 36.864 MHz (48 kHz*768) Not available Not available 110.592 MHz (55 MIPS operation) Note 8: Crystal oscillation clock is as asynchronous as the system clocks (AD converter, DA converter, etc.) of external LSI. A case needs to input the clock oscillated externally into CKI terminal, and needs to synchronize with them. 7. Flag Input (FI0-FI3 terminal) It is used when inputting a flag from a MCU. However, a function changes with built-in programs. FI0 to FI3 terminal should fix each terminal to “H”, or since pull-up resistance is built in, when not being specified by the program, please it be open and be used for it. 8. Interruption Input (IRQ terminal) It is used when interrupting and inputting from a MCU. However, operation changes with built-in programs. IRQ terminal should fix a terminal to “L”, or since pull down resistance is built in, when not being specified by the program, please it be open and be used for it. 9. General-Purpose Output Terminal (PO0-PO7 terminal) It can be used when carrying out logic control of the case where it is used as an interruption output to the flag and the MCU for detection of internal operation, or the external LSI. However, the function and operation of a terminal change with built-in programs. Since PO0-PO7 terminal contains pull-up resistance, when not being specified by the program, please carry out and use each output terminal for opening. At the time of a power-supply injection, the output of a general-purpose output terminal becomes unfixed. “L” level will be outputted if it initializes with a reset terminal. 25 2002-04-18 TC9446F 10. External SRAM Connection It can be used by the ability of able to connect external SRAM to processing of data tables, such as coefficient data, or data delay. The function of the terminal for external SRAM control is shown in Table 7. Moreover, the example of connection of external SRAM is shown in Figure 21. Table 7 Function of Terminal for External SRAM Control Terminal Name Functions WR terminal Write signal output terminal for external SRAM OE terminal Output enable signal output terminal for external SRAM CE terminal Chip enable signal output terminal for external SRAM Data input/output terminal for external SRAM (8 bit I/O) IO0 to IO7 terminal It is 3rd times accessing at 24 bit I/O. Address output terminal for external SRAM AD0 to AD16 terminal It can access to address 00000h to 20000h. Example of High-speed 1 M SRAM connection Example of High-speed 256 k SRAM connection TC9446F (3.3 V) TC9446F (3.3 V) 256 k HS SRAM (3.3 V) 1 M HS SRAM (3.3 V) AD15, 16 AD0¯ AD16 IO0¯ IO7 17 8 AD0¯ AD16 AD0¯ AD14 IO0¯ IO7 IO0¯ IO7 N.C 15 8 AD0¯ AD14 IO0¯ IO7 CE CE CE CE OE OE OE OE WR WR WR WR Figure 21 Example of Connection of External SRAM 26 2002-04-18 TC9446F 11. Serial Data Input-and-Output Terminal Since two terminals (SDI0 and SDI1 terminal) are prepared for an audio serial data input and four terminals (SDO0-SDO3 terminal) are prepared for an output, the connection with external AD/DA converter LSI is easy. Although an input terminal (SDI0, SDI1, LRCKA, BCKA, LRCKB, and BCKB terminal) can be inputted by 3-5 V, an output terminal (SDO0-3, LRCKOA, BCKOA, LRCKOB, and BCKOB terminal) is outputted by 3 V. Therefore, when the input terminal of external LSI does not correspond to TTL level input, please carry out level conversion using a level shifter circuit etc. Figure 22 the example of connection of AD/DA converter is shown. However, when an input-and-output signal has the same sampling frequency, it is restricted. Since a sampling frequency differs when the signal of 2 fs is inputted and it outputs a signal by 1 fs, the connection method needs to be changed. AD/DA converter TC9446F DATA OUT SDI0 (fs) RX (2 fs/fs) DIR input Analog input SDO0 (not used) Analog output DATA IN0 SDO1 DATA IN1 SDO2 DATA IN2 SDO3 LRCKI TXO (2 fs/fs) DIT DIT output LRCKOA (2 fs/fs) BCKI BCKOA LRCKA SCKI BCKA LRCKOB (not used) BCKOB (not used) LRCKB BCKB SDI1 (not used) CKO Figure 22 Example of AD/DA Converter Connection 27 2002-04-18 TC9446F 12. Example of Processing of Dolby Digital (AC-3) (Note 9) Decoder IEC958 Dolby Digital (AC-3) 5.1 ch decode Configuration C/Sch delay IEC958 Dolby Digital (AC-3) 5.1 ch decode 2 ch Down Mix IEC958 Dolby Digital (AC-3) 5.1 ch decode 3D sound IEC958 Dolby Digital (AC-3) 2 ch decode Dolby Pro Logic SFC IEC958 Dolby Digital (AC-3) 2 ch decode Dolby Pro Logic 3D sound IEC958 Dolby Digital (AC-3) 2 ch decode 3D sound SFC Note 9: “Dolby”,”Pro Logic”, and the double-D symbol are trademarks of Dolby Laboratories. 28 2002-04-18 TC9446F 13. Example of System Application MCU TC9446F MCU Interface CKO LRCKOA BCKOA 384 fs DIR (VCO) RX (IEC958) TIMING 384 fs fs 64 fs L OUT DAC R OUT CKI 384 fs LRCKA BCKA DLL (×6) SL OUT DAC SR OUT 18.432 MHz 110.592 MHz SDO0¯ 3 L IN ADC R IN SDI0 LRCK BCK 384 fs C OUT DAC DECODE (55 MIPS) LFE OUT DIT TXO (IEC958) 29 2002-04-18 TC9446F 14. Example of Application Circuit CKI PO5 AMPO PO6 AMPI PO7 PLON VDDDL VDDA TC9446F PDO LPFO (top view) DLON TSTSUB2 DLCKS TSTSUB1 VSSDL XI TEST2 MCU I/F (3.3 V) 31 30 0.1 µF 4.7 µF BCKOB LRCKOB TEST1 TEST0 BCKOA LRCKOA VDD SDI1 SDI0 BCKB LRCKB SDO3 SDO2 SDO1 SDO0 BCKA LRCKA VSS IRQ FI3 FI2 FI1 FI0 MIACK MICK 0.1 µF MIDIO 100 1 DIT OUT TXO VDDX MILP * TEST3 MICS * DIR IN RX XO MIMD 20 pF 2.2 M VSS VSSX RST 20 pF 18.432 MHz * 10 kΩ TSTSUB0 SCKI * 0.47 µF 100 Ω FCONT SCKO 0.1 µF 0.01 µF 10 kΩ VSSA PO4 4.7 kΩ PO3 MCU I/F 120 pF CKO 47 µF PO2 AUDIO SCK 15 kΩ LOCK 100 pF VSS PO1 1 kΩ (1%) 1 kΩ (1%) EXT OUT (3.3 V) 0.1 µF PO0 0.1 µF 50 WR VSS 0.033 µF to 0.1 µF 51 0.1 µF CE OE IO7 VDD IO6 IO5 IO4 IO3 IO2 IO1 IO0 VSS AD0 AD1 AD2 AD3 AD4 AD5 AD6 VDD AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 81 AD15 80 AD16 0.1 µF SRAM I/F (3.3 V) AUDIO I/F (3.3 V) VDDX and VSSX line which the *-mark attached should dissociate and connect with other VDD and VSS line. Note 10: According to the diving noise of outside which receives a power supply line and GND line, etc., or jitters of the input signal, and other operating conditions (power-supply voltage, temperature conditions, etc.), the lock of PLL may separate from this product and it may become unstable. Please determine constant value according to the characteristic of a circuit in the case of use of this product. In addition, the constant value in the example of an application circuit is for explaining operation of this product, and application, and does not offer a guarantee of operation. 30 2002-04-18 TC9446F Maximum Ratings (Ta = 25°C) Characteristics Symbol Rating Unit Power supply voltage VDD −0.3 to +4.0 V Input voltage-1 VIN1 −0.3 to VDD + 0.3 V Input voltage-2 VIN2 −0.3 to VDD + 3.0 V (Note 11) Power dissipation PD 1500 mW Operating temperature Topr −40 to +85 °C Storage temperature Tstg −55 to +150 °C Note 11: MICS , MILP , MIDIO, MICK , LRCKA, BCKA, LRCKB, BCKB, SDI0, SDI1, RX (schmitt input terminals) Electrical Characteristics (unless otherwise specified, Ta = 25°C, VDD = VDDX = VDDA = VDDDL = 3.3 V) DC Characteristics Symbol Test Circuit Operating power supply voltage-1 VDD1 Operating power supply voltage-2 VDD2 Operating frequency range-1 fopr1 Characteristics Test Condition Min Typ. Max Unit Ta = −40 to +85°C, fopr < = 140 MHz 3.0 3.3 3.6 V Ta = −40 to +85°C, fopr > 140 MHz 3.1 3.3 3.6 V DLL oscillation frequency (4th times) 120 MHz 150 MHz 110 160 mA 2.5 0.8 −8 15 Operating frequency range-2 fopr2 DLL oscillation frequency (6th times), At fopr > 140 MHz, VDD = 3.1 to 3.6 V. Power supply current IDD fopr = 150 MHz 75 MIPS operating “H” level VIH1 “L” level VIL1 “H” level IOH1 VOH = 2.8 V IOL1 VOL = 0.5 V Clock Terminals Input voltage Output current “L” level XI pin, (Note 14) XO pin V mA Note 14: CKI, SCKI (CMOS input terminals) 31 2002-04-18 TC9446F Symbol Test Circuit “H” level VIH2 “L” level VIL2 Characteristics Test Condition Min Typ. Max (Note 11), (Note 12), (Note 13), (Note 15) 2.8 0.5 ±10 Unit Input Terminals Input voltage “H” level IIH VIN = VDD Input leakage current (Note 11), (Note 12), (Note 15), AMPI pin “L” level IIL VIN = 0 V (Note 11), (Note 13) V µA ±10 −8 15 −1 1 −8 15 ±10 µA 20 mA ±10 µA AMPI pin Output Terminals “H” level IOH2 VOH = 2.8 V “L” level IOL2 VOL = 0.5 V “H” level IOH3 VOH = 2.8 V IOL3 VOL = 0.5 V “H” level IOH4 VOH = 2.8 V “L” level IOL4 VOL = 0.5 V IOZ4 VOH = VDD, VOL = 0 V IOL6 VOL = 0.5 V Output current Output current “L” level (Note 15), (Note 16), (Note 17) AMPO pin mA mA 3-State Output Terminals Output current Output off leakage current FCONT, PD pins mA Open-Drain Output Terminals Output current “L” level Output off leakage current IOL6 VOH = VDD, VOL = 0 V MIDIO pin Pull-Up Resistor and Pull-Down Resistor Built-In Terminals Pull-up resistor Pull-down resistor Rup VIN = 0 V (Note 12), (Note 15), (Note 16) 45 75 kΩ Rdwn VIN = 3.3 V (Note 13) 55 85 kΩ Note 11: MICS , MILP , MIDIO, MICK , LRCKA, BCKA, LRCKB, BCKB, SDI0, SDI1, RX (schmitt input terminals) Note 12: RST , TSTSUB0 to 2, TEST0 to 3, PLON, DLON, DLCKS, FI0 to 3 (schmitt input terminals with pull-up resistor) Note 13: MIMD, IRQ (schmitt input terminals with pull-down resistor) Note 15: IO0 to 7 (input/output terminals with pull-up resistor) Note 16: PO0 to 7, AD0 to 16, WE , OE , CE (output terminals with pull-up resistor) Note 17: MIACK, SDO0 to 3, LRCKOA, BCKOA, LRCKOB, BCKOB, TXO, CKO, SCKO, LOCK (output terminals) 32 2002-04-18 TC9446F Characteristics Symbol Test Circuit Test Condition Min Typ. Max Unit 30 MHz 40 50 60 % 37 MHz AC Characteristics (1) Timing Clock Input Terminals (XI) DLL oscillation circuit (4th times) fXI fDTY fCI Clock “H” duration tCIH 13 ns Clock “L” duration tCIL 13 ns fSI 150 MHz Clock “H” duration tSIH 3.3 ns Clock “L” duration tSIL 3.3 ns Stand-by time tRRS 10 ms Reset pulse width tWRS 10 µs Clock frequency Clock duty Clock Input Terminals (CKI) Clock frequency 384 fs, fs = 96 kHz Clock Input Terminals (SCKI) Clock frequency 75 MIPS operating Reset Terminal ( RST ) Audio Serial Interface (LRCKA to B, BCKA to B, LRCKOA to B, BCKOA to B, SDI0 to 1, SDO0 to 3) LRCK setup time tLBS CL = 30 pF, fs = 96 kHz 20 ns LRCK hold time tLBH CL = 30 pF, fs = 96 kHz −60 60 ns SDI setup time tSDI CL = 30 pF, fs = 96 kHz 20 ns SDI hold time tHDI CL = 30 pF, fs = 96 kHz 20 ns BCK clock cycle tBCK CL = 30 pF, fs = 96 kHz 160 ns BCK clock “H” duration tBCH CL = 30 pF, fs = 96 kHz 80 ns BCK clock “L” duration tBCL CL = 30 pF, fs = 96 kHz 80 ns SDO output delay time-1 tDO1 CL = 30 pF, fs = 96 kHz 10 ns SDO output delay time-2 tDO2 CL = 30 pF, fs = 96 kHz 10 ns LRCK output delay time tDCLR CL = 30 pF, fs = 96 kHz 10 ns 33 2002-04-18 TC9446F Characteristics Symbol Test Circuit Test Condition Min Typ. Max Unit Micro Controller Interface Serial Transmission Mode ( MICS , MICK , MIDIO, MILP , MIACK) tSTB 25 ms MICS fall-MICK rise setup time t1 0.5 µs MIACK fall-MICK rise setup time t2 0.5 µs MICK clock cycle t3 1.0 µs MICK “L” duration t4 0.5 µs MICK “H” duration t5 0.5 µs MICK rise-MILP fall setup time t6 0.5 µs MILP “duration t7 0.5 µs MIDIO input data setup time t8 0.5 µs MIDIO input data hold time t9 0.5 µs MIDIO output data delay time t10 0.5 µs MICS “H” duration t11 0.5 µs MIACK output delay time t12 0.1 µs MILP rise-MICS rise setup time t13 0.5 µs Stand-by time Note 18: “H” duration of MIACK signal depends on firmware of TC9446F. 2 I C Mode ( MICK , MIDIO) fIFCK CL = 400 pF 0 400 kHz MICK “H” duration tH CL = 400 pF 0.6 µs MICK “L” duration tL CL = 400 pF 1.3 µs tDS CL = 400 pF 0.1 µs Data hold time tDH CL = 400 pF 0 µs Transmission start condition hold time tSCH CL = 400 pF 0.6 µs Repeat transmission start condition setup time tSCS CL = 400 pF 0.6 µs Transmission end condition setup time tECS CL = 400 pF 0.6 µs Data transmission interval MICK clock frequency Data setup time tBUF CL = 400 pF 1.3 µs 2 tR CL = 400 pF 0.1 µs 2 tF CL = 400 pF 0.5 µs I C rise time I C fall time 34 2002-04-18 TC9446F Characteristics Symbol Test Circuit Test Condition Min Typ. Max Unit 14 ns External RAM Memory Interface (WR, OE, CE, IO0 to 7, AD0 to 16) (1) Memory read input/output tASR CL = 30 pF, 75 MIPS operating Address hole time tAHR CL = 30 pF, 75 MIPS operating 0 ns Pre-charge time tPCR CL = 30 pF, 75 MIPS operating 14 ns Read cycle width tRC CL = 30 pF, 75 MIPS operating 27 ns 27 54 80 Address setup time CL = 30 pF, 75 MIPS operating 8 bit, one time access Until read end from chip select tCR CL = 30 pF, 75 MIPS operating 16 bit, two times access CL = 30 pF, 75 MIPS operating 24 bit, three times access ns OE access time of external SRAM tOE CL = 30 pF, 75 MIPS operating 15 ns CE access time of external SRAM tCO CL = 30 pF, 75 MIPS operating 15 ns Output data hold time of external SRAM tOH CL = 30 pF, 75 MIPS operating 0 ns Address access time of external SRAM tACC CL = 30 pF, 75 MIPS operating 15 ns CE disable time of external SRAM tCOD CL = 30 pF, 75 MIPS operating 14 ns Address setup time tASW CL = 30 pF, 75 MIPS operating 14 ns WR pulse width tWP CL = 30 pF, 75 MIPS operating 17 ns Address hold time tAHW CL = 30 pF, 75 MIPS operating 0 ns Pre-charge time tPCW CL = 30 pF, 75 MIPS operating 14 ns Write cycle width tWC CL = 30 pF, 75 MIPS operating 27 ns 27 54 80 (2) Memory write output CL = 30 pF, 75 MIPS operating 8 bit, one time access Until write end from chip select tCW CL = 30 pF, 75 MIPS operating 16 bit, two times access CL = 30 pF, 75 MIPS operating 24 bit, three times access ns Output data setup time tDS CL = 30 pF, 75 MIPS operating 23 ns Output data hold time tDH CL = 30 pF, 75 MIPS operating 4 ns OE setup time tOES CL = 30 pF, 75 MIPS operating 0 ns OE hold time tOEH CL = 30 pF, 75 MIPS operating 0 ns 35 2002-04-18 TC9446F AC Characteristics Measurement Points (1) Clock terminal (XI, CKI, SCKI) Clock 50% tH, tCIH, tSIH tL, tCIL, tSIL fXI, fCI, fSI Duty cycle (fDTY) = tH/(tL + tH) × 100 (%) (2) Reset VDD 100% 0% 90% 90% RST tRRS (3) tWRS Audio serial interface (LRCKx, BCKx, SDIx, LRCKOx, BCKOx, SDOx, CKO) 50% CKO LRCKOx tDCLR 100% 0% 50% tBCK tBCL tBCH LRCKx/ LRCKOx tLBH BCKx/ BCKOx tLBS SDIx tSDI tHDI SDOx tDO1 tDO2 36 2002-04-18 TC9446F (4) Micro controller interface (4-1) Serial transmission interface mode ( MICS , MICK , MIDIO, MILP , MIACK ) RST MICS tSTB MICS t1 t2 ȂǿǹCȀ t4 t3 t12 t5 MICK t6 t7 MILP t9 t8 DATA IN MIDIO DATA OUT MIDIO t10 t11 MICS t13 ȂǿǹCȀ MICK t6 t7 MILP MIDIO MIDIO DATA IN DATA OUT 37 2002-04-18 TC9446F (4-2) I2C mode ( MICK , MIDIO) RST MIDIO (SDA) tSTB tBUF MIDIO (SDA) MICK (SCL) tSCH tR tL tH tDS tDH tSCS tF tECS Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Right to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. 38 2002-04-18 TC9446F (5) External RAM memory interface (5-1) READ cycle timing ADDRESS AD0-AD16 tASR tRC tAHR tCR CE tPCR WR tACC OE tOE tCO tOH IO0-IO7 tCOD DATA IN (5-2) WRITE cycle timing AD0-AD16 ADDRESS tASW tAHW tWC tWC CE tWP tPCW WR OE tOES IO0-IO7 tDS tDH tOEH DATA OUT 39 2002-04-18 TC9446F Package Dimensions Weight: 1.57 g (typ.) 40 2002-04-18 TC9446F RESTRICTIONS ON PRODUCT USE 000707EBA • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. • The products described in this document are subject to the foreign exchange and foreign trade laws. • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. • The information contained herein is subject to change without notice. 41 2002-04-18