LTC1871 Wide Input Range, No RSENSETM Current Mode Boost, Flyback and SEPIC Controller U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO The LTC®1871 is a wide input range, current mode, boost, flyback and SEPIC controller that drives an N-channel power MOSFET and requires very few external components. Intended for low to medium power applications, it eliminates the need for a current sense resistor by utilizing the power MOSFET’s on-resistance, thereby maximizing efficiency. High Efficiency (No Sense Resistor Required) Wide Input Voltage Range: 2.5V to 36V Current Mode Control Provides Excellent Transient Response High Maximum Duty Cycle (92% Typ) ±2% RUN Pin Threshold with 100mV Hysteresis ±1% Internal Voltage Reference Micropower Shutdown: IQ = 10µA Programmable Operating Frequency (50kHz to 1MHz) with One External Resistor Synchronizable to an External Clock Up to 1.3 × fOSC User-Controlled Pulse Skip or Burst Mode® Operation Internal 5.2V Low Dropout Voltage Regulator Output Overvoltage Protection Capable of Operating with a Sense Resistor for High Output Voltage Applications Small 10-Lead MSOP Package The IC’s operating frequency can be set with an external resistor over a 50kHz to 1MHz range, and can be synchronized to an external clock using the MODE/SYNC pin. Burst Mode operation at light loads, a low minimum operating supply voltage of 2.5V and a low shutdown quiescent current of 10µA make the LTC1871 ideally suited for battery-operated systems. For applications requiring constant frequency operation, Burst Mode operation can be defeated using the MODE/ SYNC pin. Higher output voltage boost, SEPIC and flyback applications are possible with the LTC1871 by connecting the SENSE pin to a resistor in the source of the power MOSFET. U APPLICATIO S ■ ■ Telecom Power Supplies Portable Electronic Equipment The LTC1871 is available in the 10-lead MSOP package. , LTC and LT are registered trademarks of Linear Technology Corporation. Burst Mode is a registered trademark of Linear Technology Corporation. No RSENSE is a trademark of Linear Technology Corporation. U TYPICAL APPLICATIO VIN 3.3V Efficiency of Figure 1 L1 1µH 100 D1 90 VIN ITH RC 22k CC1 6.8nF CC2 47pF R2 37.4k 1% + LTC1871 R1 12.1k 1% FB FREQ RT 80.6k 1% VOUT 5V 7A (10A PEAK) MODE/SYNC INTVCC GATE GND CVCC 4.7µF X5R + CIN 22µF 6.3V ×2 M1 COUT1 150µF 6.3V ×4 COUT2 22µF 6.3V X5R ×2 GND Burst Mode OPERATION 80 EFFICIENCY (%) SENSE RUN 70 60 PULSE-SKIP MODE 50 40 1871 F01a CIN: TAIYO YUDEN JMK325BJ226MM COUT1: PANASONIC EEFUEOJ151R COUT2: TAIYO YUDEN JMK325BJ226MM D1: MBRB2515L L1: SUMIDA CEP125-H 1R0MH M1: FAIRCHILD FDS7760A 30 0.001 0.01 0.1 1 OUTPUT CURRENT (A) 10 1871 F01b Figure 1. High Efficiency 3.3V Input, 5V Output Boost Converter (Bootstrapped) 1 LTC1871 W W W AXI U U ABSOLUTE RATI GS U U W PACKAGE/ORDER I FOR ATIO (Note 1) VIN Voltage ............................................... – 0.3V to 36V INTVCC Voltage ........................................... – 0.3V to 7V INTVCC Output Current ........................................ 50mA GATE Voltage ........................... – 0.3V to VINTVCC + 0.3V ITH, FB Voltages ....................................... – 0.3V to 2.7V RUN, MODE/SYNC Voltages ....................... – 0.3V to 7V FREQ Voltage ............................................– 0.3V to 1.5V SENSE Pin Voltage ................................... – 0.3V to 36V Operating Temperature Range (Note 2) .. – 40°C to 85°C Junction Temperature (Note 3) ............................ 125°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C ORDER PART NUMBER TOP VIEW RUN ITH FB FREQ MODE/ SYNC 1 2 3 4 5 10 9 8 7 6 SENSE VIN INTVCC GATE GND LTC1871EMS MS PART MARKING MS PACKAGE 10-LEAD PLASTIC MSOP TJMAX = 125°C, θJA = 120°C/ W LTSX Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = VINTVCC = 5V, VRUN = 1.5V, RFREQ = 80k, VMODE/SYNC = 0V, unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Main Control Loop VIN(MIN) Minimum Input Voltage IQ Input Voltage Supply Current Continuous Mode Burst Mode Operation, No Load Shutdown Mode VRUN+ Rising RUN Input Threshold Voltage VRUN– Falling RUN Input Threshold Voltage 2.5 (Note 4) VMODE/SYNC = 5V, VFB = 1.4V, VITH = 0.75V VMODE/SYNC = 0V, VITH = 0.2V (Note 5) VRUN = 0V 550 250 10 RUN Pin Input Threshold Hysteresis IRUN RUN Input Current VFB Feedback Voltage 1000 500 20 1.348 ● VRUN(HYST) V VITH = 0.2V (Note 5) ● µA µA µA V 1.223 1.198 1.248 1.273 1.298 50 100 150 mV 1 60 nA 1.230 1.242 1.248 V V 18 60 nA 0.002 0.02 %/V 1.218 1.212 V V IFB FB Pin Input Current VITH = 0.2V (Note 5) ∆VFB ∆VIN Line Regulation 2.5V ≤ VIN ≤ 30V ∆VFB ∆VITH Load Regulation VMODE/SYNC = 0V, VTH = 0.5V to 0.90V (Note 5) ∆VFB(OV) ∆FB Pin, Overvoltage Lockout VFB(OV) – VFB(NOM) in Percent gm Error Amplifier Transconductance ITH Pin Load = ±5µA (Note 5) 650 µmho VITH(BURST) Burst Mode Operation ITH Pin Voltage Falling ITH Voltage (Note 5) 0.3 V VSENSE(MAX) Maximum Current Sense Input Threshold Duty Cycle < 20% ● –1 – 0.1 2.5 6 120 % 10 % 150 180 mV ISENSE(ON) SENSE Pin Current (GATE High) VSENSE = 0V 35 50 µA ISENSE(OFF) SENSE Pin Current (GATE Low) VSENSE = 30V 0.1 5 µA 2 LTC1871 ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = VINTVCC = 5V, VRUN = 1.5V, RFREQ = 80k, VMODE/SYNC = 0V, unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP Oscillator Frequency RFREQ = 80k 250 300 MAX UNITS Oscillator fOSC Oscillator Frequency Range 350 kHz 1000 kHz 92 97 % 1.25 1.30 50 DMAX Maximum Duty Cycle fSYNC/fOSC Recommended Maximum Synchronized Frequency Ratio fOSC = 300kHz (Note 6) 87 tSYNC(MIN) MODE/SYNC Minimum Input Pulse Width VSYNC = 0V to 5V 25 tSYNC(MAX) MODE/SYNC Maximum Input Pulse Width VSYNC = 0V to 5V 0.8/fOSC VIL(MODE) Low Level MODE/SYNC Input Voltage VIH(MODE) High Level MODE/SYNC Input Voltage RMODE/SYNC MODE/SYNC Input Pull-Down Resistance VFREQ Nominal FREQ Pin Voltage ns ns 0.3 1.2 V V 50 kΩ 0.62 V Low Dropout Regulator VINTVCC ∆VINTVCC ∆VIN1 ∆VINTVCC ∆VIN2 INTVCC Regulator Output Voltage VIN = 7.5V 5.2 5.4 V INTVCC Regulator Line Regulation 7.5V ≤ VIN ≤ 15V 5.0 8 25 mV INTVCC Regulator Line Regulation 15V ≤ VIN ≤ 30V 70 200 mV VLDO(LOAD) INTVCC Load Regulation 0 ≤ IINTVCC ≤ 20mA, VIN = 7.5V – 0.2 % VDROPOUT INTVCC Regulator Dropout Voltage VIN = 5V, INTVCC Load = 20mA 280 mV IINTVCC Bootstrap Mode INTVCC Supply Current in Shutdown RUN = 0V, SENSE = 5V 10 20 µA tr GATE Driver Output Rise Time CL = 3300pF (Note 7) 17 100 ns tf GATE Driver Output Fall Time CL = 3300pF (Note 7) 8 100 ns –2 GATE Driver Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. Note 2: The LTC1871E is guaranteed to meet performance specifications from 0°C to 70°C. Specifications over the – 40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formula: TJ = TA + (PD • 120°C/W) Note 4: The dynamic input supply current is higher due to power MOSFET gate charging (QG • fOSC). See Applications Information. Note 5: The LTC1871 is tested in a feedback loop that servos VFB to the reference voltage with the ITH pin forced to a voltage between 0V and 1.4V (the no load to full load operating voltage range for the ITH pin is 0.3V to 1.23V). Note 6: In a synchronized application, the internal slope compensation gain is increased by 25%. Synchronizing to a significantly higher ratio will reduce the effective amount of slope compensation, which could result in subharmonic oscillation for duty cycles greater than 50%. Note 7: Rise and fall times are measured at 10% and 90% levels. 3 LTC1871 U W TYPICAL PERFOR A CE CHARACTERISTICS FB Voltage vs Temp FB Voltage Line Regulation FB Pin Current vs Temperature 60 1.231 1.25 50 1.23 FB PIN CURRENT (nA) FB VOLTAGE (V) FB VOLTAGE (V) 1.24 1.230 1.22 40 30 20 10 1.21 –50 –25 1.229 0 0 25 50 75 100 125 150 TEMPERATURE (°C) 5 10 15 20 VIN (V) 25 30 0 –50 –25 35 0 25 50 75 100 125 150 TEMPERATURE (°C) 1871 G02 1871 G01 Shutdown Mode IQ vs VIN 1871 G03 Shutdown Mode IQ vs Temperature 20 30 Burst Mode IQ vs VIN 600 VIN = 5V 20 10 Burst Mode IQ (µA) SHUTDOWN MODE IQ (µA) SHUTDOWN MODE IQ (µA) 500 15 10 400 300 200 5 100 0 0 10 20 VIN (V) 30 0 –50 –25 40 0 10 0 20 VIN (V) 30 1871 G05 1871 G04 Burst Mode IQ vs Temperature 18 Gate Drive Rise and Fall Time vs CL 60 CL = 3300pF IQ(TOT) = 550µA + Qg • f 16 40 1871 G06 Dynamic IQ vs Frequency 500 50 400 14 12 200 40 TIME (ns) 300 IQ (mA) Burst Mode IQ (µA) 0 25 50 75 100 125 150 TEMPERATURE (°C) 10 8 6 RISE TIME 30 20 FALL TIME 4 100 10 2 0 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 1871 G07 4 0 0 0 200 400 600 800 FREQUENCY (kHz) 1000 1200 1871 G08 0 2000 4000 6000 8000 CL (pF) 10000 12000 1871 G09 LTC1871 U W TYPICAL PERFOR A CE CHARACTERISTICS RUN Thresholds vs VIN RUN Thresholds vs Temperature RT vs Frequency 1000 1.40 1.4 1.3 1.2 0 10 20 VIN (V) 30 1.35 RT (kΩ) RUN THRESHOLDS (V) RUN THRESHOLDS (V) 1.5 1.30 1.25 1.20 –50 –25 40 100 10 25 50 75 100 125 150 TEMPERATURE (°C) 0 1871 G10 0 100 200 300 400 500 600 700 800 900 1000 FREQUENCY (kHz) 1871 G12 1871 G11 Maximum Sense Threshold vs Temperature Frequency vs Temperature 325 SENSE Pin Current vs Temperature 35 160 GATE HIGH VSENSE = 0V GATE FREQUENCY (kHz) 315 310 305 300 295 290 285 SENSE PIN CURRENT (µA) MAX SENSE THRESHOLD (mV) 320 155 150 145 30 280 275 –50 –25 0 140 –50 –25 25 50 75 100 125 150 TEMPERATURE (°C) 0 25 –50 –25 25 50 75 100 125 150 TEMPERATURE (°C) 0 25 50 75 100 125 150 TEMPERATURE (°C) 1871 G14 1871 G13 INTVCC Load Regulation 1871 G15 INTVCC Dropout Voltage vs Current, Temperature INTVCC Line Regulation 500 5.4 VIN = 7.5V 450 150°C 5.1 DROPOUT VOLTAGE (mV) INTVCC VOLTAGE (V) INTVCC VOLTAGE (V) 5.2 5.3 5.2 400 125°C 350 75°C 300 25°C 250 200 0°C 150 –50°C 100 50 5.1 5.0 0 10 20 30 40 50 60 INTVCC LOAD (mA) 70 80 1871 G16 0 5 10 15 20 25 VIN (V) 30 0 35 40 1871 G17 0 5 10 15 INTVCC LOAD (mA) 20 1871 G18 5 LTC1871 U U U PI FU CTIO S RUN (Pin 1): The RUN pin provides the user with an accurate means for sensing the input voltage and programming the start-up threshold for the converter. The falling RUN pin threshold is nominally 1.248V and the comparator has 100mV of hysteresis for noise immunity. When the RUN pin is below this input threshold, the IC is shut down and the VIN supply current is kept to a low value (typ 10µA). The Absolute Maximum Rating for the voltage on this pin is 7V. operating frequency to an external clock. If the MODE/ SYNC pin is connected to ground, Burst Mode operation is enabled. If the MODE/SYNC pin is connected to INTVCC, or if an external logic-level synchronization signal is applied to this input, Burst Mode operation is disabled and the IC operates in a continuous mode. ITH (Pin 2): Error Amplifier Compensation Pin. The current comparator input threshold increases with this control voltage. Nominal voltage range for this pin is 0V to 1.40V. INTVCC (Pin 8): The Internal 5.20V Regulator Output. The gate driver and control circuits are powered from this voltage. Decouple this pin locally to the IC ground with a minimum of 4.7µF low ESR tantalum or ceramic capacitor. FB (Pin 3): Receives the feedback voltage from the external resistor divider across the output. Nominal voltage for this pin in regulaton is 1.230V. FREQ (Pin 4): A resistor from the FREQ pin to ground programs the operating frequency of the chip. The nominal voltage at the FREQ pin is 0.6V. MODE/SYNC (Pin 5): This input controls the operating mode of the converter and allows for synchronizing the 6 GND (Pin 6): Ground Pin. GATE (Pin 7): Gate Driver Output. VIN (Pin 9): Main Supply Pin. Must be closely decoupled to ground. SENSE (Pin 10): The Current Sense Input for the Control Loop. Connect this pin to the drain of the power MOSFET for VDS sensing and highest efficiency. Alternatively, the SENSE pin may be connected to a resistor in the source of the power MOSFET. Internal leading edge blanking is provided for both sensing methods. LTC1871 W BLOCK DIAGRA RUN + BIAS AND START-UP CONTROL SLOPE COMPENSATION 1 C2 – 1.248V VIN FREQ V-TO-I 4 OSC 9 0.6V IOSC MODE/SYNC INTVCC 5 85mV + 1.230V S Q GND R + 0.30V FB – 3 1.230V + 7 LOGIC OV – GATE PWM LATCH 50k EA + BURST COMPARATOR CURRENT COMPARATOR SENSE + 10 C1 – – gm ITH V-TO-I 2 INTVCC 8 5.2V ILOOP LDO RLOOP 1.230V SLOPE 1.230V – 2.00V + UV TO START-UP CONTROL GND BIAS VREF 6 1871 BD VIN 7 LTC1871 U OPERATIO Main Control Loop The LTC1871 is a constant frequency, current mode controller for DC/DC boost, SEPIC and flyback converter applications. The LTC1871 is distinguished from conventional current mode controllers because the current control loop can be closed by sensing the voltage drop across the power MOSFET switch instead of across a discrete sense resistor, as shown in Figure 2. This sensing technique improves efficiency, increases power density, and reduces the cost of the overall solution. L D VIN VOUT VIN + SENSE COUT VSW GATE GND GND 2a. SENSE Pin Connection for Maximum Efficiency (VSW < 36V) L D VIN VOUT VIN VSW GATE + SENSE GND GND COUT RS 1871 F02 2b. SENSE Pin Connection for Precise Control of Peak Current or for VSW > 36V Figure 2. Using the SENSE Pin On the LTC1871 For circuit operation, please refer to the Block Diagram of the IC and Figure 1. In normal operation, the power MOSFET is turned on when the oscillator sets the PWM latch and is turned off when the current comparator C1 resets the latch. The divided-down output voltage is compared to an internal 1.230V reference by the error amplifier EA, which outputs an error signal at the ITH pin. The voltage on the ITH pin sets the current comparator C1 input threshold. When the load current increases, a fall in the FB voltage relative to the reference voltage causes the ITH pin 8 to rise, which causes the current comparator C1 to trip at a higher peak inductor current value. The average inductor current will therefore rise until it equals the load current, thereby maintaining output regulation. The nominal operating frequency of the LTC1871 is programmed using a resistor from the FREQ pin to ground and can be controlled over a 50kHz to 1000kHz range. In addition, the internal oscillator can be synchronized to an external clock applied to the MODE/SYNC pin and can be locked to a frequency between 100% and 130% of its nominal value. When the MODE/SYNC pin is left open, it is pulled low by an internal 50k resistor and Burst Mode operation is enabled. If this pin is taken above 2V or an external clock is applied, Burst Mode operation is disabled and the IC operates in continuous mode. With no load (or an extremely light load), the controller will skip pulses in order to maintain regulation and prevent excessive output ripple. The RUN pin controls whether the IC is enabled or is in a low current shutdown state. A micropower 1.248V reference and comparator C2 allow the user to program the supply voltage at which the IC turns on and off (comparator C2 has 100mV of hysteresis for noise immunity). With the RUN pin below 1.248V, the chip is off and the input supply current is typically only 10µA. An overvoltage comparator OV senses when the FB pin exceeds the reference voltage by 6.5% and provides a reset pulse to the main RS latch. Because this RS latch is reset-dominant, the power MOSFET is actively held off for the duration of an output overvoltage condition. The LTC1871 can be used either by sensing the voltage drop across the power MOSFET or by connecting the SENSE pin to a conventional shunt resistor in the source of the power MOSFET, as shown in Figure 2. Sensing the voltage across the power MOSFET maximizes converter efficiency and minimizes the component count, but limits the output voltage to the maximum rating for this pin (36V). By connecting the SENSE pin to a resistor in the source of the power MOSFET, the user is able to program output voltages significantly greater than 36V. LTC1871 U OPERATIO Programming the Operating Mode For applications where maximizing the efficiency at very light loads (e.g., <100µA) is a high priority, the current in the output divider could be decreased to a few microamps and Burst Mode operation should be applied (i.e., the MODE/SYNC pin should be connected to ground). In applications where fixed frequency operation is more critical than low current efficiency, or where the lowest output ripple is desired, pulse-skip mode operation should be used and the MODE/SYNC pin should be connected to the INTVCC pin. This allows discontinuous conduction mode (DCM) operation down to near the limit defined by the chip’s minimum on-time (about 175ns). Below this output current level, the converter will begin to skip cycles in order to maintain output regulation. Figures 3 and 4 show the light load switching waveforms for Burst Mode and pulse-skip mode operation for the converter in Figure␣ 1. Burst Mode Operation Burst Mode operation is selected by leaving the MODE/ SYNC pin unconnected or by connecting it to ground. In normal operation, the range on the ITH pin corresponding to no load to full load is 0.30V to 1.2V. In Burst Mode operation, if the error amplifier EA drives the ITH voltage below 0.525V, the buffered ITH input to the current comparator C1 will be clamped at 0.525V (which corresponds to 25% of maximum load current). The inductor current peak is then held at approximately 30mV divided by the VIN = 3.3V VOUT = 5V IOUT = 500mA power MOSFET RDS(ON). If the ITH pin drops below 0.30V, the Burst Mode comparator B1 will turn off the power MOSFET and scale back the quiescent current of the IC to 250µA (sleep mode). In this condition, the load current will be supplied by the output capacitor until the ITH voltage rises above the 50mV hysteresis of the burst comparator. At light loads, short bursts of switching (where the average inductor current is 20% of its maximum value) followed by long periods of sleep will be observed, thereby greatly improving converter efficiency. Oscilloscope waveforms illustrating Burst Mode operation are shown in Figure 3. Pulse-Skip Mode Operation With the MODE/SYNC pin tied to a DC voltage above 2V, Burst Mode operation is disabled. The internal, 0.525V buffered ITH burst clamp is removed, allowing the ITH pin to directly control the current comparator from no load to full load. With no load, the ITH pin is driven below 0.30V, the power MOSFET is turned off and sleep mode is invoked. Oscilloscope waveforms illustrating this mode of operation are shown in Figure 4. When an external clock signal drives the MODE/SYNC pin at a rate faster than the chip’s internal oscillator, the oscillator will synchronize to it. In this synchronized mode, Burst Mode operation is disabled. The constant frequency associated with synchronized operation provides a more controlled noise spectrum from the converter, at the expense of overall system efficiency of light loads. MODE/SYNC = 0V (Burst Mode OPERATION) VIN = 3.3V VOUT = 5V IOUT = 500mA VOUT 50mV/DIV MODE/SYNC = INTVCC (PULSE-SKIP MODE) VOUT 50mV/DIV IL 5A/DIV IL 5A/DIV 10µs/DIV 1871 F03 Figure 3. LTC1871 Burst Mode Operation (MODE/SYNC = 0V) at Low Output Current 2µs/DIV 1871 F04 Figure 4. LTC1871 Low Output Current Operation with Burst Mode Operation Disabled (MODE/SYNC = INTVCC) 9 LTC1871 U W U U APPLICATIO S I FOR ATIO The external clock signal must exceed 2V for at least 25ns, and should have a maximum duty cycle of 80%, as shown in Figure 5. The MOSFET turn on will synchronize to the rising edge of the external clock signal. to charge and discharge an internal oscillator capacitor. A graph for selecting the value of RT for a given operating frequency is shown in Figure 6. 1000 RT (kΩ) When the oscillator’s internal logic circuitry detects a synchronizing signal on the MODE/SYNC pin, the internal oscillator ramp is terminated early and the slope compensation is increased by approximately 30%. As a result, in applications requiring synchronization, it is recommended that the nominal operating frequency of the IC be programmed to be about 75% of the external clock frequency. Attempting to synchronize to too high an external frequency (above 1.3fO) can result in inadequate slope compensation and possible subharmonic oscillation (or jitter). 100 10 0 100 200 300 400 500 600 700 800 900 1000 FREQUENCY (kHz) 1871 F06 2V TO 7V MODE/ SYNC tMIN = 25ns 0.8T GATE T T = 1/fO Figure 6. Timing Resistor (RT) Value INTVCC Regulator Bypassing and Operation An internal, P-channel low dropout voltage regulator produces the 5.2V supply which powers the gate driver and logic circuitry within the LTC1871, as shown in Figure 7. The INTVCC regulator can supply up to 50mA and must be bypassed to ground immediately adjacent to the IC pins with a minimum of 4.7µF tantalum or ceramic capacitor. Good bypassing is necessary to supply the high transient currents required by the MOSFET gate driver. D = 40% IL 1871 F05 Figure 5. MODE/SYNC Clock Input and Switching Waveforms for Synchronized Operation Programming the Operating Frequency The choice of operating frequency and inductor value is a tradeoff between efficiency and component size. Low frequency operation improves efficiency by reducing MOSFET and diode switching losses. However, lower frequency operation requires more inductance for a given amount of load current. The LTC1871 uses a constant frequency architecture that can be programmed over a 50kHz to 1000kHz range with a single external resistor from the FREQ pin to ground, as shown in Figure 1. The nominal voltage on the FREQ pin is 0.6V, and the current that flows into the FREQ pin is used 10 For input voltages that don’t exceed 7V (the absolute maximum rating for this pin), the internal low dropout regulator in the LTC1871 is redundant and the INTVCC pin can be shorted directly to the VIN pin. With the INTVCC pin shorted to VIN, however, the divider that programs the regulated INTVCC voltage will draw 10µA of current from the input supply, even in shutdown mode. For applications that require the lowest shutdown mode input supply current, do not connect the INTVCC pin to VIN. Regardless of whether the INTVCC pin is shorted to VIN or not, it is always necessary to have the driver circuitry bypassed with a 4.7µF tantalum or low ESR ceramic capacitor to ground immediately adjacent to the INTVCC and GND pins. In an actual application, most of the IC supply current is used to drive the gate capacitance of the power MOSFET. LTC1871 U W U U APPLICATIO S I FOR ATIO INPUT SUPPLY 2.5V TO 30V VIN 1.230V – P-CH + CIN R1 R2 5.2V INTVCC + LOGIC DRIVER GATE CVCC 4.7µF M1 GND 1871 F07 GND PLACE AS CLOSE AS POSSIBLE TO DEVICE PINS Figure 7. Bypassing the LDO Regulator and Gate Driver Supply As a result, high input voltage applications in which a large power MOSFET is being driven at high frequencies can cause the LTC1871 to exceed its maximum junction temperature rating. The junction temperature can be estimated using the following equations: IQ(TOT) ≈ IQ + f • QG PIC = VIN • (IQ + f • QG) TJ = TA + PIC • RTH(JA) The total quiescent current IQ(TOT) consists of the static supply current (IQ) and the current required to charge and discharge the gate of the power MOSFET. The 10-pin MSOP package has a thermal resistance of RTH(JA) = 120°C/W. As an example, consider a power supply with VIN = 5V and VO = 12V at IO = 1A. The switching frequency is 500kHz, and the maximum ambient temperature is 70°C. The power MOSFET chosen is the IRF7805, which has a maximum RDS(ON) of 11mΩ (at room temperature) and a maximum total gate charge of 37nC (the temperature coefficient of the gate charge is low). IQ(TOT) = 600µA + 37nC • 500kHz = 19.1mA PIC = 5V • 19.1mA = 95mW TJ = 70°C + 120°C/W • 95mW = 81.4°C This demonstrates how significant the gate charge current can be when compared to the static quiescent current in the IC. To prevent the maximum junction temperature from being exceeded, the input supply current must be checked when operating in a continuous mode at high VIN. A tradeoff between the operating frequency and the size of the power MOSFET may need to be made in order to maintain a reliable IC junction temperature. Prior to lowering the operating frequency, however, be sure to check with power MOSFET manufacturers for their latest-and-greatest low QG, low RDS(ON) devices. Power MOSFET manufacturing technologies are continually improving, with newer and better performance devices being introduced almost yearly. Output Voltage Programming The output voltage is set by a resistor divider according to the following formula: R2 VO = 1.230 V • 1 + R1 The external resistor divider is connected to the output as shown in Figure 1, allowing remote voltage sensing. The resistors R1 and R2 are typically chosen so that the error 11 LTC1871 U W U U APPLICATIO S I FOR ATIO caused by the current flowing into the FB pin during normal operation is less than 1% (this translates to a maximum value of R1 of about 250k). The turn-on and turn-off input voltage thresholds are programmed using a resistor divider according to the following formulas: Programming Turn-On and Turn-Off Thresholds with the RUN Pin R2 VIN(OFF) = 1.248 V • 1 + R1 The LTC1871 contains an independent, micropower voltage reference and comparator detection circuit that remains active even when the device is shut down, as shown in Figure 8. This allows users to accurately program an input voltage at which the converter will turn on and off. The falling threshold voltage on the RUN pin is equal to the internal reference voltage of 1.248V. The comparator has 100mV of hysteresis to increase noise immunity. R2 VIN(ON) = 1.348 V • 1 + R1 The resistor R1 is typically chosen to be less than 1M. For applications where the RUN pin is only to be used as a logic input, the user should be aware of the 7V Absolute Maximum Rating for this pin! The RUN pin can be connected to the input voltage through an external 1M resistor, as shown in Figure 8c, for “always on” operaton. VIN + R2 RUN + RUN COMPARATOR BIAS AND START-UP CONTROL 6V – INPUT SUPPLY OPTIONAL FILTER CAPACITOR R1 1.248V µPOWER REFERENCE GND – 1871 F8a Figure 8a. Programming the Turn-On and Turn-Off Thresholds Using the RUN Pin VIN + R2 1M RUN COMPARATOR RUN RUN + RUN COMPARATOR 6V INPUT SUPPLY – + 6V EXTERNAL LOGIC CONTROL 1.248V – – GND 1.248V 1871 F08b Figure 8b. On/Off Control Using External Logic 12 1871 F08c Figure 8c. External Pull-Up Resistor On RUN Pin for “Always On” Operation LTC1871 U W U U APPLICATIO S I FOR ATIO Application Circuits A basic LTC1871 application circuit is shown in Figure 1. External component selection is driven by the characteristics of the load and the input supply. The first topology to be analyzed will be the boost converter, followed by SEPIC (single ended primary inductance converter). Boost Converter: Duty Cycle Considerations For a boost converter operating in a continuous conduction mode (CCM), the duty cycle of the main switch is: V +V –V D = O D IN VO + VD where VD is the forward voltage of the boost diode. For converters where the input voltage is close to the output voltage, the duty cycle is low and for converters that develop a high output voltage from a low voltage input supply, the duty cycle is high. The maximum output voltage for a boost converter operating in CCM is: VO(MAX) = VIN(MIN) –V (1– DMAX ) D The maximum duty cycle capability of the LTC1871 is typically 92%. This allows the user to obtain high output voltages from low input supply voltages. Boost Converter: The Peak and Average Input Currents The control circuit in the LTC1871 is measuring the input current (either by using the RDS(ON) of the power MOSFET or by using a sense resistor in the MOSFET source), so the output current needs to be reflected back to the input in order to dimension the power MOSFET properly. Based on the fact that, ideally, the output power is equal to the input power, the maximum average input current is: IO(MAX) IIN(MAX) = 1 – DMAX The maximum duty cycle, DMAX, should be calculated at minimum VIN. Boost Converter: Ripple Current ∆IL and the ‘χ’ Factor The constant ‘χ’ in the equation above represents the percentage peak-to-peak ripple current in the inductor, relative to its maximum value. For example, if 30% ripple current is chosen, then χ = 0.30, and the peak current is 15% greater than the average. For a current mode boost regulator operating in CCM, slope compensation must be added for duty cycles above 50% in order to avoid subharmonic oscillation. For the LTC1871, this ramp compensation is internal. Having an internally fixed ramp compensation waveform, however, does place some constraints on the value of the inductor and the operating frequency. If too large an inductor is used, the resulting current ramp (∆IL) will be small relative to the internal ramp compensation (at duty cycles above 50%), and the converter operation will approach voltage mode (ramp compensation reduces the gain of the current loop). If too small an inductor is used, but the converter is still operating in CCM (near critical conduction mode), the internal ramp compensation may be inadequate to prevent subharmonic oscillation. To ensure good current mode gain and avoid subharmonic oscillation, it is recommended that the ripple current in the inductor fall in the range of 20% to 40% of the maximum average current. For example, if the maximum average input current is 1A, choose a ∆IL between 0.2A and 0.4A, and a value ‘χ’ between 0.2 and 0.4. Boost Converter: Inductor Selection Given an operating input voltage range, and having chosen the operating frequency and ripple current in the inductor, the inductor value can be determined using the following equation: L= VIN(MIN) • DMAX ∆IL • f where: The peak input current is: χ IO(MAX) IIN(PEAK) = 1 + • 2 1 – DMAX ∆IL = χ • IO(MAX) 1 – DMAX 13 LTC1871 U W U U APPLICATIO S I FOR ATIO Remember that boost converters are not short-circuit protected. Under a shorted output condition, the inductor current is limited only by the input supply capability. For applications requiring a step-up converter that is shortcircuit protected, please refer to the applications section covering SEPIC converters. The minimum required saturation current of the inductor can be expressed as a function of the duty cycle and the load current, as follows: χ IO(MAX) IL(SAT) ≥ 1 + • 2 1 – DMAX The saturation current rating for the inductor should be checked at the minimum input voltage (which results in the highest inductor current) and maximum output current. Boost Converter: Operating in Discontinuous Mode Discontinuous mode operation occurs when the load current is low enough to allow the inductor current to run out during the off-time of the switch, as shown in Figure␣ 9. Once the inductor current is near zero, the switch and diode capacitances resonate with the inductance to form damped ringing at 1MHz to 10MHz. If the off-time is long enough, the drain voltage will settle to the input voltage. Depending on the input voltage and the residual energy in the inductor, this ringing can cause the drain of the power MOSFET to go below ground where it is clamped by the body diode. This ringing is not harmful to the IC and it has not been shown to contribute significantly to EMI. Any attempt to damp it with a snubber will degrade the efficiency. VIN = 3.3V IOUT = 200mA VOUT = 5V MOSFET DRAIN VOLTAGE 2V/DIV Once the value for L is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy or Kool Mµ® cores. Actual core loss is independent of core size for a fixed inductor value, but is very dependent on the inductance selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore, copper losses will increase. Generally, there is a tradeoff between core losses and copper losses that needs to be balanced. Ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can concentrate on copper losses and preventing saturation. Ferrite core material saturates “hard,” meaning that the inductance collapses rapidly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequently, output voltage ripple. Do not allow the core to saturate! Molypermalloy (from Magnetics, Inc.) is a very good, low cost core material for toroids, but is more expensive than ferrite. A reasonable compromise from the same manufacturer is Kool Mµ. Boost Converter: Power MOSFET Selection The power MOSFET serves two purposes in the LTC1871: it represents the main switching element in the power path, and its RDS(ON) represents the current sensing element for the control loop. Important parameters for the power MOSFET include the drain-to-source breakdown voltage (BVDSS), the threshold voltage (VGS(TH)), the onresistance (RDS(ON)) versus gate-to-source voltage, the gate-to-source and gate-to-drain charges (QGS and QGD, respectively), the maximum drain current (ID(MAX)) and the MOSFET’s thermal resistances (RTH(JC) and RTH(JA)). The gate drive voltage is set by the 5.2V INTVCC low drop regulator. Consequently, logic-level threshold MOSFETs should be used in most LTC1871 applications. If low input voltage operation is expected (e.g., supplying power from INDUCTOR CURRENT 2A/DIV 2µs/DIV 1871 F09 Figure 9. Discontinuous Mode Waveforms 14 Boost Converter: Inductor Core Selection Kool Mµ is a registered trademark of Magnetics, Inc. LTC1871 U W U U APPLICATIO S I FOR ATIO a lithium-ion battery or a 3.3V logic supply), then sublogiclevel threshold MOSFETs should be used. Pay close attention to the BVDSS specifications for the MOSFETs relative to the maximum actual switch voltage in the application. Many logic-level devices are limited to 30V or less, and the switch node can ring during the turn-off of the MOSFET due to layout parasitics. Check the switching waveforms of the MOSFET directly across the drain and source terminals using the actual PC board layout (not just on a lab breadboard!) for excessive ringing. During the switch on-time, the control circuit limits the maximum voltage drop across the power MOSFET to about 150mV (at low duty cycle). The peak inductor current is therefore limited to 150mV/RDS(ON). The relationship between the maximum load current, duty cycle and the RDS(ON) of the power MOSFET is: RDS(ON) ≤ VSENSE(MAX) • 1 – DMAX χ 1 + • IO(MAX) • ρT 2 IO(MAX) = VSENSE(MAX) • Calculating Power MOSFET Switching and Conduction Losses and Junction Temperatures In order to calculate the junction temperature of the power MOSFET, the power dissipated by the device must be known. This power dissipation is a function of the duty cycle, the load current and the junction temperature itself (due to the positive temperature coefficient of its RDS(ON)). As a result, some iterative calculation is normally required to determine a reasonably accurate value. Since the controller is using the MOSFET as both a switching and a sensing element, care should be taken to ensure that the converter is capable of delivering the required load current over all operating conditions (line voltage and temperature), and for the worst-case specifications for VSENSE(MAX) 2.0 200 150 100 50 0 1 – DMAX χ 1 + • RDS(ON) • ρT 2 It is worth noting that the 1 – DMAX relationship between IO(MAX) and RDS(ON) can cause boost converters with a wide input range to experience a dramatic range of maximum input and output current. This should be taken into consideration in applications where it is important to limit the maximum current drawn from the input supply. ρT NORMALIZED ON RESISTANCE MAXIMUM CURRENT SENSE VOLTAGE (mV) The VSENSE(MAX) term is typically 150mV at low duty cycle, and is reduced to about 100mV at a duty cycle of 92% due to slope compensation, as shown in Figure 10. The ρT term accounts for the temperature coefficient of the RDS(ON) of the MOSFET, which is typically 0.4%/°C. Figure 11 illustrates the variation of normalized RDS(ON) over temperature for a typical power MOSFET. Another method of choosing which power MOSFET to use is to check what the maximum output current is for a given RDS(ON), since MOSFET on-resistances are available in discrete values. 0 0.2 0.5 0.4 DUTY CYCLE 0.8 1.0 1871 F10 Figure 10. Maximum SENSE Threshold Voltage vs Duty Cycle 1.5 1.0 0.5 0 – 50 50 100 0 JUNCTION TEMPERATURE (°C) 150 1871 F11 Figure 11. Normalized RDS(ON) vs Temperature 15 LTC1871 U W U U APPLICATIO S I FOR ATIO and the RDS(ON) of the MOSFET listed in the manufacturer’s data sheet. and the diode junction temperature is: The power dissipated by the MOSFET in a boost converter is: The RTH(JA) to be used in this equation normally includes the RTH(JC) for the device plus the thermal resistance from the board to the ambient temperature in the enclosure. 2 IO(MAX) PFET = • RDS(ON) • DMAX • ρT 1 – DMAX IO(MAX) + k • VO1.85 • •C •f (1– DMAX ) RSS The first term in the equation above represents the I2R losses in the device, and the second term, the switching losses. The constant, k = 1.7, is an empirical factor inversely related to the gate drive current and has the dimension of 1/current. From a known power dissipated in the power MOSFET, its junction temperature can be obtained using the following formula: TJ = TA + PFET • RTH(JA) The RTH(JA) to be used in this equation normally includes the RTH(JC) for the device plus the thermal resistance from the case to the ambient temperature (RTH(CA)). This value of TJ can then be compared to the original, assumed value used in the iterative calculation process. Boost Converter: Output Diode Selection To maximize efficiency, a fast switching diode with low forward drop and low reverse leakage is desired. The output diode in a boost converter conducts current during the switch off-time. The peak reverse voltage that the diode must withstand is equal to the regulator output voltage. The average forward current in normal operation is equal to the output current, and the peak current is equal to the peak inductor current. χ IO(MAX) ID(PEAK) = IL(PEAK) = 1 + • 2 1 – DMAX The power dissipated by the diode is: PD = IO(MAX) • VD 16 TJ = TA + PD • RTH(JA) Remember to keep the diode lead lengths short and to observe proper switch-node layout (see Board Layout Checklist) to avoid excessive ringing and increased dissipation. Boost Converter: Output Capacitor Selection Contributions of ESR (equivalent series resistance), ESL (equivalent series inductance) and the bulk capacitance must be considered when choosing the correct component for a given output ripple voltage. The effects of these three parameters (ESR, ESL and bulk C) on the output voltage ripple waveform are illustrated in Figure 12e for a typical boost converter. The choice of component(s) begins with the maximum acceptable ripple voltage (expressed as a percentage of the output voltage), and how this ripple should be divided between the ESR step and the charging/discharging ∆V. For the purpose of simplicity we will choose 2% for the maximum output ripple, to be divided equally between the ESR step and the charging/discharging ∆V. This percentage ripple will change, depending on the requirements of the application, and the equations provided below can easily be modified. For a 1% contribution to the total ripple voltage, the ESR of the output capacitor can be determined using the following equation: ESRCOUT ≤ 0.01 • VO IIN(PEAK) where: χ IO(MAX) IIN(PEAK)= 1 + • 2 1 – DMAX LTC1871 U W U U APPLICATIO S I FOR ATIO For the bulk C component, which also contributes 1% to the total ripple: COUT ≥ IO(MAX) 0.01 • VO • f For many designs it is possible to choose a single capacitor type that satisfies both the ESR and bulk C requirements for the design. In certain demanding applications, however, the ripple voltage can be improved significantly by connecting two or more types of capacitors in parallel. For example, using a low ESR ceramic capacitor can minimize the ESR step, while an electrolytic capacitor can be used to supply the required bulk C. Once the output capacitor ESR and bulk capacitance have been determined, the overall ripple voltage waveform should be verified on a dedicated PC board (see Board Layout section for more information on component placement). Lab breadboards generally suffer from excessive series inductance (due to inter-component wiring), and these parasitics can make the switching waveforms look significantly worse than they would be on a properly designed PC board. The output capacitor in a boost regulator experiences high RMS ripple currents, as shown in Figure 12. The RMS output capacitor ripple current is: IRMS(COUT) ≈ IO(MAX) • VO – VIN(MIN) VIN(MIN) Note that the ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. Several capacitors may also be placed in parallel to meet size or height requirements in the design. Manufacturers such as Nichicon, United Chemicon and Sanyo should be considered for high performance throughhole capacitors. The OS-CON semiconductor dielectric capacitor available from Sanyo has the lowest product of ESR and size of any aluminum electrolytic, at a somewhat higher price. In surface mount applications, multiple capacitors may have to be placed in parallel in order to meet the ESR or RMS current handling requirements of the application. Aluminum electrolytic and dry tantalum capacitors are both available in surface mount packages. In the case of tantalum, it is critical that the capacitors have been surge tested for use in switching power supplies. An excellent choice is AVX TPS series of surface mount tantalum. Also, ceramic capacitors are now available with extremely low ESR, ESL and high ripple current ratings. Boost Converter: Input Capacitor Selection The input capacitor of a boost converter is less critical than the output capacitor, due to the fact that the inductor is in series with the input and the input current waveform is L VIN D SW VOUT COUT RL 12a. Circuit Diagram IIN IL 12b. Inductor and Input Currents ISW tON 12c. Switch Current ID tOFF IO 12d. Diode and Output Currents ∆VCOUT VOUT (AC) ∆VESR RINGING DUE TO TOTAL INDUCTANCE (BOARD + CAP) 12e. Output Voltage Ripple Waveform Figure 12. Switching Waveforms for a Boost Converter 17 LTC1871 U W U U APPLICATIO S I FOR ATIO Table 1. Recommended Component Manufacturers VENDOR AVX BH Electronics Coilcraft Coiltronics Diodes, Inc Fairchild General Semiconductor International Rectifier IRC Kemet Magnetics Inc Microsemi Murata-Erie Nichicon On Semiconductor Panasonic Sanyo Sumida Taiyo Yuden TDK Thermalloy Tokin Toko United Chemicon Vishay/Dale Vishay/Siliconix Vishay/Sprague Zetex COMPONENTS Capacitors Inductors, Transformers Inductors Inductors Diodes MOSFETs Diodes MOSFETs, Diodes Sense Resistors Tantalum Capacitors Toroid Cores Diodes Inductors, Capacitors Capacitors Diodes Capacitors Capacitors Inductors Capacitors Capacitors, Inductors Heat Sinks Capacitors Inductors Capacitors Resistors MOSFETs Capacitors Small-Signal Discretes continuous (see Figure 12b). The input voltage source impedance determines the size of the input capacitor, which is typically in the range of 10µF to 100µF. A low ESR capacitor is recommended, although it is not as critical as for the output capacitor. The RMS input capacitor ripple current for a boost converter is: VIN(MIN) • DMAX L•f Please note that the input capacitor can see a very high surge current when a battery is suddenly connected to the input of the converter and solid tantalum capacitors can fail catastrophically under these conditions. Be sure to specify surge-tested capacitors! IRMS(CIN) = 0.3 • 18 TELEPHONE (207) 282-5111 (952) 894-9590 (847) 639-6400 (407) 241-7876 (805) 446-4800 (408) 822-2126 (516) 847-3000 (310) 322-3331 (361) 992-7900 (408) 986-0424 (800) 245-3984 (617) 926-0404 (770) 436-1300 (847) 843-7500 (602) 244-6600 (714) 373-7334 (619) 661-6835 (847) 956-0667 (408) 573-4150 (562) 596-1212 (972) 243-4321 (408) 432-8020 (847) 699-3430 (847) 696-2000 (605) 665-9301 (800) 554-5565 (207) 324-4140 (631) 543-7100 WEB ADDRESS avxcorp.com bhelectronics.com coilcraft.com coiltronics.com diodes.com fairchildsemi.com generalsemiconductor.com irf.com irctt.com kemet.com mag-inc.com microsemi.com murata.co.jp nichicon.com onsemi.com panasonic.com sanyo.co.jp sumida.com t-yuden.com component.tdk.com aavidthermalloy.com tokin.com tokoam.com chemi-com.com vishay.com vishay.com vishay.com zetex.com Burst Mode Operation and Considerations The choice of MOSFET RDS(ON) and inductor value also determines the load current at which the LTC1871 enters Burst Mode operation. When bursting, the controller clamps the peak inductor current to approximately: IBURST(PEAK) = 30mV RDS(ON) which represents about 20% of the maximum 150mV SENSE pin voltage. The corresponding average current depends upon the amount of ripple current. Lower inductor values (higher ∆IL) will reduce the load current at which Burst Mode operations begins, since it is the peak current that is being clamped. LTC1871 U W U U APPLICATIO S I FOR ATIO The output voltage ripple can increase during Burst Mode operation if ∆IL is substantially less than IBURST. This can occur if the input voltage is very low or if a very large inductor is chosen. At high duty cycles, a skipped cycle causes the inductor current to quickly decay to zero. However, because ∆IL is small, it takes multiple cycles for the current to ramp back up to IBURST(PEAK). During this inductor charging interval, the output capacitor must supply the load current and a significant droop in the output voltage can occur. Generally, it is a good idea to choose a value of inductor ∆IL between 25% and 40% of IIN(MAX). The alternative is to either increase the value of the output capacitor or disable Burst Mode operation using the MODE/SYNC pin. Burst Mode operation can be defeated by connecting the MODE/SYNC pin to a high logic-level voltage (either with a control input or by connecting this pin to INTVCC). In this mode, the burst clamp is removed, and the chip can operate at constant frequency from continuous conduction mode (CCM) at full load, down into deep discontinuous conduction mode (DCM) at light load. Prior to skipping pulses at very light load (i.e., < 5% of full load), the controller will operate with a minimum switch on-time in DCM. Pulse skipping prevents a loss of control of the output at very light loads and reduces output voltage ripple. Efficiency Considerations: How Much Does VDS Sensing Help? The efficiency of a switching regulator is equal to the output power divided by the input power (×100%). Percent efficiency can be expressed as: % Efficiency = 100% – (L1 + L2 + L3 + …), where L1, L2, etc. are the individual loss components as a percentage of the input power. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Although all dissipative elements in the circuit produce losses, four main sources usually account for the majority of the losses in LTC1871 application circuits: 1. The supply current into VIN. The VIN current is the sum of the DC supply current IQ (given in the Electrical Characteristics) and the MOSFET driver and control currents. The DC supply current into the VIN pin is typically about 550µA and represents a small power loss (much less than 1%) that increases with VIN. The driver current results from switching the gate capacitance of the power MOSFET; this current is typically much larger than the DC current. Each time the MOSFET is switched on and then off, a packet of gate charge QG is transferred from INTVCC to ground. The resulting dQ/dt is a current that must be supplied to the INTVCC capacitor through the VIN pin by an external supply. If the IC is operating in CCM: IQ(TOT) ≈ IQ = f • QG PIC = VIN • (IQ + f • QG) 2. Power MOSFET switching and conduction losses. The technique of using the voltage drop across the power MOSFET to close the current feedback loop was chosen because of the increased efficiency that results from not having a sense resistor. The losses in the power MOSFET are equal to: 2 IO(MAX) PFET = • RDS(ON) • DMAX • ρT 1 – DMAX IO(MAX) • CRSS • f + k • VO1.85 • 1 – DMAX The I2R power savings that result from not having a discrete sense resistor can be calculated almost by inspection. 2 IO(MAX) PR(SENSE) = • RSENSE • DMAX 1 – DMAX To understand the magnitude of the improvement with this VDS sensing technique, consider the 3.3V input, 5V output power supply shown in Figure 1. The maximum load current is 7A (10A peak) and the duty cycle is 39%. Assuming a ripple current of 40%, the peak inductor current is 13.8A and the average is 11.5A. With a maximum sense voltage of about 140mV, the sense 19 LTC1871 U W U U APPLICATIO S I FOR ATIO resistor value would be 10mΩ, and the power dissipated in this resistor would be 514mW at maximum output current. Assuming an efficiency of 90%, this sense resistor power dissipation represents 1.3% of the overall input power. In other words, for this application, the use of VDS sensing would increase the efficiency by approximately 1.3%. IOUT 2A/DIV VOUT (AC) 100mV/DIV For more details regarding the various terms in these equations, please refer to the section Boost Converter: Power MOSFET Selection. 3. The losses in the inductor are simply the DC input current squared times the winding resistance. Expressing this loss as a function of the output current yields: 2 IO(MAX) PR(WINDING) = • RW 1 – DMAX 4. Losses in the boost diode. The power dissipation in the boost diode is: PDIODE = IO(MAX) • VD The boost diode can be a major source of power loss in a boost converter. For the 3.3V input, 5V output at 7A example given above, a Schottky diode with a 0.4V forward voltage would dissipate 2.8W, which represents 7% of the input power. Diode losses can become significant at low output voltages where the forward voltage is a significant percentage of the output voltage. 5. Other losses, including CIN and CO ESR dissipation and inductor core losses, generally account for less than 2% of the total additional loss. Checking Transient Response The regulator loop response can be verified by looking at the load transient response. Switching regulators generally take several cycles to respond to an instantaneous step in resistive load current. When the load step occurs, VO immediately shifts by an amount equal to (∆ILOAD)(ESR), and then CO begins to charge or discharge (depending on the direction of the load step) as shown in Figure 13. The regulator feedback loop acts on the resulting error amp output signal to return VO to its steady-state value. During this recovery time, VO can be monitored for overshoot or ringing that would indicate a stability problem. 20 VIN = 3.3V VOUT = 5V MODE/SYNC = INTVCC (PULSE-SKIP MODE) 100µs/DIV 1871 F13 Figure 13. Load Transient Response for a 3.3V Input, 5V Output Boost Converter Application, 0.7A to 7A Step A second, more severe transient can occur when connecting loads with large (> 1µF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with CO, causing a nearly instantaneous drop in VO. No regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. The only solution is to limit the rise time of the switch drive in order to limit the inrush current di/dt to the load. Boost Converter Design Example The design example given here will be for the circuit shown in Figure 1. The input voltage is 3.3V, and the output is 5V at a maximum load current of 7A (10A peak). 1. The duty cycle is: V + V – V 5 + 0.4 – 3.3 D = O D IN = = 38.9% VO + VD 5 + 0.4 2. Pulse-skip operation is chosen so the MODE/SYNC pin is shorted to INTVCC. 3. The operating frequency is chosen to be 300kHz to reduce the size of the inductor. From Figure 5, the resistor from the FREQ pin to ground is 80k. 4. An inductor ripple current of 40% of the maximum load current is chosen, so the peak input current (which is also the minimum saturation current) is: 7 χ IO(MAX) IIN(PEAK) = 1 + • = 1.2 • = 13.8 A 2 1 – DMAX 1 – 0. 39 LTC1871 U W U U APPLICATIO S I FOR ATIO The inductor ripple current is: ∆IL = χ • IO(MAX) 7 = 0.4 • = 4.6 A 1 – DMAX 1 – 0.39 And so the inductor value is: L= VIN(MIN) 3.3V • DMAX = • 0.39 = 0.93µH ∆IL • f 4.6 A • 300kHz The component chosen is a 1µH inductor made by Sumida (part number CEP125-H 1ROMH) which has a saturation current of greater than 20A. 5. With the input voltage to the IC bootstrapped to the output of the power supply (5V), a logic-level MOSFET can be used. Because the duty cycle is 39%, the maximum SENSE pin threshold voltage is reduced from its low duty cycle typical value of 150mV to approximately 140mV. Assuming a MOSFET junction temperature of 125°C, the room temperature MOSFET RDS(ON) should be less than: 1 – DMAX χ 1 + • IO(MAX) • ρT 2 1 – 0.39 = 0.140 V • = 6.8mΩ 0.4 1+ • 7 A • 1.5 2 RDS(ON) ≤ VSENSE(MAX) • The MOSFET used was the Fairchild FDS7760A, which has a maximum RDS(ON) of 8mΩ at 4.5V VGS, a BVDSS of greater than 30V, and a gate charge of 37nC at 5V VGS. 6. The diode for this design must handle a maximum DC output current of 10A and be rated for a minimum reverse voltage of VOUT, or 5V. A 25A, 15V diode from On Semiconductor (MBRB2515L) was chosen for its high power dissipation capability. 7. The output capacitor usually consists of a high valued bulk C connected in parallel with a lower valued, low ESR ceramic. Based on a maximum output ripple voltage of 1%, or 50mV, the bulk C needs to be greater than: IOUT(MAX) = 0.01 • VOUT • f 7A = 466µF 0.01 • 5V • 300kHz COUT ≥ The RMS ripple current rating for this capacitor needs to exceed: IRMS(COUT) ≥ IO(MAX) • 7A • VO – VIN(MIN) = VIN(MIN) 5V – 3.3V = 5A 3.3V To satisfy this high RMS current demand, four 150µF Panasonic capacitors (EEFUEOJ151R) are required. In parallel with these bulk capacitors, two 22µF, low ESR (X5R) Taiyo Yuden ceramic capacitors (JMK325BJ226MM) are added for HF noise reduction. Check the output ripple with a single oscilloscope probe connected directly across the output capacitor terminals, where the HF switching currents flow. 8. The choice of an input capacitor for a boost converter depends on the impedance of the source supply and the amount of input ripple the converter will safely tolerate. For this particular design and lab setup a 100µF Sanyo Poscap (6TPC 100M), in parallel with two 22µF Taiyo Yuden ceramic capacitors (JMK325BJ226MM) is required (the input and return lead lengths are kept to a few inches, but the peak input current is close to 20A!). As with the output node, check the input ripple with a single oscilloscope probe connected across the input capacitor terminals. PC Board Layout Checklist 1. In order to minimize switching noise and improve output load regulation, the GND pin of the LTC1871 should be connected directly to 1) the negative terminal of the INTVCC decoupling capacitor, 2) the negative terminal of the output decoupling capacitors, 3) the source of the power MOSFET or the bottom terminal of the sense resistor, 4) the negative terminal of the input capacitor and 5) at least one via to the ground plane 21 LTC1871 U W U U APPLICATIO S I FOR ATIO immediately adjacent to Pin 6. The ground trace on the top layer of the PC board should be as wide and short as possible to minimize series resistance and inductance. 2. Beware of ground loops in multiple layer PC boards. Try to maintain one central ground node on the board and use the input capacitor to avoid excess input ripple for high output current power supplies. If the ground plane VIN L1 JUMPER R3 RC R4 CC J1 CIN PIN 1 R2 LTC1871 R1 RT CVCC PSEUDO-KELVIN SIGNAL GROUND CONNECTION COUT SWITCH NODE IS ALSO THE HEAT SPREADER FOR L1, M1, D1 M1 COUT D1 VIAS TO GROUND PLANE VOUT TRUE REMOTE OUTPUT SENSING BULK C 1871 F14 LOW ESR CERAMIC Figure 14. LTC1871 Boost Converter Suggested Layout VIN R3 R4 CC R1 R2 1 RC 2 SENSE VIN ITH 10 SWITCH NODE 9 LTC1871 3 4 RT RUN L1 J1 5 FB FREQ INTVCC GATE MODE/ SYNC GND D1 8 7 M1 6 + CVCC CIN GND + PSEUDO-KELVIN GROUND CONNECTION COUT BOLD LINES INDICATE HIGH CURRENT PATHS Figure 15. LTC1871 Boost Converter Layout Diagram 22 VOUT 1871 F15 LTC1871 U W U U APPLICATIO S I FOR ATIO 5. Check the stress on the power MOSFET by measuring its drain-to-source voltage directly across the device terminals (reference the ground of a single scope probe directly to the source pad on the PC board). Beware of inductive ringing which can exceed the maximum specified voltage rating of the MOSFET. If this ringing cannot be avoided and exceeds the maximum rating of the device, either choose a higher voltage device or specify an avalanche-rated power MOSFET. Not all MOSFETs are created equal (some are more equal than others). 6. Place the small-signal components away from high frequency switching nodes. In the layout shown in Figure 14, all of the small-signal components have been placed on one side of the IC and all of the power components have been placed on the other. This also allows the use of a pseudo-Kelvin connection for the signal ground, where high di/dt gate driver currents flow out of the IC ground pin in one direction (to the bottom plate of the INTVCC decoupling capacitor) and small-signal currents flow in the other direction. 7. If a sense resistor is used in the source of the power MOSFET, minimize the capacitance between the SENSE pin trace and any high frequency switching nodes. The LTC1871 contains an internal leading edge blanking time of approximately 180ns, which should be adequate for most applications. 9. For applications with multiple switching power converters connected to the same input supply, make sure that the input filter capacitor for the LTC1871 is not shared with other converters. AC input current from another converter could cause substantial input voltage ripple, and this could interfere with the operation of the LTC1871. A few inches of PC trace or wire (L ≈ 100nH) between the CIN of the LTC1871 and the actual source VIN should be sufficient to prevent current sharing problems. SEPIC Converter Applications The LTC1871 is also well suited to SEPIC (single-ended primary inductance converter) converter applications. The SEPIC converter shown in Figure 16 uses two inductors. The advantage of the SEPIC converter is the input voltage may be higher or lower than the output voltage, and the output is short-circuit protected. C1 L1 + • VIN D1 VOUT + SW L2 RL COUT • 16a. SEPIC Topology VIN + • VOUT + VIN RL • 16b. Current Flow During Switch On-Time VIN + • D1 + 4. The high di/dt loop from the bottom terminal of the output capacitor, through the power MOSFET, through the boost diode and back through the output capacitors should be kept as tight as possible to reduce inductive ringing. Excess inductance can cause increased stress on the power MOSFET and increase HF noise on the output. If low ESR ceramic capacitors are used on the output to reduce output noise, place these capacitors close to the boost diode in order to keep the series inductance to a minimum. + 3. Place the CVCC capacitor immediately adjacent to the INTVCC and GND pins on the IC package. This capacitor carries high di/dt MOSFET gate drive currents. A low ESR and ESL 4.7µF ceramic capacitor works well here. 8. For optimum load regulation and true remote sensing, the top of the output resistor divider should connect independently to the top of the output capacitor (Kelvin connection), staying away from any high dV/dt traces. Place the divider resistors near the LTC1871 in order to keep the high impedance FB node short. + is to be used for high DC currents, choose a path away from the small-signal components. VOUT + VIN RL • 16c. Current Flow During Switch Off-Time Figures 16. SEPIC Topolgy and Current Flow 23 LTC1871 U W U U APPLICATIO S I FOR ATIO The first inductor, L1, together with the main switch, resembles a boost converter. The second inductor, L2, together with the output diode D1, resembles a flyback or buck-boost converter. The two inductors L1 and L2 can be independent but can also be wound on the same core since identical voltages are applied to L1 and L2 throughout the switching cycle. By making L1 = L2 and winding them on the same core the input ripple is reduced along with cost and size. All of the SEPIC applications information that follows assumes L1 = L2 = L. SEPIC Converter: Duty Cycle Considerations For a SEPIC converter operating in a continuous conduction mode (CCM), the duty cycle of the main switch is: VO + VD D= VIN + VO + VD where VD is the forward voltage of the diode. For converters where the input voltage is close to the output voltage the duty cycle is near 50%. The maximum output voltage for a SEPIC converter is: IL1 IIN SW ON VO(MAX) = ( VIN + VD ) SW OFF 17a. Input Inductor Current DMAX 1 – VD 1 – DMAX 1 – DMAX The maximum duty cycle of the LTC1871 is typically 92%. IO IL2 SEPIC Converter: The Peak and Average Input Currents 17b. Output Inductor Current IIN IC1 IO 17c. DC Coupling Capacitor Current The control circuit in the LTC1871 is measuring the input current (either using the RDS(ON) of the power MOSFET or by means of a sense resistor in the MOSFET source), so the output current needs to be reflected back to the input in order to dimension the power MOSFET properly. Based on the fact that, ideally, the output power is equal to the input power, the maximum input current for a SEPIC converter is: ID1 IO 17d. Diode Current DMAX 1 – DMAX The peak input current is: χ D IIN(PEAK) = 1 + • IO(MAX) • MAX 1 – DMAX 2 VOUT (AC) ∆VCOUT ∆VESR RINGING DUE TO TOTAL INDUCTANCE (BOARD + CAP) 17e. Output Ripple Voltage Figures 17. SEPIC Converter Switching Waveforms 24 IIN(MAX) = IO(MAX) • The maximum duty cycle, DMAX, should be calculated at minimum VIN. The constant ‘χ’ represents the fraction of ripple current in the inductor relative to its maximum value. For example, if 30% ripple current is chosen, then χ = 0.30 and the peak current is 15% greater than the average. LTC1871 U W U U APPLICATIO S I FOR ATIO It is worth noting here that SEPIC converters that operate at high duty cycles (i.e., that develop a high output voltage from a low input voltage) can have very high input currents, relative to the output current. Be sure to check that the maximum load current will not overload the input supply. SEPIC Converter: Inductor Selection For most SEPIC applications the equal inductor values will fall in the range of 10µH to 100µH. Higher values will reduce the input ripple voltage and reduce the core loss. Lower inductor values are chosen to reduce physical size and improve transient response. Like the boost converter, the input current of the SEPIC converter is calculated at full load current and minimum input voltage. The peak inductor current can be significantly higher than the output current, especially with smaller inductors and lighter loads. The following formulas assume CCM operation and calculate the maximum peak inductor currents at minimum VIN: χ V +V IL1(PEAK) = 1 + • IO(MAX) • O D VIN(MIN) 2 χ VIN(MIN) + VD IL2(PEAK) = 1 + • IO(MAX) • VIN(MIN) 2 The ripple current in the inductor is typically 20% to 40% (i.e., a range of ‘χ’ from 0.20 to 0.40) of the maximum average input current occurring at VIN(MIN) and IO(MAX) and ∆IL1 = ∆IL2. Expressing this ripple current as a function of the output current results in the following equations for calculating the inductor value: L= VIN(MIN) • DMAX ∆IL • f where: ∆IL = χ • IO(MAX) • DMAX 1 – DMAX By making L1 = L2 and winding them on the same core, the value of inductance in the equation above is replace by 2L due to mutual inductance. Doing this maintains the same ripple current and energy storage in the inductors. For example, a Coiltronix CTX10-4 is a 10µH inductor with two windings. With the windings in parallel, 10µH inductance is obtained with a current rating of 4A (the number of turns hasn’t changed, but the wire diameter has doubled). Splitting the two windings creates two 10µH inductors with a current rating of 2A each. Therefore, substituting 2L yields the following equation for coupled inductors: L1 = L2 = VIN(MIN) • DMAX 2 • ∆IL • f Specify the maximum inductor current to safely handle IL(PK) specified in the equation above. The saturation current rating for the inductor should be checked at the minimum input voltage (which results in the highest inductor current) and maximum output current. SEPIC Converter: Power MOSFET Selection The power MOSFET serves two purposes in the LTC1871: it represents the main switching element in the power path, and its RDS(ON) represents the current sensing element for the control loop. Important parameters for the power MOSFET include the drain-to-source breakdown voltage (BVDSS), the threshold voltage (VGS(TH)), the onresistance (RDS(ON)) versus gate-to-source voltage, the gate-to-source and gate-to-drain charges (QGS and QGD, respectively), the maximum drain current (ID(MAX)) and the MOSFET’s thermal resistances (RTH(JC) and RTH(JA)). The gate drive voltage is set by the 5.2V INTVCC low dropout regulator. Consequently, logic-level threshold MOSFETs should be used in most LTC1871 applications. If low input voltage operation is expected (e.g., supplying power from a lithium-ion battery), then sublogic-level threshold MOSFETs should be used. The maximum voltage that the MOSFET switch must sustain during the off-time in a SEPIC converter is equal to the sum of the input and output voltages (VO + VIN). As a result, careful attention must be paid to the BVDSS specifications for the MOSFETs relative to the maximum actual switch voltage in the application. Many logic-level devices are limited to 30V or less. Check the switching waveforms directly across the drain and source terminals of the power 25 LTC1871 U W U U APPLICATIO S I FOR ATIO MOSFET to ensure the VDS remains below the maximum rating for the device. During the MOSFET’s on-time, the control circuit limits the maximum voltage drop across the power MOSFET to about 150mV (at low duty cycle). The peak inductor current is therefore limited to 150mV/RDS(ON). The relationship between the maximum load current, duty cycle and the RDS(ON) of the power MOSFET is: RDS(ON) ≤ VSENSE(MAX) 1 • IO(MAX) χ 1 + • ρT 2 • 1 VO + VD V +1 IN(MIN) The VSENSE(MAX) term is typically 150mV at low duty cycle and is reduced to about 100mV at a duty cycle of 92% due to slope compensation, as shown in Figure 8. The constant ‘χ’ in the denominator represents the ripple current in the inductors relative to their maximum current. For example, if 30% ripple current is chosen, then χ = 0.30. The ρT term accounts for the temperature coefficient of the RDS(ON) of the MOSFET, which is typically 0.4%/°C. Figure 9 illustrates the variation of normalized RDS(ON) over temperature for a typical power MOSFET. Another method of choosing which power MOSFET to use is to check what the maximum output current is for a given RDS(ON) since MOSFET on-resistances are available in discrete values. IO(MAX) ≤ VSENSE(MAX) 1 • RDS(ON) χ 1 + • ρT 2 • 1 VO + VD V +1 IN(MIN) Calculating Power MOSFET Switching and Conduction Losses and Junction Temperatures In order to calculate the junction temperature of the power MOSFET, the power dissipated by the device must be known. This power dissipation is a function of the duty cycle, the load current and the junction temperature itself. As a result, some iterative calculation is normally required to determine a reasonably accurate value. Since the controller is using the MOSFET as both a switching and a sensing element, care should be taken to ensure that the converter is capable of delivering the required load current 26 over all operating conditions (load, line and temperature) and for the worst-case specifications for VSENSE(MAX) and the RDS(ON) of the MOSFET listed in the manufacturer’s data sheet. The power dissipated by the MOSFET in a SEPIC converter is: 2 D PFET = IO(MAX) • MAX • RDS(ON) • DMAX • ρT 1 – DMAX 1.85 D + k • VIN(MIN) + VO • IO(MAX) • MAX • CRSS • f 1 – DMAX ( ) The first term in the equation above represents the I2R losses in the device and the second term, the switching losses. The constant k = 1.7 is an empirical factor inversely related to the gate drive current and has the dimension of 1/current. From a known power dissipated in the power MOSFET, its junction temperature can be obtained using the following formula: TJ = TA + PFET •RTH(JA) The RTH(JA) to be used in this equation normally includes the RTH(JC) for the device plus the thermal resistance from the board to the ambient temperature in the enclosure. This value of TJ can then be used to check the original assumption for the junction temperature in the iterative calculation process. SEPIC Converter: Output Diode Selection To maximize efficiency, a fast-switching diode with low forward drop and low reverse leakage is desired. The output diode in a SEPIC converter conducts current during the switch off-time. The peak reverse voltage that the diode must withstand is equal to VIN(MAX) + VO. The average forward current in normal operation is equal to the output current, and the peak current is equal to: V +V χ ID(PEAK) = 1 + • IO(MAX) • O D + 1 2 VIN(MIN) The power dissipated by the diode is: PD = IO(MAX) • VD LTC1871 U W U U APPLICATIO S I FOR ATIO SEPIC Converter: Output Capacitor Selection For many designs it is possible to choose a single capacitor type that satisfies both the ESR and bulk C requirements for the design. In certain demanding applications, however, the ripple voltage can be improved significantly by connecting two or more types of capacitors in parallel. For example, using a low ESR ceramic capacitor can minimize the ESR step, while an electrolytic or tantalum capacitor can be used to supply the required bulk C. Because of the improved performance of today’s electrolytic, tantalum and ceramic capacitors, engineers need to consider the contributions of ESR (equivalent series resistance), ESL (equivalent series inductance) and the bulk capacitance when choosing the correct component for a given output ripple voltage. The effects of these three parameters (ESR, ESL, and bulk C) on the output voltage ripple waveform are illustrated in Figure 17 for a typical coupled-inductor SEPIC converter. Once the output capacitor ESR and bulk capacitance have been determined, the overall ripple voltage waveform should be verified on a dedicated PC board (see Board Layout section for more information on component placement). Lab breadboards generally suffer from excessive series inductance (due to inter-component wiring), and these parasitics can make the switching waveforms look significantly worse than they would be on a properly designed PC board. The choice of component(s) begins with the maximum acceptable ripple voltage (expressed as a percentage of the output voltage), and how this ripple should be divided between the ESR step and the charging/discharging ∆V. For the purpose of simplicity we will choose 2% for the maximum output ripple, to be divided equally between the ESR step and the charging/discharging ∆V. This percentage ripple will change, depending on the requirements of the application, and the equations provided below can easily be modified. The output capacitor in a SEPIC regulator experiences high RMS ripple currents, as shown in Figure 17. The RMS output capacitor ripple current is: and the diode junction temperature is: TJ = TA + PD • RTH(JA) The RTH(JA) to be used in this equation normally includes the RTH(JC) for the device plus the thermal resistance from the board to the ambient temperature in the enclosure. For a 1% contribution to the total ripple voltage, the ESR of the output capacitor can be determined using the following equation: 0.01 • VO ESRCOUT ≤ ID(PEAK) where: V +V χ ID(PEAK) = 1 + • IO(MAX) • O D + 1 2 VIN(MIN) For the bulk C component, which also contributes 1% to the total ripple: COUT ≥ IO(MAX) 0.01 • VO • f IRMS(COUT) = IO(MAX) • VO VIN(MIN) Note that the ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. Several capacitors may also be placed in parallel to meet size or height requirements in the design. Manufacturers such as Nichicon, United Chemicon and Sanyo should be considered for high performance throughhole capacitors. The OS-CON semiconductor dielectric capacitor available from Sanyo has the lowest product of ESR and size of any aluminum electrolytic, at a somewhat higher price. In surface mount applications, multiple capacitors may have to be placed in parallel in order to meet the ESR or RMS current handling requirements of the application. Aluminum electrolytic and dry tantalum capacitors are both available in surface mount packages. In the case of tantalum, it is critical that the capacitors have been surge tested for use in switching power supplies. An excellent 27 LTC1871 U W U U APPLICATIO S I FOR ATIO choice is AVX TPS series of surface mount tantalum. Also, ceramic capacitors are now available with extremely low ESR, ESL and high ripple current ratings. SEPIC Converter: Input Capacitor Selection The input capacitor of a SEPIC converter is less critical than the output capacitor due to the fact that an inductor is in series with the input and the input current waveform is triangular in shape. The input voltage source impedance determines the size of the input capacitor which is typically in the range of 10µF to 100µF. A low ESR capacitor is recommended, although it is not as critical as for the output capacitor. The RMS input capacitor ripple current for a SEPIC converter is: IRMS(CIN) = 1 12 SEPIC Converter: Selecting the DC Coupling Capacitor The coupling capacitor C1 in Figure 16 sees nearly a rectangular current waveform as shown in Figure 17. During the switch off-time the current through C1 is IO(VO/ VIN) while approximately – IO flows during the on-time. This current waveform creates a triangular ripple voltage on C1: IO(MAX) C1 • f • VO VIN + VO + VD The maximum voltage on C1 is then: VC1(MAX) = VIN + 28 IRMS(C1) = IO(MAX) • VO + VD VIN(MIN) The value chosen for the DC coupling capacitor normally starts with the minimum value that will satisfy 1) the RMS current requirement and 2) the peak voltage requirement (typically close to VIN). Low ESR ceramic and tantalum capacitors work well here. SEPIC Converter Design Example The design example given here will be for the circuit shown in Figure 18. The input voltage is 5V to 15V and the output is 12V at a maximum load current of 1.5A (2A peak). 1. The duty cycle range is: • ∆IL Please note that the input capacitor can see a very high surge current when a battery is suddenly connected to the input of the converter and solid tantalum capacitors can fail catastrophically under these conditions. Be sure to specify surge-tested capacitors! ∆VC1(P−P) = which is typically close to VIN(MAX). The ripple current through C1 is: ∆VC1(P−P) 2 VO + VD D= = 45.5% to 71.4% VIN + VO + VD 2. The operating mode chosen is pulse skipping, so the MODE/SYNC pin is shorted to INTVCC. 3. The operating frequency is chosen to be 300kHz to reduce the size of the inductors; the resistor from the FREQ pin to ground is 80k. 4. An inductor ripple current of 40% is chosen, so the peak input current (which is also the minimum saturation current) is: V +V χ IL1(PEAK) = 1 + • IO(MAX) • O D 2 VIN(MIN) 12 + 0.5 0.4 = 1+ = 4.5A • 1.5 • 2 5 The inductor ripple current is: DMAX 1 – DMAX 0.714 = 0.4 • 1.5 • = 1.5A 1 – 0.714 ∆IL = χ • IO(MAX) • LTC1871 U W U U APPLICATIO S I FOR ATIO And so the inductor value is: L= VIN(MIN) 5 • DMAX = • 0.714 = 4µH 2 • ∆IL • f 2 • 1.5 • 300k = The component chosen is a BH Electronics BH5101007, which has a saturation current of 8A. 5. With an minimum input voltage of 5V, only logic-level power MOSFETs should be considered. Because the maximum duty cycle is 71.4%, the maximum SENSE pin threshold voltage is reduced from its low duty cycle typical value of 150mV to approximately 120mV. Assuming a MOSFET junction temperature of 125°C, the room temperature MOSFET RDS(ON) should be less than: 2 RC 33k CC1 R1 6.8nF 12.1k 1% R2 105k 1% VIN ITH 4 RT 80.6k 1% 5 FB 10 D1 GATE MODE/SYNC GND VOUT 12V 1.5A (2A PEAK) 9 + INTVCC FREQ 8 7 M1 6 CVCC 4.7µF X5R + CIN 47µF L2* COUT1 47µF 20V ×2 COUT2 10µF 25V X5R ×2 • GND 1871 F018a CIN, COUT1: KEMET T495X476K020AS CDC, COUT2: TAIYO YUDEN TMK432BJ106MM D1: INTERNATIONAL RECTIFIER 30BQ040 L1, L2: BH ELECTRONICS BH510-1007 (*COUPLED INDUCTORS) M1: INTERNATIONAL RECTIFIER IRF7811W Figure 18a. 4.5V to 15V Input, 12V/2A Output SEPIC Converter 100 95 90 85 EFFICIENCY (%) CC2 47pF CDC 10µF 25V X5R L1* SENSE VO + VD V +1 IN(MIN) VIN 4.5V to 15V • RUN 1 For a SEPIC converter, the switch BVDSS rating must be greater than VIN(MAX) + VO, or 27V. This comes close to an IRF7811W, which is rated to 30V, and has a maximum room temperature RDS(ON) of 12mΩ at VGS = 4.5V. LTC1871 3 • 0.12 1 1 • • = 12.7mΩ 1.5 1.2 • 1.5 12.5 + 1 5 R3 1M 1 VSENSE(MAX) 1 • χ IO(MAX) 1 + • ρT 2 RDS(ON) ≤ 80 75 VIN = 12V VIN = 4.5V VIN = 15V 70 65 60 55 50 45 0.001 VO = 12V MODE = INTVCC 0.01 0.1 1 OUTPUT CURRENT (A) 10 1871 F18b Figure 18b. SEPIC Efficiency vs Output Current 29 LTC1871 U W U U APPLICATIO S I FOR ATIO VIN = 4.5V VOUT = 12V VIN = 15V VOUT = 12V VOUT (AC) 200mV/DIV VOUT (AC) 200mV/DIV IOUT 0.5A/DIV IOUT 0.5A/DIV 50µs/DIV 50µs/DIV 1871 F19a 1871 F19b Figure 19. LTC1871 SEPIC Converter Load Step Response 6. The diode for this design must handle a maximum DC output current of 2A and be rated for a minimum reverse voltage of VIN + VOUT, or 27V. A 3A, 40V diode from International Rectifier (30BQ040) is chosen for its small size, relatively low forward drop and acceptable reverse leakage at high temp. 7. The output capacitor usually consists of a high valued bulk C connected in parallel with a lower valued, low ESR ceramic. Based on a maximum output ripple voltage of 1%, or 120mV, the bulk C needs to be greater than: IOUT(MAX) = 0.01 • VOUT • f 1.5A = 41µF 0.01 • 12V • 300kHz COUT ≥ The RMS ripple current rating for this capacitor needs to exceed: IRMS(COUT) ≥ IO(MAX) • 1.5A • VO VIN(MIN) = 12V = 2.3A 5V To satisfy this high RMS current demand, two 47µF Kemet capacitors (T495X476K020AS) are required. As a result, the output ripple voltage is a low 50mV to 60mV. In parallel with these tantalums, two 10µF, low ESR (X5R) Taiyo Yuden ceramic capacitors (TMK432BJ106MM) are added for HF noise reduction. 30 Check the output ripple with a single oscilloscope probe connected directly across the output capacitor terminals, where the HF switching currents flow. 8. The choice of an input capacitor for a SEPIC converter depends on the impedance of the source supply and the amount of input ripple the converter will safely tolerate. For this particular design and lab setup, a single 47µF Kemet tantalum capacitor (T495X476K020AS) is adequate. As with the output node, check the input ripple with a single oscilloscope probe connected across the input capacitor terminals. If any HF switching noise is observed it is a good idea to decouple the input with a low ESR, X5R ceramic capacitor as close to the VIN and GND pins as possible. 9. The DC coupling capacitor in a SEPIC converter is chosen based on its RMS current requirement and must be rated for a minimum voltage of VIN plus the AC ripple voltage. Start with the minimum value which satisfies the RMS current requirement and then check the ripple voltage to ensure that it doesn’t exceed the DC rating. IRMS(CI) ≥ IO(MAX) • = 1.5A • VO + VD VIN(MIN) 12V + 0.5V = 2.4A 5V For this design a single 10µF, low ESR (X5R) Taiyo Yuden ceramic capacitor (TMK432BJ106MM) is adequate. LTC1871 U TYPICAL APPLICATIO S 2.5V to 3.3V Input, 5V/2A Output Boost Converter VIN 2.5V to 3.3V L1 1.8µH 1 2 RC 22k SENSE ITH VIN 10 CC1 R1 6.8nF 12.1k 1% R2 37.4k 1% 4 RT 80.6k 1% 5 FB + INTVCC FREQ MODE/SYNC GATE GND VOUT 5V 2A 9 LTC1871 3 8 7 6 M1 CVCC 4.7µF X5R + CIN 47µF 6.3V COUT1 150µF 6.3V ×2 COUT2 10µF 6.3V X5R ×2 GND 1871 TA01a CIN: COUT1: COUT2: CVCC: SANYO POSCAP 6TPA47M SANYO POSCAP 6TPB150M TAIYO YUDEN JMK316BJ106ML TAIYO YUDEN LMK316BJ475ML D1: INTERNATIONAL RECTIFIER 30BQ015 L1: TOKO DS104C2 B952AS-1R8N M1: SILICONIX/VISHAY Si9426 Output Efficiency at 2.5V and 3.3V Input 100 95 90 85 EFFICIENCY (%) CC2 47pF RUN D1 80 75 70 65 60 55 50 0.001 0.01 0.1 1 OUTPUT CURRENT (A) 10 1871 TA01b 31 LTC1871 U TYPICAL APPLICATIO S 18V to 27V Input, 28V Output, 400W 2-Phase, Low Ripple, Synchronized RF Base Station Power Supply (Boost) VIN 18V to 27V R1 93.1k 1% R2 8.45k 1% L1 5.6µH 1 2 CC1 47pF SENSE RUN VIN ITH 10 CFB1 47pF RT1 150k 5% 5 FB INTVCC FREQ GATE MODE/SYNC GND 1 2 D1 CC3 6.8nF VIN ITH 7 M1 6 CVCC1 4.7µF X5R CIN2 2.2µF 35V X5R CFB2 47pF R3 12.1k 1% R4 261k 1% 4 RT2 150k 5% 5 FB INTVCC FREQ GATE MODE/SYNC GND + COUT2 330µF 50V RS1 0.007Ω 1W 10 GND COUT5* 330µF 50V ×4 L4 5.6µH + COUT6* 2.2µF 35V X5R D2 VOUT 28V 14A 9 LTC1871 3 COUT1 2.2µF 35V X5R ×3 8 L3 5.6µH SENSE RUN CIN1 330µF 50V 9 EXT CLOCK INPUT (200kHz) CC2 47pF + LTC1871 3 4 RC 22k L2 5.6µH 8 7 M2 6 CVCC2 4.7µF X5R CIN3 2.2µF 35V X5R COUT3 2.2µF + 35V X5R ×3 L5* 0.3µH COUT4 330µF 50V *L5, COUT5 AND COUT6 ARE AN OPTIONAL SECONDARY FILTER TO REDUCE OUTPUT RIPPLE FROM <500mVP-P TO <100mVP-P RS2 0.007Ω 1W 1871 TA04 CIN1: CIN2, 3: COUT2, 4, 5: COUT1, 3, 6: CVCC1, 2: SANYO 50MV330AX TAIYO YUDEN GMK325BJ225MN SANYO 50MV330AX TAIYO YUDEN GMK325BJ225MN TAIYO YUDEN LMK316BJ475ML L1 TO L4: L5: D1, D2: M1, M2: SUMIDA CEP125-5R6MC-HD SUMIDA CEP125-0R3NC-ND ON SEMICONDUCTOR MBR2045CT INTERNATIONAL RECTIFIER IRLZ44NS 5V to 12V Input, ±12V/0.2A Output SEPIC Converter with Undervoltage Lockout R2 54.9k 1% R1 127k 1% L1* 1 2 RC 22k CC2 100pF RUN SENSE ITH VIN 10 CDC1 4.7µF 16V X5R D1 VOUT1 12V 0.4A 9 LTC1871 3 CC1 R4 6.8nF 127Ω 1% R3 1.10k 1% 4 RT 60.4k 1% 5 FB INTVCC GATE FREQ MODE/SYNC NOTE: 1. VIN UVLO + = 4.47V VIN UVLO– = 4.14V 32 VIN 5V to 12V • GND COUT1 4.7µF 16V X5R ×3 8 7 6 L2* M1 CVCC 4.7µF 10V X5R CIN1 1µF 16V X5R + CIN2 47µF 16V AVX D1, D2: MBS120T3 L1 TO L3: COILTRONICS VP1-0076 (*COUPLED INDUCTORS) M1: SILICONIX/VISHAY Si4840 • RS 0.02Ω CDC2 4.7µF 16V X5R D2 L3* • GND COUT2 4.7µF 16V X5R VOUT2 ×3 –12V 1871 TA03 0.4A LTC1871 U TYPICAL APPLICATIO S 4.5V to 28V Input, 5V/2A Output SEPIC Converter with Undervoltage Lockout and Soft-Start R2 54.9k 1% R1 115k 1% C1 4.7nF • L1* 1 2 RC 12k SENSE RUN VIN ITH 10 VIN 4.5V to 28V CDC 2.2µF 25V X5R ×3 D1 + LTC1871 3 CC1 8.2nF R3 154k 1% CC2 47pF R4 49.9k 1% FB 4 RT 162k 1% INTVCC FREQ 5 GATE MODE/SYNC GND VOUT 5V 2A (3A TO 4A PEAK) 9 8 7 6 CVCC 4.7µF 10V X5R CIN1 2.2µF 35V X5R M1 + CIN2 22µF 35V L2* • COUT1 330µF 6.3V COUT2 22µF 6.3V X5R GND 1871 TA02a R5 100Ω C2 1µF X5R Q1 NOTES: 1. VIN UVLO + = 4.17V VIN UVLO– = 3.86V 2. SOFT-START dVOUT/dt = 5V/6ms R6 750Ω CIN1, CDC: CIN2: COUT1: COUT2: CVCC: TAIYO YUDEN GMK325BJ225MN AVX TPSE226M035R0300 SANYO 6TPB330M TAIYO YUDEN JMK325BJ226MN LMK316BJ475ML D1: L1, L2: M1: Q1: INTERNATIONAL RECTIFIER 30BQ040 BH ELECTRONICS BH510-1007 (*COUPLED INDUCTORS) SILICONIX/VISHAY Si4840 PHILIPS BC847BF Soft-Start Load Step Response at VIN = 4.5V VOUT 100mV/DIV (AC) VOUT 1V/DIV IOUT 2.2A 1A/DIV (DC) 0.5A 1ms/DIV 250µs/DIV 1871 TA02b 1871 TA02c Load Step Response at VIN = 28V VOUT 100mV/DIV (AC) IOUT 1A/DIV (DC) 2.2A 0.5A 250µs/DIV 1871 TA02d 33 LTC1871 U TYPICAL APPLICATIO S 5V to 15V Input, – 5V/5A Output Positive-to-Negative Converter with Undervoltage Lockout and Level-Shifted Feedback • R1 154k 1% R2 68.1k C1 1% 1nF 2 SENSE RUN VIN ITH 4 5 CC2 330pF FB FREQ MODE/SYNC INTVCC GATE GND 9 COUT 100µF 6.3V X5R ×2 CDC 22µF 25V X7R M1 8 7 6 CIN 47µF 16V X5R CVCC 4.7µF 10V X5R RT 80.6k 1% R4 10k 1% 6 1 – R3 10k 1% L2* 10 LTC1871 3 RC 10k CC1 10nF • L1* 1 VIN 5V to 15V VOUT –5V 5A 4 D1 GND C2 10nF R5 40.2k 1% LT1783 3 + 2 CIN: CDC: COUT: CVCC: 34 TDK C5750X5R1C476M TDK C5750X7R1E226M TDK C5750X5R0J107M TAIYO YUDEN LMK316BJ475ML D1: ON SEMICONDUCTOR MBRB2035CT L1, L2: COILTRONICS VP5-0053 (*3 WINDINGS IN PARALLEL FOR THE PRIMARY, 3 IN PARALLEL FOR SECONDARY) M1: INTERNATIONAL RECTIFIER IRF7822 1871 TA05 LTC1871 U PACKAGE DESCRIPTIO MS Package 10-Lead Plastic MSOP (Reference LTC DWG # 05-08-1661) 0.889 ± 0.127 (.035 ± .005) 5.23 (.206) MIN 3.2 – 3.45 (.126 – .136) 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 0.50 3.05 ± 0.38 (.0197) (.0120 ± .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT WITHOUT EXPOSED PAD OPTION 0.254 (.010) 0.497 ± 0.076 (.0196 ± .003) REF 10 9 8 7 6 3.00 ± 0.102 (.118 ± .004) NOTE 4 4.88 ± 0.10 (.192 ± .004) DETAIL “A” 0° – 6° TYP GAUGE PLANE 1 2 3 4 5 0.53 ± 0.01 (.021 ± .006) DETAIL “A” 0.86 (.034) REF 1.10 (.043) MAX 0.18 (.007) SEATING PLANE 0.17 – 0.27 (.007 – .011) 0.50 (.0197) TYP 0.13 ± 0.05 (.005 ± .002) MSOP (MS) 1001 NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 35 LTC1871 U TYPICAL APPLICATIO S High Power SLIC Supply with Undervoltage Lockout GND • D2 10BQ060 4 R1 49.9k 1% R2 150k 1% CR 1nF + CIN 220µF 16V TPS D3 10BQ060 + C4 10µF 25V X5R D4 10BQ060 + C5 10µF 25V X5R • • FB C2 4.7µF 50V IRL2910 X5R INTVCC FREQ MODE/SYNC GATE GND + f = 200kHz C1 4.7µF X5R *COILTRONICS VP5-0155 (PRIMARY = 3 WINDINGS IN PARALLEL) 6 RF1 10k 1% RS 0.012Ω 6 10k 1 RF2 196k 1% 4 + LTC1871 RT 120k 5 + COUT 3.3µF 100V VIN ITH CC1 1nF • T1* 1, 2, 3 SENSE RUN RC 82k VOUT1 –24V 200mA – CC2 100pF + VIN 7V TO 12V C3 10µF 25V X5R 3 VOUT2 –72V 200mA LT1783 C8 0.1µF 2 1871 TA06 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT®1619 Current Mode PWM Controller 300kHz Fixed Frequency, Boost, SEPIC, Flyback Topology LTC1624 Current Mode DC/DC Controller SO-8; 300kHz Operating Frequency; Buck, Boost, SEPIC Design; VIN Up to 36V LTC1700 No RSENSE Synchronous Step-Up Controller Up to 95% Efficiency, Operation as Low as 0.9V Input LTC1872 SOT-23 Boost Controller Delivers Up to 5A, 550kHz Fixed Frequency, Current Mode LT1930 1.2MHz, SOT-23 Boost Converter Up to 34V Output, 2.6V ≤ VIN ≤ 16V, Miniature Design LT1931 Inverting 1.2MHz, SOT-23 Converter Positive-to-Negative DC/DC Conversion, Miniature Design LTC3401/LTC3402 1A/2A 3MHz Synchronous Boost Converters Up to 97% Efficiency, Very Small Solution, 0.5V ≤ VIN ≤ 5V 36 Linear Technology Corporation sn1871 1871fs LT/TP 1001 2K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LINEAR TECHNOLOGY CORPORATION 2001