TI SN74ALVC16269

SCAS417B − OCTOBER 1993 − REVISED JULY 1995
D EPIC  ( Enhanced-Performance Implanted
D
D
D
D
D
DGG OR DL PACKAGE
(TOP VIEW)
CMOS) Submicron Process
Member of the Texas Instruments
Widebus  Family
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
Bus Hold on Data Inputs Eliminates
the Need for External Pullup/ Pulldown
Resistors
Package Options Include Plastic Shrink
Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
OEA
OEB1
2B3
GND
2B2
2B1
VCC
A1
A2
A3
GND
A4
A5
A6
A7
A8
A9
GND
A10
A11
A12
VCC
1B1
1B2
GND
1B3
NC
SEL
description
The SN74ALVC16269 is a 12-bit to 24-bit
registered bus transceiver, which is intended
for applications where two separate ports
must be multiplexed onto, or demultiplexed
from, a single port. The device is particularly
suitable as an interface between synchronous
DRAMs and high-speed microprocessors. The
SN74ALVC16269 is designed specifically for
low-voltage (3.3-V ) VCC operation; it is tested at
2.5-V, 2.7-V, and 3.3-V VCC.
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
OEB2
CLKENA2
2B4
GND
2B5
2B6
VCC
2B7
2B8
2B9
GND
2B10
2B11
2B12
1B12
1B11
1B10
GND
1B9
1B8
1B7
VCC
1B6
1B5
GND
1B4
CLKENA1
CLK
Data is stored in the internal B-port registers on
28
29
the low-to-high transition of the clock (CLK) input
when the appropriate clock-enable (CLKENA)
NC − No internal connection
inputs are low. Proper control of these inputs
allows two sequential 12-bit words to be
presented as a 24-bit word on the B port. For data
transfer in the B-to-A direction, a single storage register is provided. The select (SEL) line selects 1B or 2B data
for the A outputs. The register on the A output permits the fastest possible data transfer, thus extending the
period that the data is valid on the bus. The control terminals are registered so that all transactions are
synchronous with CLK. Data flow is controlled by the active-low output enables (OEA, OEB1, OEB2).
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVC16269 is available in TI’s shrink small-outline (DL) and thin shrink small-outline (DGG)
packages, which provide twice the I/O pin count and functionality of standard small-outline packages in the
same printed-circuit-board area.
The SN74ALVC16269 is characterized for operation from − 40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright  1995, Texas Instruments Incorporated
!"# $ %&'# "$ (&)*%"# +"#',
+&%#$ %! # $('%%"#$ (' #-' #'!$ '."$ $#&!'#$
$#"+"+ /""#0, +&%# (%'$$1 +'$ # '%'$$"*0 %*&+'
#'$#1 "** (""!'#'$,
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1
SCAS417B − OCTOBER 1993 − REVISED JULY 1995
Function Tables
OUTPUT ENABLE
OUTPUTS
INPUTS
CLK
OEA
OEB
A
1B, 2B
↑
H
H
Z
Z
↑
H
L
Z
Active
↑
L
H
Active
Z
↑
L
L
Active
Active
A-TO-B STORAGE (OEB = L)
INPUTS
OUTPUTS
CLKENA1
CLKENA2
CLK
A
1B
1B0†
2B
2B0†
H
H
X
X
L
X
↑
L
X
↑
L
L
X
H
H
X
X
L
↑
L
X
X
L
↑
H
L
H
X
† Output level before the indicated steady-state input
conditions were established
B-TO-A STORAGE (OEA = L)
INPUTS
1B
2B
OUTPUT
A
CLK
SEL
X
H
X
X
X
L
X
X
↑
H
L
X
A0†
A0†
L
↑
H
H
X
H
↑
L
X
L
L
↑
L
X
H
H
† Output level before the indicated steady-state
input conditions were established
2
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•
SCAS417B − OCTOBER 1993 − REVISED JULY 1995
logic diagram (positive logic)
CLK
OEB1
29
C1
2
1D
C1
OEB2
CLKENA1
CLKENA2
56
1D
30
55
C1
SEL
OEA
28
1D
1
1D
C1
G1
C1
A1
23
8
1
1D
1B1
1
CE
C1
1D
6
2B1
CE
C1
1D
1 of 12 Channels
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3
SCAS417B − OCTOBER 1993 − REVISED JULY 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
I/O ports (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 100 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 3): DGG package . . . . . . . . . . . . . . . . . . 1 W
DL package . . . . . . . . . . . . . . . . . . 1.4 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology
Data Book, literature number SCBD002B.
recommended operating conditions (see Note 4)
MIN
MAX
2.3
3.6
VCC
Supply voltage
VIH
High-level input voltage
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VIL
Low-level input voltage
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VI
VO
Input voltage
0
Output voltage
0
IOH
High-level output current
IOL
Low-level output current
∆t /∆v
Input transition rise or fall rate
4
•
•
V
2
0.7
0.8
VCC
VCC
−12
VCC = 3 V
VCC = 2.3 V
−24
VCC = 2.7 V
VCC = 3 V
12
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V
1.7
VCC = 2.3 V
VCC = 2.7 V
TA
Operating free-air temperature
NOTE 4: Unused control inputs must be held high or low to prevent them from floating.
UNIT
−12
V
V
V
mA
12
mA
24
0
10
ns / V
−40
85
°C
SCAS417B − OCTOBER 1993 − REVISED JULY 1995
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
IOH = − 100 µA
IOH = − 6 mA,
VOH
VOL
II
II(hold)
IOZ§
ICC
nICC
Ci
Cio
VCC†
TEST CONDITIONS
MIN to MAX
TA = − 40°C to 85°C
MIN TYP‡
MAX
VIH = 1.7 V
VIH = 1.7 V
2.3 V
VCC −0.2
2
2.3 V
1.7
IOH = − 12 mA
VIH = 2 V
VIH = 2 V
2.7 V
2.2
3V
2.4
IOH = − 24 mA,
IOL = 100 µA
VIH = 2 V
3V
2
MIN to MAX
0.2
IOL = 6 mA,
VIL = 0.7 V
VIL = 0.7 V
2.3 V
0.4
2.3 V
0.7
VIL = 0.8 V
VIL = 0.8 V
2.7 V
0.4
3V
0.55
IOL = 12 mA
IOL = 24 mA,
VI = VCC or GND
V
±5
3.6 V
VI = 0.7 V
VI = 1.7 V
2.3 V
VI = 0.8 V
VI = 2 V
3V
UNIT
V
µA
45
−45
µA
75
3.6 V
± 500
3.6 V
± 10
µA
3.6 V
40
µA
3 V to 3.6 V
750
µA
VI = 0 to 3.6 V
VO = VCC or GND
VI = VCC or GND,
One input at VCC − 0.6 V,
Other inputs at VCC or GND
−75
IO = 0
VI = VCC or GND
VO = VCC or GND
3.3 V
3.5
pF
3.3 V
9
pF
† For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions.
‡ All typical values are at VCC = 3.3 V.
§ For I/O ports, the parameter IOZ includes the input-leakage current.
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•
5
SCAS417B − OCTOBER 1993 − REVISED JULY 1995
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
VCC = 2.5 V
± 0.2 V
MIN
fclock
tw
tsu
th
MAX
Clock frequency
Hold
time
MIN
135
Pulse duration, CLK high or low
Setup
time
VCC = 2.7 V
MAX
VCC = 3.3 V
± 0.3 V
MIN
135
135
3.3
3.3
3.3
A data before CLK↑
High or low
2
2
1.7
B data before CLK↑
High or low
2.2
2.1
1.8
SEL before CLK↑
High or low
1.6
1.6
1.3
CLKENA1 or CLKENA2 before CLK↑
High or low
1
1.2
0.9
OE before CLK↑
High or low
1.5
1.6
1.3
A data after CLK↑
High or low
0.7
0.6
0.6
B data after CLK↑
High or low
0.7
0.6
0.6
SEL after CLK↑
High or low
1.1
0.7
0.7
CLKENA1 or CLKENA2 after CLK↑
High or low
1
0.8
1.1
OE after CLK↑
High or low
0.8
0.8
0.8
UNIT
MAX
MHz
ns
ns
ns
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figures 1 and 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
VCC = 2.5 V
± 0.2 V
MIN
MAX
135
tpd
CLK
ten
CLK
tdis
CLK
VCC = 2.7 V
MIN
MAX
135
VCC = 3.3 V
± 0.3 V
MIN
UNIT
MAX
135
ns
B
1
8.8
7.3
1
6.2
A
1
7
5.8
1
5
B
1
8.4
6.7
1
6.1
A
1
8.1
6.2
1
5.9
B
1.4
8.3
6.9
1
6.1
A
1.5
7.7
6.8
1
5.6
ns
ns
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
6
Power dissipation capacitance
TEST CONDITIONS
Outputs enabled
CL = 50 pF,
Outputs disabled
•
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•
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
TYP
TYP
55
59
46
49
UNIT
pF
SCAS417B − OCTOBER 1993 − REVISED JULY 1995
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V " 0.2 V
4.6 V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
4.6 V
GND
500 Ω
tw
LOAD CIRCUIT
2.3 V
Input
2.3 V
Timing
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
2.3 V
Data
Input
1.2 V
1.2 V
0V
tPHL
Output
Waveform 2
S1 at GND
(see Note B)
VOH
1.2 V
1.2 V
VOL
1.2 V
0V
tPLZ
2.3 V
Output
Waveform 1
S1 at 4.6 V
(see Note B)
1.2 V
tPLH
1.2 V
tPZL
2.3 V
1.2 V
2.3 V
Output
Control
(low-level
enabling)
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
1.2 V
0V
0V
tsu
Input
1.2 V
1.2 V
1.2 V
tPZH
VOL + 0.3 V
VOL
tPHZ
1.2 V
VOH − 0.3 V
VOH
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR v 10 MHz, ZO = 50 Ω, tr v 2.5 ns, tf v 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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7
SCAS417B − OCTOBER 1993 − REVISED JULY 1995
PARAMETER MEASUREMENT INFORMATION
VCC = 2.7 V AND 3.3 V " 0.3 V
6V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
500 Ω
tw
LOAD CIRCUIT
2.7 V
Input
2.7 V
Timing
Input
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
th
2.7 V
Data
Input
1.5 V
1.5 V
0V
tPHL
Output
Waveform 2
S1 at GND
(see Note B)
VOH
1.5 V
1.5 V
VOL
1.5 V
0V
tPLZ
3V
Output
Waveform 1
S1 at 6 V
(see Note B)
1.5 V
tPLH
1.5 V
tPZL
2.7 V
1.5 V
2.7 V
Output
Control
(low-level
enabling)
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
1.5 V
1.5 V
tsu
Input
1.5 V
1.5 V
tPZH
VOL + 0.3 V
VOL
tPHZ
VOH
1.5 V
VOH − 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR v 10 MHz, ZO = 50 Ω, tr v 2.5 ns, tf v 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
8
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