Revised August 2000 100390 Low Power Single Supply Hex PECL-to-TTL Translator General Description Features The 100390 is a hex translator for converting F100K logic levels to TTL logic levels. Unlike other level translators, the 100390 operates using only one +5V supply. Differential inputs allow each circuit to be used as an inverting, noninverting, or differential receiver. An internal reference generator provides VBB for single-ended operation. The standard FAST 3-STATE outputs are enabled by a common active low TTL compatible OE input. Partitioned VCCs on chip are brought out on separate power pins, allowing the noisy TTL VCC power plane to be isolated from the relatively quiet ECL VCC. The 100390 is ideal for applications limited to a single +5V supply, allowing for easy ECL to TTL Interfacing. ■ Operates from a single +5V supply ■ 3-STATE outputs ■ 2000V ESD protection ■ VBB supplied for single-ended operation Ordering Code: Order Number Package Number Package Description 100390SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 100390PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 100390QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 100390QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Industrial Temperature Range (−40°C to +85°C) Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams 24-Pin DIP/SOIC 28-Pin PLCC FAST is a registered trademark of Fairchild Semiconductor. © 2000 Fairchild Semiconductor Corporation DS010897 www.fairchildsemi.com 100390 Low Power Single Supply Hex PECL-to-TTL Translator September 1990 100390 Logic Symbol Pin Descriptions Pin Names Description D0–D5 Data Inputs (PECL) D0–D5 Inverting Data Inputs (PECL) Q0–Q5 Data Outputs (TTL) OE Output Enable (TTL) VBB Reference Voltage (PECL) Truth Table Data Control TTL Inputs Input Outputs (PECL) (TTL) Comments Dn Dn OE Qn X X H Z Outputs Disable L H L L Differential Operation H L L H Differential Operation L L L U Invalid Input States H H L U Invalid Input States OPEN OPEN L U Invalid Input States L VBB L L Single Ended Operation H VBB L H Single Ended Operation VBB L L H Single Ended Operation VBB H L L Single Ended Operation VBB OPEN L H Single Ended Operation OPEN VBB L L Single Ended Operation H = HIGH Voltage Level L = LOW Voltage Level Z = HIGH Impedance U = Undefined Logic Diagram www.fairchildsemi.com Detail 2 Recommended Operating Conditions −65°C to +150°C Storage Temperature Maximum Junction Temperature +150°C VCC Pin Potential to Ground Pin −0.5V to +7.0V TTL Input Voltage (Note 2) −0.5V to +7.0V TTL Input Current (Note 2) −30 mA to +5.0 mA VBB Output Current −5.0 mA to +1.0 mA ECL Input Potential GND to ECL VCC + 0.5V 0°C to +85°C Case Temperature +4.75V to +5.25V Supply Voltage VCC Differential −1.0V to +1.0V ECL VCC to TTL VCC Voltage Applied to Output in High State (with VCC = 0V) −0.5V to +5.5V 3-STATE Output Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Current Applied to Output in Low State (Max) Twice the Rated IOL (mA) ESD Last Passing Voltage (Min) 2000V Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics ECL VCC = +5.0V ±5%, TTL VCC = +5.0V ±5%, GND = 0V Symbol Parameter VIH Input HIGH Voltage Data OE VIL Input LOW Voltage Data Min Max ECL VCC − 1.165 ECL VCC − 0.870 2.0 Units V V ECL VCC − 1.830 ECL VCC − 1.475 OE 0.8 VBB Output Reference Voltage ECL VCC − 1.38 VOH Output HIGH Voltage (TTL) 2.7 VOL Output LOW Voltage (TTL) IIH Input HIGH Current ECL VCC − 1.26 V V Conditions Guaranteed HIGH Signal for ALL Inputs (with One Input Tied to VBB) Guaranteed HIGH Signal (TTL) Guaranteed LOW Signal for ALL Inputs (with One Input Tied to VBB) Guaranteed LOW Signal (TTL) V IBB = 0.0 mA or −1.0 mA V IOH = −3 mA 0.5 V IOL = 24 mA Data 50 µA OE 20 µA VIN = 2.7V (TTL) VIN = VIH(Max), D0–D5 = VBB, D0–D5 = VIL(Min) IIL Input LOW Current OE −200 µA VIN = 0.5V (TTL) IBVI Input Breakdown Current OE 10 µA VIN = 7.0V (TTL) ICBO Input Leakage Current µA VIN = GND, D0–D5 = VBB IOZH 3-STATE Current Output HIGH 50 µA VOUT = +2.7V IOZL 3-STATE Current Output LOW −50 µA VOUT = +0.5V ICC ECL Supply Current 13 30 mA ICCZ TTL Supply Current 10 20 mA 3-STATE ICCL TTL Supply Current 8 17 mA Low State ICCH TTL Supply Current HIGH 0.4 2.0 mA HIGH State IOS Output Short-Circuit Current −150 −60 mA VOUT = 0.0V, VCC = +5.25 VDiff Differential Input Voltage mV Required for Full Output Swing VCM Common Mode Voltage VCD Clamp Diode Voltage −10 D0–D5 = VIL(Min) 150 ECL VCC − 2.0 3 ECL VCC − 0.5 V −1.2 V IIN = −18 mA www.fairchildsemi.com 100390 Absolute Maximum Ratings(Note 1) 100390 DIP AC Electrical Characteristics VCC = 5.0V ± 5%; TC = 0°C to +85°C Symbol TC = 0°C Parameter Min fMAX Maximum Clock Frequency tPLH Propagation Delay tPHL Data to Output tPZH Output Enable Time tPZL tPHZ Output Disable Time tPLZ TC = +25°C Max Min 100 Max 100 TC = +85°C Min Units Max 100 Figure Number MHz 3.5 7.2 3.5 6.8 3.5 6.7 2.7 4.8 2.7 4.8 3.0 5.1 2.4 4.0 2.4 4.0 2.6 4.2 2.9 5.8 2.9 5.4 2.7 5.1 2.3 3.9 2.2 3.9 2.2 3.9 ns Figure 1 ns Figure 2 ns Figure 2 SOIC and PLCC Package AC Electrical Characteristics VCC = 5.0V ± 5%; TC = 0°C to +85°C Symbol Parameter fMAX Maximum Clock Frequency tPLH Propagation Delay tPHL Data to Output tPZH Output Enable Time tPZL tPHZ Output Disable Time tPLZ www.fairchildsemi.com TC = 0°C Min TC = +25°C Max Min 100 Max 100 TC = +85°C Min Max 100 Figure Number MHz 3.5 7.0 3.5 6.6 3.5 6.5 2.7 4.6 2.7 4.6 3.0 4.9 2.4 3.8 2.4 3.8 2.6 4.0 2.9 5.6 2.9 5.2 2.7 4.9 2.3 3.7 2.2 3.7 2.2 3.7 4 Units ns Figure 1 ns Figure 2 ns Figure 2 100390 Switching Waveforms FIGURE 1. Data to Output Propagation Delay FIGURE 2. Enable/Disable Propagation Delay Test Circuit Notes: GND = 0V, ECL VCC = +5V, TTL VCC = +5V L1 and L2 = equal length 50Ω impedance lines 50Ω terminators are internal to S/H measurement unit Decoupling 0.1 µF from GND to ECL VCC and TTL V CC All unused outputs are loaded with 500Ω to GND CL = Fixture and stray capacitance = 50 pF Switch S1 is open for tPLH, tPHL, tPHZ and tPZH tests Switch S1 is closed only for tPLZ and tPZL tests FIGURE 3. AC Test Circuit 5 www.fairchildsemi.com 100390 Application Notes 1. Device performance will be enhanced by the use of dual VCC power planes as illustrated in the Application Figures 4, 5. This will minimize the coupling of TTL switching noise into the primary reference to the ECL circuitry and take full advantage of the 100390’s on chip VCC partitioning. 4. Undefined output states can occur for some invalid combinations. See Truth Table. This should be avoided to prevent possible oscillation or increased power consumption due to TTL outputs biased into a quasi state with both pullup and pulldown stages partially on. 3-STATEing the outputs will counteract the effects of invalid input states. 2. The device’s partitioned VCC may be operated from two 5V, 5% tolerance, supplies provided that they are ramped up/down together so that the max differential is 1V. This is to prevent overstress to internal ESD diodes. If the ECL driver to the F390 is powered from a separate supply, it must obey this sequence rule also. 5. Pins 8, 15, and 22 on the 28-pin PLCC package are tied to the chip’s substrate and are named GNDs. These pins are electrically common to the ground pins 1, 2, and 28. For best thermal performance, tie the GND pins to the circuit ground plane. They may be tied to an electrically isolated thermal dissipation plane or may float. 3. Glitch-free power up, independent of Data input levels, is achieved if TTL logic HIGH is held on the Output Enable pin during ramping up/down of the VCC supply. 6. Figure 4 illustrates typical differential input operation. 7. Figure 5 illustrates typical single-ended input operation. FIGURE 4. FIGURE 5. www.fairchildsemi.com 6 100390 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide Package Number N24E 7 www.fairchildsemi.com 100390 Low Power Single Supply Hex PECL-to-TTL Translator Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Package Number V28A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 8