Revised August 2000 100397 Quad Differential ECL/TTL Translating Transceiver with Latch General Description Features The 100397 is a quad latched transceiver designed to convert TTL logic levels to differential F100K ECL logic levels and vice versa. This device was designed with the capability of driving a differential 25Ω ECL load with cutoff capability, and will sink a 64 mA TTL load. The 100397 is ideal for mixed technology applications utilizing either an ECL or TTL backplane. ■ Differential ECL input/output structure The direction of translation is set by the direction control pin (DIR). The DIR pin on the 100397 accepts F100K ECL logic levels. An ECL LOW on DIR sets up the ECL pins as inputs and TTL pins as outputs. An ECL HIGH on DIR sets up the TTL pins as inputs and ECL pins as outputs. ■ 3-STATE outputs ■ 64 mA FAST TTL outputs ■ 25Ω differential ECL outputs with cut-off ■ Bi-directional translation ■ 2000V ESD protection ■ Latched outputs ■ Voltage compensated operating range = −4.2V to −5.7V A LOW on the output enable input pin (OE) holds the ECL output in a cut-off state and the TTL outputs at a high impedance level. A HIGH on the latch enable input (LE) latches the data at both inputs even though only one output is enabled at the time. A LOW on LE makes the latch transparent. The cut-off state is designed to be more negative than a normal ECL LOW level. This allows the output emitterfollowers to turn off when the termination supply is −2.0V, presenting a high impedance to the data bus. This high impedance reduces termination power and prevents loss of low state noise margin when several loads share the bus. The 100397 is designed with FAST TTL output buffers, featuring optimal DC drive and capable of quickly charging and discharging highly capacitive loads. All inputs have 50 KΩ pull-down resistors. Ordering Code: Order Number 100397PC Package Number N24E Package Description 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 100397QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 100397QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Industrial Temperature Range (−40°C to +85°C) Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. FAST is a registered trademark of Fairchild Semiconductor Corporation. © 2000 Fairchild Semiconductor Corporation DS010971 www.fairchildsemi.com 100397 Quad Differential ECL/TTL Translating Transceiver with Latch January 1992 100397 Logic Symbol Pin Descriptions Pin Names Connection Diagrams 24-Pin DIP Description E0–E3 ECL Data I/O E0–E3 Complementary ECL Data I/O T0–T3 TTL Data I/O OE Output Enable Input (ECL Levels) LE Latch Enable Input (ECL Levels) DIR Direction Control Input (ECL levels) GNDECL ECL Ground GNDECLO ECL Output Ground GNDS ECL Ground-to-Substrate VEE ECL Quiescent Power Supply VEED ECL Dynamic Power Supply GNDTTL TTL Quiescent Ground GNDTTLD TTL Dynamic Ground VTTL TTL Quiescent Power Supply VTTLD TTL Dynamic Power Supply All pins function at 100K ECL levels except for T0–T3. Truth Table 28-Pin PLCC LE DIR OE 0 0 0 ECL TTL Port Port LOW Z Notes (Cut-Off) 0 0 1 Input 0 1 0 LOW Output (Note 1)(Note 4) Z (Cut-Off) 0 1 1 Output Input 1 0 0 Input Z (Note 2)(Note 4) (Note 1)(Note 3) 1 0 1 Latched X (Note 1)(Note 3) 1 1 0 LOW Input (Note 2)(Note 3) X (Note 2)(Note 3) (Cut-Off) 1 1 1 Latched H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High Impedance Note 1: ECL input to TTL output mode. Note 2: TTL input to ECL output mode. Note 3: Retains data present before LE set HIGH. Note 4: Latch is transparent. www.fairchildsemi.com 2 100397 Functional Diagram Note: LE, DIR, and OE use ECL logic levels Detail 3 www.fairchildsemi.com 100397 Absolute Maximum Ratings(Note 5) Storage Temperature (TSTG) Recommended Operating Conditions −65°C to +150°C Maximum Junction Temperature Case Temperature (TC) +150°C (TJ) VEE Pin Potential to Ground Pin −7.0V to +0.5V VTTL Pin Potential to Ground Pin −0.5V to +6.0V ECL Input Voltage (DC) 0°C to +85°C Commercial −40°C to +85°C Industrial VEE to +0.5V ECL Supply Voltage (VEE) −5.7V to −4.2V TTL Supply Voltage (VTTL) +4.5V to +5.5V ECL Output Current −50 mA (DC Output HIGH) TTL Input Voltage (Note 7) −0.5V to +7.0V TTL Input Current (Note 7) −30 mA to +5.0 mA Voltage Applied to Output Note 5: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation. in HIGH State −0.5V to +5.5V 3-STATE Output Current Applied to TTL Output in LOW State (Max) twice the Rated IOL (mA) Note 6: ESD testing conforms to MIL-STD-883, Method 3015. ≥2000V ESD (Note 6) Note 7: Either voltage limit or current limit is sufficient to protect inputs. Commercial Version TTL-to-ECL DC Electrical Characteristics (Note 8) VEE = −4.2V to −5.7V, GND = 0V, TC = 0°C to +85°C, VTTL = +4.5V to +5.5V Min Typ Max Units VOH Symbol Output HIGH Voltage Parameter −1025 −955 −870 mV VIN = VIH(Max) or VIL(Min) VOL Output LOW Voltage −1830 −1705 −1620 mV Loading with 50Ω to − 2V −2000 −1950 mV Cutoff Voltage Conditions OE and LE Low, DIR High VIN = VIH(Max) or VIL(Min), Loading with 50Ω to −2V VOHC Output HIGH Voltage Corner Point High VOLC −1035 mV Output LOW Voltage Corner Point Low −1610 mV VIN = VIH(Min) or VIL(Max) Loading with 50Ω to −2V VIH Input HIGH Voltage 2.0 5.0 V VIL Input LOW Voltage 0 0.8 V Over VTTL, VEE, TC Range IIH Input HIGH Current 5.0 µA VIN = +2.7V IBVIT Input HIGH Current 0.5 mA VIN = 5.5V −1.0 mA VIN = +0.5V −1.2 V IIN = −18 mA Breakdown (I/O) IIL Input LOW Current VFCD Input Clamp Diode Voltage Over VTTL, VEE, TC Range IEE VEE Supply Current −99 −50 LE Low, OE and DIR HIGH IEEZ VEE Supply Current −159 −90 LE and OE Low, Dir HIGH Inputs Open Inputs Open Note 8: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. www.fairchildsemi.com 4 100397 Commercial Version (Continued) ECL-to-TTL DC Electrical Characteristics (Note 9) VEE = −4.2V to −5.7V, GND = 0V, TC = 0°C to +85°C, CL = 50 pF, VTTL = +4.5V to +5.5V Symbol Parameter VOH Output HIGH Voltage VOL Output LOW Voltage Min Typ 2.7 3.1 2.4 Max Units V 2.9 0.3 0.5 Conditions IOH = −3 mA, VTTL = 4.75V V IOH = −3 mA, VTTL = 4.50V V IOL = 24 mA, VTTL = 4.50V VIH Input HIGH Voltage −1165 −870 mV Guaranteed HIGH Signal for All Inputs VIL Input LOW Voltage −1830 −1475 mV Guaranteed LOW Signal for All Inputs VDIFF Input Voltage Differential 150 mV Required for Full Output Swing VCM Common Mode Voltage GNDECL − 2.0 IIH Input HIGH Current ICEX GNDECL − 0.5 V E0–E3, E0–E3 240 µA VIN = VIH(Max) OE, LE, DIR 35 50 µA VOUT = VTTL 500 µA Output HIGH Leakage Current IZZ Bus Drainage Test VOUT = 5.25V VTTL = 0.0V IIL Input LOW Current IOZHT 3-STATE Current IOZLT 3-STATE Current IOS Output Short-Circuit 0.50 70 Output High Output Low Current ITTL −650 −100 VTTL Supply Current µA VIN = VIL(Min) µA VOUT = +2.7V µA VOUT = +0.5V −225 mA VOUT = 0.0V, VTTL = +5.5V 39 mA TTL Outputs LOW 27 mA TTL Outputs HIGH 39 mA TTL Outputs in 3-STATE Note 9: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. DIP and PCC TTL-to-ECL AC Electrical Characteristics VEE = −4.2V to −5.7V, VTTL = +4.5V to +5.5V Symbol Parameter fMAX Maximum Clock Frequency tPLH Tn to En, En tPHL (Transparent) tPLH LE to En, En TC = 0°C Min Max 180 TC = 25°C Min Max 180 TC = 85°C Min Max 180 Units Conditions MHz 0.9 2.1 0.8 2.2 0.7 2.5 ns Figures 1, 3 1.2 2.3 1.3 2.4 1.4 2.5 ns Figures 1, 3 2.5 4.5 2.5 4.5 2.5 4.6 ns Figures 1, 3 2.1 3.8 2.3 4.0 2.5 4.5 ns Figures 1, 3 2.0 3.5 2.1 3.7 2.3 4.2 ns Figures 1, 3 tPHL tPZH OE to En, En (Cutoff to HIGH) tPHZ OE to En, En (HIGH to Cutoff) tPHZ DIR to En, En (HIGH to Cutoff) tS Tn to LE 0.8 0.8 0.8 ns Figures 1, 3 tH Tn to LE 0.6 0.6 0.6 ns Figures 1, 3 tTLH Transition Time tTHL 20% to 80%, 80% to 20% ns Figures 1, 3 0.8 2.8 0.8 5 2.8 0.8 2.8 www.fairchildsemi.com 100397 Commercial Version (Continued) DIP and PCC ECL-to-TTL AC Electrical Characteristics VEE = −4.2V to −5.7V, VTTL = +4.5V to +5.5V, CL = 50 pF TC = 0°C Symbol Parameter Min Max fMAX Maximum Clock Frequency tPLH En, En to Tn tPHL (Transparent) tPLH LE to Tn tPHL TC = 25°C Min 75 Max 75 TC = 85°C Min Units Conditions Max 75 MHz 1.7 4.9 1.7 5.1 1.8 5.8 2.2 4.0 2.2 4.0 2.3 4.1 3.3 5.2 3.4 5.4 3.8 6.1 tPZH OE to Tn 3.2 5.6 3.3 5.7 3.6 6.3 tPZL (Enable Time) 4.9 8.3 5.1 8.5 5.6 9.2 tPHZ OE to Tn 3.6 8.6 3.5 8.3 3.5 7.5 tPLZ (Disable Time) 3.4 6.9 3.5 6.7 3.6 6.7 ns Figures 2, 4 ns Figures 2, 4 ns Figures 2, 5 ns Figures 2, 5 ns Figures 2, 6 Figures 2, 4 tPHZ DIR to Tn 3.5 8.1 3.5 8.1 3.5 7.6 tPLZ (Disable Time) 3.4 6.8 3.4 6.7 3.6 6.7 tS En, En to LE 0.6 0.6 0.6 ns tH En, En to LE 0.7 0.7 0.7 ns Figures 2, 4 tPW(L) Pulse Width LE 2.0 2.0 2.0 ns Figures 2, 4 Industrial Version TTL-to-ECL DC Electrical Characteristics (Note 10) VEE = −4.2V to −5.7V, GND = 0V, TC = −40°C to +85°C, VTTL = +4.5V to +5.5V Min Typ Max Units VOH Symbol Output HIGH Voltage Parameter −1085 −955 −870 mV VIN = VIH(Max) or VIL(Min) VOL Output LOW Voltage −1830 −1705 −1575 mV Loading with 50Ω to −2V −2000 −1900 mV Cutoff Voltage Conditions OE and LE LOW, DIR HIGH VIN= VIH(Max) or VIL(Min), Loading with 50Ω to −2V VOHC Output HIGH Voltage Corner Point HIGH VOLC −1095 mV Output LOW Voltage Corner Point LOW −1565 mV VIN = VIH(Min) or VIL(Max) Loading with 50Ω to −2V VIH Input HIGH Voltage 2.0 5.0 V VIL Input LOW Voltage 0 0.8 V Over VTTL, VEE, TC Range IIH Input HIGH Current 5.0 µA VIN = +2.7V IBVIT Input HIGH Current 0.5 mA VIN = 5.5V −1.0 mA VIN = +0.5V −1.2 V IIN = −18 mA Breakdown (I/O) IIL Input LOW Current VFCD Input Clamp Diode Voltage Over VTTL, VEE, TC Range IEE VEE Supply Current −99 −40 LE Low, OE and DIR HIGH IEEZ VEE Supply Current −159 −90 LE and OE LOW, Dir HIGH Inputs Open Inputs Open Note 10: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. www.fairchildsemi.com 6 100397 Industrial Version (Continued) ECL-to-TTL DC Electrical Characteristics (Note 11) VEE = −4.2V to −5.7V, GND = 0V, TC = −40°C to +85°C, CL = 50 pF, VTTL = +4.5V to +5.5V Symbol Parameter VOH Output HIGH Voltage VOL Output LOW Voltage Min Typ 2.7 3.1 2.4 Max Units V 2.9 0.3 0.5 Conditions IOH = −3 mA, VTTL = 4.75V V IOH = −3 mA, VTTL = 4.50V V IOL = 24 mA, VTTL = 4.50V VIH Input HIGH Voltage −1170 −870 mV Guaranteed HIGH Signal for All Inputs VIL Input LOW Voltage −1830 −1480 mV Guaranteed LOW Signal for All Inputs VDIFF Input Voltage Differential 150 mV Required for Full Output Swing VCM Common Mode Voltage GNDECL − 2.0 IIH Input HIGH Current ICEX GNDECL − 0.5 V E0–E3, E0–E3 300 µA OE, LE, DIR 35 VIN = VIH(Max) Output HIGH Leakage Current IZZ Bus Drainage Test 50 µA 500 µA VOUT = VTTL VOUT = 5.25V VTTL = 0.0V IIL Input LOW Current IOZHT 3-STATE Current IOZLT 3-STATE Current IOS Output Short-Circuit Current ITTL VTTL Supply Current µA 0.50 70 Output HIGH Output LOW −650 µA µA −100 VIN = VIL(Min) VOUT = +2.7V VOUT = +0.5V −225 mA VOUT = 0.0V, VTTL = +5.5V 39 mA TTL Outputs LOW 27 mA TTL Outputs HIGH 39 mA TTL Outputs in 3-STATE Note 11: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. PCC TTL-to-ECL AC Electrical Characteristics VEE = −4.2V to −5.7V, VTTL = +4.5V to +5.5V Symbol Parameter fMAX Maximum Clock Frequency tPLH Tn to En, En tPHL (Transparent) tPLH LE to En, En TC = −40°C Min Max 180 TC = +25°C Min Max 180 TC = +85°C Min Max 180 Units Conditions MHz 0.9 2.4 0.8 2.2 0.7 2.5 ns Figures 1, 3 1.2 2.3 1.3 2.4 1.4 2.5 ns Figures 1, 3 1.9 3.8 2.5 4.5 2.5 4.6 ns Figures 1, 3 2.5 4.7 2.3 4.0 2.5 4.5 ns Figures 1, 3 1.8 3.5 2.1 3.7 2.3 4.2 ns Figures 1, 3 tPHL tPZH OE to En, En (Cutoff to HIGH) tPHZ OE to En, En (HIGH to Cutoff) tPHZ DIR to En, En (HIGH to Cutoff) tS Tn to LE 0.8 0.8 0.8 ns Figures 1, 3 tH Tn to LE 0.6 0.6 0.6 ns Figures 1, 3 tTLH Transition Time tTHL 20% to 80%, 80% to 20% ns Figures 1, 3 0.8 2.8 0.8 7 2.8 0.8 2.8 www.fairchildsemi.com 100397 Industrial Version (Continued) PCC ECL-to-TTL AC Electrical Characteristics VEE = −4.2V to −5.7V, VTTL = +4.5V to +5.5V, CL = 50 pF TC = −40°C Symbol Parameter Min Max fMAX Maximum Clock Frequency tPLH En, En to Tn tPHL (Transparent) tPLH LE to Tn tPHL TC = +25°C Min 75 Max 75 TC = +85°C Min Units Conditions Max 75 MHz 1.7 4.9 1.7 5.1 1.8 5.8 2.2 4.3 2.2 4.0 2.3 4.1 3.3 5.2 3.4 5.4 3.8 6.1 tPZH OE to Tn 3.1 5.6 3.3 5.7 3.6 6.3 tPZL (Enable Time) 4.8 8.3 5.1 8.5 5.6 9.2 tPHZ OE to Tn 3.5 9.2 3.5 8.3 3.5 7.5 tPLZ (Disable Time) 3.2 7.3 3.5 6.7 3.6 6.7 ns Figures 2, 4 ns Figures 2, 4 ns Figures 2, 5 ns Figures 2, 5 ns Figures 2, 6 Figures 2, 4 tPHZ DIR to Tn 3.5 8.8 3.5 8.1 3.5 7.6 tPLZ (Disable Time) 3.2 7.2 3.4 6.7 3.6 6.7 tS En, En to LE 0.6 0.6 0.6 ns tH En, En to LE 0.7 0.7 0.7 ns Figures 2, 4 tPW(L) Pulse Width LE 2.0 2.0 2.0 ns Figures 2, 4 www.fairchildsemi.com 8 100397 Test Circuitry (TTL-to-ECL) Notes: Rt = 50Ω termination. When an input or output is being monitored by a scope, Rt is supplied by the scope’s 50Ω resistance. When an input or output is not being monitored, and external 50Ω resistance must be applied to serve as Rt. TTL and ECL force signals are brought to the DUT via 50Ω coax lines. VTTL is decoupled to ground with 0.1 µF to ground, VEE is decoupled to ground with 0.01 µF and GND is connected to ground. For ECL input pins, the equivalent force/sense circuitry is optional. FIGURE 1. TTL-to-ECL AC Test Circuit Switching Waveforms (TTL-to-ECL) FIGURE 2. TTL to ECL Transition—Propagation Delay and Transition Times 9 www.fairchildsemi.com 100397 Test Circuitry (ECL-to-TTL) Notes: Rt = 50Ω termination. When an input or output is being monitored by a scope, Rt is supplied by the scope’s 50Ω resistance. When an input or output is not being monitored, and external 50Ω resistance must be applied to serve as Rt. The TTL 3-STATE pull up switch is connected to +7V only for ZL and LZ tests. TTL and ECL force signals are brought to the DUT via 50Ω coax lines. VTTL is decoupled to ground with 0.1 µF to ground, V EE is decoupled to ground with 0.01 µF and GND is connected to ground. FIGURE 3. ECL-to-TTL AC Test Circuit Note: DIR is LOW, and OE is HIGH FIGURE 4. ECL-to-TTL Transition—Propagation Delay and Transition Times www.fairchildsemi.com 10 100397 Test Circuitry (ECL-to-TTL) (Continued) Note: Note: DIR is LOW, LE is HIGH OE is HIGH, LE is HIGH FIGURE 6. ECL-to-TTL Transition, DIR to TTL Output, Disable Time FIGURE 5. ECL-to-TTL Transition, OE to TTL Output, Enable and Disable Times Applications FIGURE 7. Applications Diagram—MOS/TTL SRAM Interface Using 100397 ECL–TTL Latched Translator 11 www.fairchildsemi.com 100397 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide Package Number N24E www.fairchildsemi.com 12 100397 Quad Differential ECL/TTL Translating Transceiver with Latch Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Package Number V28A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 13 www.fairchildsemi.com