PHILIPS TEA6321T

INTEGRATED CIRCUITS
DATA SHEET
TEA6321
Sound fader control circuit
Preliminary specification
Supersedes data of August 1993
File under Integrated Circuits, IC01
1995 Dec 19
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6321
FEATURES
• Source selector for four stereo and one mono inputs
• Interface for noise reduction circuits
• Interface for external equalizer
• Volume, balance and fader control
• Special loudness characteristic automatically controlled
in combination with volume setting
GENERAL DESCRIPTION
The sound fader control circuit TEA6321 is an I2C-bus
controlled stereo preamplifier for car radio hi-fi sound
applications.
• Bass control with equalizer filters
• Treble control
• Mute control at audio signal zero crossing
• Fast mute control via I2C-bus
• Fast mute control via pin
• I2C-bus control for all functions
• Power supply with internal power-on reset.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VCC
supply voltage
ICC
supply current
VCC = 8.5 V
Vo(rms)
maximum output voltage level
VCC = 8.5 V; THD ≤ 0.1%
−
2000
−
mV
Gv
voltage gain
−86
−
+20
dB
Gstep(vol)
step resolution (volume)
−
1
−
dB
Gbass
bass control
−18
−
+18
dB
Gtreble
treble control
−12
−
+12
dB
Gstep(treble)
step resolution (treble)
−
1.5
−
dB
(S+N)/N
signal-plus-noise to noise ratio
Vo = 2.0 V; Gv = 0 dB;
unweighted
−
105
−
dB
RR100
ripple rejection
Vr(rms) < 200 mV; f = 100 Hz;
Gv = 0 dB
−
75
−
dB
αcs
channel separation
250 Hz ≤ f ≤ 10 kHz; Gv = 0 dB
90
96
−
dB
7.5
8.5
9.5
V
−
26
−
mA
ORDERING INFORMATION
TYPE
NUMBER
TEA6321T
1995 Dec 19
PACKAGE
NAME
SO32
DESCRIPTION
plastic small outline package; 32 leads; body width 7.5 mm
2
VERSION
SOT287-1
Vref
VCC
10
8
150 nF 270 nF
270 nF
7
9
Cm
5.6 nF
MUTE
5
6
12
21
31
MUTE
FUNCTION
ZERO CROSS
DETECTOR
POWER
SUPPLY
2
GND
10 nF
VOLUME I
+20 to −31 dB
LOUDNESS
LEFT
47 µF
19
BASS
LEFT
TREBLE
LEFT
±18 dB
±12 dB
VOLUME II
0 to −55 dB
BALANCE
FADER REAR
3
output
left
VOLUME II
0 to −55 dB
BALANCE
FADER FRONT
9 x 220 nF
Philips Semiconductors
100 µF
3.4 k Ω
Sound fader control circuit
20 kΩ
CKVL 220 nF
2.2 kΩ
BLOCK DIAGRAM
1995 Dec 19
8.2 nF
4
16
32
15
I2C-BUS
RECEIVER
LOGIC
13
1
SCL
SDA
11
SOURCE
input
mono
source
14
SELECTOR
VOLUME I
+20 to −31 dB
LOUDNESS
RIGHT
22
BASS
RIGHT
TREBLE
RIGHT
±18 dB
±12 dB
VOLUME II
0 to −55 dB
BALANCE
FADER FRONT
input
right
source
18
TEA6321
17
CKIN
23
25
24
26
27
29
output
right
20
VOLUME II
0 to −55 dB
BALANCE
FADER REAR
30
28
270 nF
2.2 kΩ
3.4 k Ω
8.2 nF 20 kΩ
Fig.1 Block diagram.
5.6 nF
TEA6321
150 nF 270 nF
Preliminary specification
MED838
CKVL 220 nF
handbook, full pagewidth
3
input
left
source
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6321
PINNING
SYMBOL
PIN
DESCRIPTION
SDA
1
serial data input/output
GND
2
ground
OUTLR
3
output left rear
OUTLF
4
output left front
TL
5
treble control capacitor left channel
or input from an external equalizer
handbook, halfpage
SDA
1
32 SCL
GND
2
31 VCC
OUTLR
3
30 OUTRR
OUTLF
4
29 OUTRF
TL
5
28 TR
B2L
6
bass control left channel or output to
an external equalizer
B1L
7
bass control, left channel
IVL
8
input volume I, left control part
ILL
9
input loudness, left control part
QSL
10
output source selector, left channel
B2L
6
27 B2R
IDL
11
input D left source
B1L
7
26 B1R
MUTE
12
mute control
IVL
8
ICL
13
input C left source
IMO
14
input mono source
IBL
15
input B left source
IAL
16
input A left source
IAR
17
input A right source
IBR
18
CAP
19
25 IVR
TEA6321
ILL
9
24 ILR
QSL 10
23 QSR
IDL 11
22 IDR
MUTE 12
21 Vref
input B right source
ICL 13
20 ICR
electronic filtering for supply
IMO 14
19 CAP
ICR
20
input C right source
IBL 15
18 IBR
Vref
21
reference voltage (0.5VCC)
IAL 16
17 IAR
IDR
22
input D right source
QSR
23
output source selector right channel
ILR
24
input loudness right channel
IVR
25
input volume I, right control part
B1R
26
bass control right channel
B2R
27
bass control right channel or output
to an external equalizer
TR
28
treble control capacitor right channel
or input from an external equalizer
OUTRF
29
output right front
OUTRR
30
output right rear
VCC
31
supply voltage
SCL
32
serial clock input
1995 Dec 19
MED839
Fig.2 Pin configuration.
4
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6321
disconnected. The connections B2L and B2R are outputs
and TL and TR are inputs for inserting an external
equalizer.
FUNCTIONAL DESCRIPTION
The source selector selects one of 4 stereo inputs or the
mono input. The maximum input signal voltage is
Vi(rms) = 2 V. The outputs of the source selector and the
inputs of the following volume control parts are available at
pins 8 and 10 for the left channel and pins 23 and 25 for
the right channel. This offers the possibility of interfacing a
noise reduction system.
The last section of the circuit is the volume II block. The
balance and fader functions are performed using the same
control blocks. This is realized by 4 independently
controllable attenuators, one for each output. The control
range of these attenuators is 55 dB in steps of 1 dB with an
additional mute step.
The volume control function is split into two sections:
volume I control block and volume II control block.
The circuit provides 3 mute modes:
1. Zero crossing mode mute via I2C-bus using
2 independent zero crossing detectors (ZCM,
see Tables 2 and 9 and Fig.16).
The control range of volume I is between +20 dB and
−31 dB in steps of 1 dB. The volume II control range is
between 0 dB and −55 dB in steps of 1 dB. Although the
theoretical possible control range is 106 dB
(+20 to −86 dB), in practice a range of 86 dB
(+20 to −66 dB) is recommended. The gain/attenuation
setting of the volume I control block is common for both
channels.
2. Fast mute via MUTE pin (see Fig.10).
3. Fast mute via I2C-bus either by general mute (GMU,
see Tables 2 and 9) or volume II block setting
(see Table 4).
The mute function is performed immediately if ZCM is
cleared (ZCM = 0). If the bit is set (ZCM = 1) the mute is
activated after changing the GMU bit. The actual mute
switching is delayed until the next zero crossing of the
audio frequency signal. As the two audio channels (left and
right) are independent, two comparators are built-in to
control independent mute switches.
The volume I control block operates in combination with
the loudness control. The filter is linear when the maximum
gain for the volume I control (+20 dB) is selected. The filter
characteristic increases automatically over a range of
32 dB down to a setting of −12 dB. That means the
maximum filter characteristic is obtained at −12 dB setting
of volume I. Further reduction of the volume does not
further influence the filter characteristic (see Fig.5). The
maximum selected filter characteristic is determined by
external components. The proposed application gives a
maximum boost of 17 dB for bass and 4.5 dB for treble.
The loudness may be switched on or off via I2C-bus control
(see Table 7).
To avoid a large delay of mute switching when very low
frequencies are processed, the maximum delay time is
limited to typically 100 ms by an integrated timing circuit
and an external capacitor (Cm = 10 nF, see Fig.10). This
timing circuit is triggered by reception of a new data word
for the switch function which includes the GMU bit. After a
discharge and charge period of an external capacitor the
muting switch follows the GMU bit if no zero crossing was
detected during that time.
The volume I control block is followed by the bass control
block. An external filter for each channel in combination
with internal resistors, provides the frequency response of
the bass control (see Fig.3). The adjustable range is
between −18 and +18 dB in steps of 1.8 dB at 46 Hz.
The mute function can also be controlled externally. If the
mute pin is switched to ground all outputs are muted
immediately (hardware mute). This mute request
overwrites all mute controls via the I2C-bus for the time the
pin is held LOW. The hardware mute position is not stored
in the TEA6321.
Both loudness and bass control result in a maximum bass
boost of 35 dB for low volume settings.
The treble control block offers a control range between
−12 and +12 dB in steps of 1.5 dB at 15 kHz. The filter
characteristic is determined by a single capacitor of 5.6 nF
for each channel in combination with internal resistors
(see Fig.4).
For the turn on/off behaviour the following explanation is
generally valid. To avoid AF output caused by the input
signal coming from preceding stages, which produces
output during drop of VCC, the mute has to be set before
the VCC will drop. This can be achieved by I2C-bus control
or by grounding the MUTE pin.
The basic step width of treble control is 3 dB. The
intermediate steps are obtained by switching 1.5 dB boost
and 1.5 dB attenuation steps.
For use where is no mute in the application before turn off,
a supply voltage drop of more than 1 × VBE will result in a
mute during the voltage drop.
The bass and treble control functions can be switched off
via I2C-bus. In this event the internal signal flow is
1995 Dec 19
5
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6321
The hardware mute function is favourable for use in Radio
Data System (RDS) applications. The zero crossing mute
avoids modulation plops. This feature is an advantage for
mute during changing presets and/or sources (e.g. traffic
announcement during cassette playback).
The power supply should include a VCC buffer capacitor,
which provides a discharging time constant. If the input
signal does not disappear after turn off the input will
become audible after certain time. A 4.7 kΩ resistor
discharges the VCC buffer capacitor, because the internal
current of the IC does not discharge it completely.
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VCC
supply voltage
0
10
V
Vn
voltage at pins 1 and 3 to 32 to
pin 2
0
VCC
V
Tamb
operating ambient temperature
−40
+85
°C
Tstg
storage temperature
−65
+150
°C
Ves
electrostatic handling
note 1
Note
1. Human body model: C = 100 pF; R = 1.5 kΩ; V ≥ 2 kV. Charge device model: C = 200 pF; R = 0 Ω; V ≥ 500 V.
1995 Dec 19
6
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6321
CHARACTERISTICS
VCC = 8.5 V; RS = 600 Ω; RL = 10 kΩ; CL = 2.5 nF; AC coupled; f = 1 kHz; Tamb = 25 °C; gain control Gv = 0 dB; bass
linear; treble linear; fader off; balance in mid position; loudness off; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VCC
supply voltage
7.5
8.5
9.5
V
ICC
supply current
−
26
33
mA
VDC
internal DC voltage at inputs and
outputs
3.83
4.25
4.68
V
Vref
internal reference voltage at pin 21
Gv(max)
maximum voltage gain
Vo(rms)
output voltage level for
−
4.25
−
V
RS = 0 Ω; RL = ∞
19
20
21
dB
Pmax at the power output stage
THD ≤ 0.1%; see Fig.11
−
2000
−
mV
start of clipping
THD = 1%
2300
−
−
mV
RL = 2 kΩ; CL = 10 nF;
THD = 1%
2000
−
−
mV
−
200
−
mV
low frequency (−1 dB)
60
−
−
Hz
low frequency (−3 dB)
30
−
−
Hz
high frequency (−1 dB)
20000 −
−
Hz
Vi(rms)
input sensitivity
Vo = 2000 mV; Gv = 20 dB
fro
roll-off frequency
CKIN = 220 nF;
CKVL = 220 nF; Zi = Zi(min)
CKIN = 470 nF;
CKVL = 100 nF; Zi = Zi(typ)
low frequency (−3 dB)
17
−
−
Hz
90
96
−
dB
Vi = 100 mV; Gv = 20 dB
−
0.1
−
%
αcs
channel separation
Vi = 2 V; frequency range
250 Hz to 10 kHz
THD
total harmonic distortion
frequency range
20 Hz to 12.5 kHz
RR
(S+N)/N
ripple rejection
signal-plus-noise to noise ratio
Vi = 1 V; Gv = 0 dB
−
0.05
0.15
%
Vi = 2 V; Gv = 0 dB
−
0.1
−
%
Vi = 2 V; Gv = −10 dB
−
0.1
−
%
f = 100 Hz
70
76
−
dB
f = 40 Hz to 12.5 kHz
−
66
−
dB
−
105
−
dB
Gv = 0 dB
−
95
−
dB
Gv = 12 dB
−
88
−
dB
Gv = 20 dB
−
81
−
dB
Vr(rms) < 200 mV
unweighted;
20 Hz to 20 kHz RMS;
Vo = 2.0 V; see Figs 6 and 7
CCIR468-2 weighted; quasi
peak; Vo = 2.0 V
1995 Dec 19
7
Philips Semiconductors
Preliminary specification
Sound fader control circuit
SYMBOL
TEA6321
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Pno(rms)
noise output power (RMS value)
only contribution of TEA6321;
power amplifier for 6 W
mute position; note 1
−
−
10
nW
αct
crosstalk

V bus ( p – p )
 20 log -------------------------- between bus
V o ( rms ) 

note 2
−
110
−
dB
25
35
45
kΩ
inputs and signal outputs
Source selector
Zi
input impedance
αS
input isolation of one selected
source to any other input
f = 1 kHz
−
105
−
dB
f = 12.5 kHz
−
95
−
dB
Vi(rms)
maximum input voltage
(RMS value)
THD < 0.5%; VCC = 8.5 V
−
2.15
−
V
THD < 0.5%; VCC = 7.5 V
−
1.8
−
V
Voffset
DC offset voltage at source
selector output by selection of any
inputs
−
−
10
mV
Zo
output impedance
−
80
120
Ω
RL
output load resistance
10
−
−
kΩ
CL
output load capacity
0
−
2500
pF
Gv
voltage gain, source selector
−
0
−
dB
Control part (source selector disconnected; source resistance 600 Ω)
Zi
input impedance volume input
100
150
200
kΩ
input impedance loudness input
25
33
40
kΩ
Zo
output impedance
−
80
120
Ω
RL
output load resistance
2
−
−
kΩ
CL
output load capacity
0
−
10
nF
RDCL
DC load resistance at output to
ground
4.7
−
−
kΩ
Vi(rms)
maximum input voltage
(RMS value)
THD < 0.5%
−
2.15
−
V
Vno
noise output voltage
CCIR468-2 weighted; quasi
peak
Gv = 20 dB
−
110
220
µV
Gv = 0 dB
−
33
50
µV
Gv = −66 dB
−
13
22
µV
mute position
−
10
−
µV
total continuous control range
−
106
−
dB
recommended control range
−
86
−
dB
step resolution
−
1
−
dB
step error between any adjoining
step
−
−
0.5
dB
CRtot
Gstep
1995 Dec 19
8
Philips Semiconductors
Preliminary specification
Sound fader control circuit
SYMBOL
TEA6321
PARAMETER
∆Ga
attenuator set error
∆Gt
gain tracking error
MUTEatt
Voffset
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Gv = +20 to −50 dB
−
−
2
dB
Gv = −51 to −66 dB
−
−
3
dB
Gv = +20 to −50 dB
−
−
2
dB
mute attenuation
see Fig.10
100
110
−
dB
DC step offset between any
adjoining step
Gv = 0 to −66 dB
−
0.2
10
mV
Gv = 20 to 0 dB
−
2
15
mV
−
−
10
mV
DC step offset between any step to Gv = 0 to −66 dB
mute
Volume I control and loudness
CRvol
continuous volume control range
−
51
−
dB
Gv
voltage gain
−31
−
+20
dB
Gstep
step resolution
−
1
−
dB
LBmax
maximum loudness boost
f = 40 Hz
−
17
−
dB
f = 10 kHz
−
4.5
−
dB
16
18
19
dB
loudness on; referred to
loudness off; boost is
determined by external
components
Bass control
Gbass
Gstep
Voffset
bass control, maximum boost
f = 46 Hz
maximum attenuation
f = 46 Hz
16
18
19
dB
step resolution (toggle switching)
f = 46 Hz
−
1.8
−
dB
step error between any adjoining
step
f = 46 Hz
−
−
0.5
dB
−
−
20
mV
11
12
13
dB
DC step offset in any bass position
Treble control
Gtreble
Gstep
Voffset
treble control, maximum boost
f = 15 kHz
maximum attenuation
f = 15 kHz
11
12
13
dB
maximum boost
f > 15 kHz
−
−
15
dB
step resolution (toggle switching)
f = 15 kHz
−
1.5
−
dB
step error between any adjoining
step
f = 15 kHz
−
−
0.5
dB
−
−
10
mV
DC step offset in any treble
position
Volume II, balance and fader control
CR
continuous attenuation fader and
volume control range
53.5
55
56.5
dB
Gstep
step resolution
−
1
2
dB
attenuation set error
−
−
1.5
dB
1995 Dec 19
9
Philips Semiconductors
Preliminary specification
Sound fader control circuit
SYMBOL
TEA6321
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Mute function (see Fig.10)
HARDWARE MUTE
mute switch level (2 × VBE)
−
1.45
−
V
VswLOW
input level
−
−
1.0
V
Ii
input current
−300
−
−
µA
Vsw
mute active
VswLOW = 1 V
mute passive: level internally defined
VswHIGH
saturation voltage
−
−
VCC
V
td(mute)
delay until mute passive
−
−
0.5
ms
ZERO CROSSING MUTE
Id
discharge current
0.3
0.6
1.2
µA
Ich
charge current
−300
−150
−
µA
VswDEL
delay switch level (3 × VBE)
−
2.2
−
V
td
delay time
−
100
−
ms
Vwind
window for audio signal zero
crossing detection
−
30
40
mV
−
V19 −
0.7
−
V
Cm = 10 nF
Muting at power supply drop
VCCdrop
supply drop for mute active
Power-on reset (when reset is active the GMU-bit (general mute) is set and the I2C-bus receiver is in reset
position)
VCC
increasing supply voltage start of
reset
−
−
2.5
V
end of reset
5.2
6.5
7.2
V
decreasing supply voltage start of
reset
4.2
5.5
6.2
V
Digital part (I2C-bus pins); note 3
ViH
HIGH level input voltage
3
−
9.5
V
ViL
LOW level input voltage
−0.3
−
+1.5
V
IiH
HIGH level input current
−10
−
+10
µA
IiL
LOW level input current
−10
−
+10
µA
VoL
LOW level output voltage
−
−
0.4
V
IL = 3 mA
Notes to the characteristics
1. The indicated values for output power assume a 6 W power amplifier at 4 Ω with 20 dB gain and a fixed attenuator
of 12 dB in front of it. Signal-to-noise ratios exclude noise contribution of the power amplifier.
2. The transmission contains: total initialization with MAD and subaddress for volume and 8 data words, see also
definition of characteristics, clock frequency = 50 kHz, repetition burst rate = 400 Hz, maximum bus signal
amplitude = 5 V (p-p).
3. The AC characteristics are in accordance with the I2C-bus specification. This specification, “The I2C-bus and how to
use it”, can be ordered using the code 9398 393 40011.
1995 Dec 19
10
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6321
I2C-BUS PROTOCOL
I2C-bus format
S(1)
SLAVE ADDRESS(2)
A(3)
SUBADDRESS(4)
A(3)
DATA(5)
A(3)
P(6)
Notes
1. S = START condition.
2. SLAVE ADDRESS (MAD) = 1000 0000.
3. A = acknowledge, generated by the slave.
4. SUBADDRESS (SAD), see Table 1.
5. DATA, see Table 1.
6. P = STOP condition.
Table 1
Second byte after MAD.
MSB
FUNCTION
LSB
BIT
7
6
5
4
3
2(1)
1(1)
0(1)
Volume/loudness
V
0
0
0
0
0
0
0
0
Fader front right
FFR
0
0
0
0
0
0
0
1
Fader front left
FFL
0
0
0
0
0
0
1
0
Fader rear right
FRR
0
0
0
0
0
0
1
1
Fader rear left
FRL
0
0
0
0
0
1
0
0
Bass
BA
0
0
0
0
0
1
0
1
Treble
TR
0
0
0
0
0
1
1
0
Switch
S
0
0
0
0
0
1
1
1
Note
1. Significant subaddress.
1995 Dec 19
11
Philips Semiconductors
Preliminary specification
Sound fader control circuit
Table 2
TEA6321
Definition of third byte after MAD and SAD
MSB
FUNCTION
LSB
BIT
7
6
5
4
3
2
1
0
ZCM(1)
LOFF(2)
V5(3)
V4(3)
V3(3)
V2(3)
V1(3)
V0(3)
Volume/loudness
V
Fader front right
FFR
X(4)
X(4)
FFR5(5) FFR4(5) FFR3(5) FFR2(5) FFR1(5) FFR0(5)
Fader front left
FFL
X(4)
X(4)
FFL5(6)
FFL4(6)
FFL3(6)
FFL2(6)
FFL1(6)
FFL0(6)
Fader rear right
FRR
X(4)
X(4)
FRR5(7)
FRR4(7)
FRR3(7)
FRR2(7)
FRR1(7)
FRR0(7)
Fader rear left
FRL
X(4)
X(4)
FRL5(8)
FRL4(8)
FRL3(8)
FRL2(8)
FRL1(8)
FRL0(8)
Bass
BA
X(4)
X(4)
X(4)
BA4(9)
BA3(9)
BA2(9)
BA1(9)
BA0(9)
Treble
TR
X(4)
X(4)
X(4)
TR4(10)
TR3(10)
TR2(10)
TR1(10)
TR0(10)
Switch
S
GMU(11)
X(4)
X(4)
X(4)
X(4)
SC2(12)
SC1(12)
SC0(12)
Notes
1. Zero crossing mode.
2. Switch loudness on/off.
3. Volume control.
4. Don’t care bits (logic 1 during testing).
5. Fader control front right.
6. Fader control front left.
7. Fader control rear right.
8. Fader control rear left.
9. Bass control.
10. Treble control.
11. Mute control for all outputs except the outputs OVL and OVR (general mute).
12. Source selector control.
1995 Dec 19
12
Philips Semiconductors
Preliminary specification
Sound fader control circuit
Table 3
TEA6321
Volume I setting
Gv
(dB)
DATA
V5
V4
V3
V2
V1
V0
Loudness on: the increment of the loudness characteristics is linear at every volume step in the range from
+20 to −11 dB
+20
1
1
1
1
1
1
+19
1
1
1
1
1
0
+18
1
1
1
1
0
1
+17
1
1
1
1
0
0
+16
1
1
1
0
1
1
+15
1
1
1
0
1
0
+14
1
1
1
0
0
1
+13
1
1
1
0
0
0
+12
1
1
0
1
1
1
+11
1
1
0
1
1
0
+10
1
1
0
1
0
1
+9
1
1
0
1
0
0
+8
1
1
0
0
1
1
+7
1
1
0
0
1
0
+6
1
1
0
0
0
1
+5
1
1
0
0
0
0
+4
1
0
1
1
1
1
+3
1
0
1
1
1
0
+2
1
0
1
1
0
1
+1
1
0
1
1
0
0
0
1
0
1
0
1
1
−1
1
0
1
0
1
0
−2
1
0
1
0
0
1
−3
1
0
1
0
0
0
−4
1
0
0
1
1
1
−5
1
0
0
1
1
0
−6
1
0
0
1
0
1
−7
1
0
0
1
0
0
−8
1
0
0
0
1
1
−9
1
0
0
0
1
0
−10
1
0
0
0
0
1
−11
1
0
0
0
0
0
1995 Dec 19
13
Philips Semiconductors
Preliminary specification
Sound fader control circuit
Gv
(dB)
TEA6321
DATA
V5
V4
V3
V2
V1
V0
Loudness characteristic is constant in a range from −11 dB to −31 dB
−12
0
1
1
1
1
1
−13
0
1
1
1
1
0
−14
0
1
1
1
0
1
−15
0
1
1
1
0
0
−16
0
1
1
0
1
1
−17
0
1
1
0
1
0
−18
0
1
1
0
0
1
−19
0
1
1
0
0
0
−20
0
1
0
1
1
1
−21
0
1
0
1
1
0
−22
0
1
0
1
0
1
−23
0
1
0
1
0
0
−24
0
1
0
0
1
1
−25
0
1
0
0
1
0
−26
0
1
0
0
0
1
−27
0
1
0
0
0
0
−28
0
0
1
1
1
1
−29
0
0
1
1
1
0
−30
0
0
1
1
0
1
−31
0
0
1
1
0
0
Repetition of steps in a range from −28 dB to −31 dB
−28
0
0
1
0
1
1
−29
0
0
1
0
1
0
−30
0
0
1
0
0
1
−31
0
0
1
0
0
0
−28
0
0
0
1
1
1
−29
0
0
0
1
1
0
−30
0
0
0
1
0
1
−31
0
0
0
1
0
0
−28
0
0
0
0
1
1
−29
0
0
0
0
1
0
−30
0
0
0
0
0
1
−31
0
0
0
0
0
0
1995 Dec 19
14
Philips Semiconductors
Preliminary specification
Sound fader control circuit
Table 4
TEA6321
Volume II setting (fader and balance); note 1
DATA
FRR5
FRR4
FRR3
FRR2
FRR1
FRR0
FRL5
FRL4
FRL3
FRL2
FRL1
FRL0
FFL5
FFL4
FFL3
FFL2
FFL1
FFL0
FFR5
FFR4
FFR3
FFR2
FFR1
FFR0
0
1
1
1
1
1
1
−1
1
1
1
1
1
0
−2
1
1
1
1
0
1
−3
1
1
1
1
0
0
−4
1
1
1
0
1
1
−5
1
1
1
0
1
0
−6
1
1
1
0
0
1
−7
1
1
1
0
0
0
−8
1
1
0
1
1
1
Gv
(dB)
−9
1
1
0
1
1
0
−10
1
1
0
1
0
1
−11
1
1
0
1
0
0
−12
1
1
0
0
1
1
−13
1
1
0
0
1
0
−14
1
1
0
0
0
1
−15
1
1
0
0
0
0
−16
1
0
1
1
1
1
−17
1
0
1
1
1
0
−18
1
0
1
1
0
1
−19
1
0
1
1
0
0
−20
1
0
1
0
1
1
−21
1
0
1
0
1
0
−22
1
0
1
0
0
1
−23
1
0
1
0
0
0
−24
1
0
0
1
1
1
−25
1
0
0
1
1
0
−26
1
0
0
1
0
1
−27
1
0
0
1
0
0
−28
1
0
0
0
1
1
−29
1
0
0
0
1
0
−30
1
0
0
0
0
1
−31
1
0
0
0
0
0
−32
0
1
1
1
1
1
−33
0
1
1
1
1
0
−34
0
1
1
1
0
1
1995 Dec 19
15
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6321
DATA
FRR5
FRR4
FRR3
FRR2
FRR1
FRR0
FRL5
FRL4
FRL3
FRL2
FRL1
FRL0
FFL5
FFL4
FFL3
FFL2
FFL1
FFL0
FFR5
FFR4
FFR3
FFR2
FFR1
FFR0
−35
0
1
1
1
0
0
−36
0
1
1
0
1
1
−37
0
1
1
0
1
0
−38
0
1
1
0
0
1
−39
0
1
1
0
0
0
−40
0
1
0
1
1
1
−41
0
1
0
1
1
0
−42
0
1
0
1
0
1
−43
0
1
0
1
0
0
−44
0
1
0
0
1
1
−45
0
1
0
0
1
0
−46
0
1
0
0
0
1
−47
0
1
0
0
0
0
−48
0
0
1
1
1
1
−49
0
0
1
1
1
0
−50
0
0
1
1
0
1
−51
0
0
1
1
0
0
−52
0
0
1
0
1
1
−53
0
0
1
0
1
0
−54
0
0
1
0
0
1
Gv
(dB)
−55
0
0
1
0
0
0
mute
0
0
0
1
1
1
mute
0
0
0
1
1
0
mute
0
0
0
1
0
1
mute
0
0
0
1
0
0
mute
0
0
0
0
1
1
mute
0
0
0
0
1
0
mute
0
0
0
0
0
1
mute
0
0
0
0
0
0
Note
1. For a particular range the data is always the same, only the subaddress changes.
1995 Dec 19
16
Philips Semiconductors
Preliminary specification
Sound fader control circuit
Table 5
TEA6321
Bass setting
DATA
Gbass
(dB)
BA4
BA3
BA2
BA1
BA0
+18.0
1
1
1
1
1
+16.2
1
1
1
1
0
+18.0
1
1
1
0
1
+16.2
1
1
1
0
0
+18.0
1
1
0
1
1
+16.2
1
1
0
1
0
+14.4
1
1
0
0
1
+12.6
1
1
0
0
0
+10.8
1
0
1
1
1
+9.0
1
0
1
1
0
+7.2
1
0
1
0
1
+5.4
1
0
1
0
0
+3.6
1
0
0
1
1
+1.8
1
0
0
1
0
0(1)
1
0
0
0
1
0(2)
1
0
0
0
0
−1.8
0
1
1
1
1
−3.6
0
1
1
1
0
−5.4
0
1
1
0
1
−7.2
0
1
1
0
0
−9.0
0
1
0
1
1
−10.8
0
1
0
1
0
−12.6
0
1
0
0
1
−14.4
0
1
0
0
0
−16.2
0
0
1
1
1
−18.0
0
0
1
1
0
−16.2
0
0
1
0
1
−18.0
0
0
1
0
0
note 3
0
0
0
1
1
note 3
0
0
0
1
0
note 3
0
0
0
0
1
notes 3 and 4
0
0
0
0
0
Notes
1. Recommended data word for step 0 dB.
2. Result of 1.8 dB boost and 1.8 dB attenuation.
3. The last four bass control data words mute the bass response.
4. The last bass control and treble control data words (00000) enable the external equalizer connection.
1995 Dec 19
17
Philips Semiconductors
Preliminary specification
Sound fader control circuit
Table 6
TEA6321
Treble setting
DATA
Gtreble
(dB)
TR4
TR3
TR2
TR1
TR0
+12.0
1
1
1
1
1
+10.5
1
1
1
1
0
+12.0
1
1
1
0
1
+10.5
1
1
1
0
0
+12.0
1
1
0
1
1
+10.5
1
1
0
1
0
+12.0
1
1
0
0
1
+10.5
1
1
0
0
0
+9.0
1
0
1
1
1
+7.5
1
0
1
1
0
+6.0
1
0
1
0
1
+4.5
1
0
1
0
0
+3.0
1
0
0
1
1
+1.5
1
0
0
1
0
0(1)
1
0
0
0
1
0(2)
1
0
0
0
0
−1.5
0
1
1
1
1
−3.0
0
1
1
1
0
−4.5
0
1
1
0
1
−6.0
0
1
1
0
0
−7.5
0
1
0
1
1
−9.0
0
1
0
1
0
−10.5
0
1
0
0
1
−12.0
0
1
0
0
0
note 3
0
0
1
1
1
note 3
0
0
1
1
0
note 3
0
0
1
0
1
note 3
0
0
1
0
0
note 3
0
0
0
1
1
note 3
0
0
0
1
0
note 3
0
0
0
0
1
notes 3 and 4
0
0
0
0
0
Notes
1. Recommended data word for step 0 dB.
2. Result of 1.5 dB boost and 1.5 dB attenuation.
3. The last eight treble control data words select treble output.
4. The last treble control and bass control data words (00000) enable the external equalizer connection.
1995 Dec 19
18
Philips Semiconductors
Preliminary specification
Sound fader control circuit
Table 7
TEA6321
Loudness setting
Table 9
CHARACTERISTIC
DATA LOFF
With loudness
0
Linear
1
Table 8
Mute mode
DATA
FUNCTION
Selected input
DATA
FUNCTION
SC2
SC1
SC0
Stereo inputs IAL and IAR
1
1
1
Stereo inputs IBL and IBR
1
1
0
Stereo inputs ICL and ICR
1
0
1
Stereo inputs IDL and IDR
1
0
0
Mono input IMO
0
X(1)
X(1)
GMU
ZCM
Direct mute off
0
0
Mute off delayed until the next zero
crossing
0
1
Direct mute
1
0
Mute delayed until the next zero
crossing
1
1
Note
1. X = don’t care bits (logic 1 during testing).
MED840
20
handbook, full pagewidth
Gbass
(dB)
10
0
−10
−20
10
10 2
10 3
Fig.3 Bass control.
1995 Dec 19
19
f (Hz)
10 4
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6321
MED424
15
handbook, full pagewidth
Gtreble
(dB)
10
5
0
−5
−10
−15
10 2
10 3
10 4
f (Hz)
10 5
Fig.4 Treble control.
MED425
handbook,20
full pagewidth
Gv
(dB)
10
0
−10
−20
−30
−40
10
10 2
10 3
10 4
Fig.5 Volume control with loudness (including low roll-off frequency).
1995 Dec 19
20
f (Hz)
10 5
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6321
MED426
100
handbook, full pagewidth
S/N
(dB)
(1)
90
(2)
(3)
80
70
60
50
10 −4
10 −3
10 −2
10 −1
Po (W)
1
10
(1) Vi = 2.0 V.
(2) Vi = 0.5 V.
(3) Vi = 0.2 V.
Fig.6 Signal-to-noise ratio; noise weighted: CCIR468-2, quasi peak.
MED427
110
handbook, full pagewidth
S/N
(dB)
(1)
100
(2)
90
(3)
80
70
60
10 −4
10 −3
10 −2
10 −1
(1) Unweighted RMS.
(2) CCIR468-2 RMS.
(3) CCIR468-2 quasi peak.
Fig.7 Signal-to-noise ratio; Vi = 2 V; Pmax = 6 W.
1995 Dec 19
21
1
Po (W)
10
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6321
MED428
200
handbook, full pagewidth
noise
(µV)
150
100
(1)
50
(2)
0
−70
−50
−30
−10
10
gain (dB)
30
Stereo/mono inputs.
(1) Loudness on.
(2) Loudness off.
Fig.8 Noise output voltage; CCIR468-2, quasi peak.
MED429
−60
handbook, full pagewidth
(dB)
−80
−100
−120
−140
20
50
10 2
200
500
10 3
Fig.9 Muting.
1995 Dec 19
22
2 x 10 3
5 x 10 3
10 4
2 x 10 4
f (Hz)
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6321
mute pin 12
handbook, full pagewidth
hardware mute switch
ICH = −150 µA
TEA6321
U
(V)
ID = 0.6 µA
Cm = 10 nF
I
(µA)
0.5 ms delay until
mute passive
VCC
8.5
0
delay switch (1)
2.2
level
−150
mute switch 1.45
level
MED841
100 ms
zero crossing
mute start
end of delay
t (ms)
hard mute
on
hard mute
off
(1) Typically 2.2 V; referenced to 3 × VBE
Fig.10 Mute function diagram.
1995 Dec 19
23
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6321
If the 20 dB gain is not required for the maximum volume
position, it will be an advantage to use the maximum boost
gain and then increased attenuation in the last section,
Volume II.
Therefore the loudness will be at the correct place and a
lower noise and offset voltage will be achieved.
POWER STAGE
handbook, halfpage
TEA6321
G = 20 dB
VI(min) = 200 mV
Vo = 2 V for P(max)
P(max) = 100 W at 4 Ω
MBE910
a.
POWER STAGE
handbook, halfpage
TEA6321
G = 26 dB
VI(min) = 200 mV
Vo = 1 V for P(max)
P(max) = 100 W at 4 Ω
MED842
b.
a. Gain volume I = 20 dB (Gv(max)); gain volume II = 0 dB; fader and balance range = 55 dB.
b. Gain volume I = 20 dB (Gv(max)); gain volume II = −6 dB global setting; fader and balance range now 49 dB, previously 55 dB.
Fig.11 Level diagram.
1995 Dec 19
24
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6321
handbook, full pagewidth
VP
+8.5 V to
oscilloscope
+
VCC
8.5 V
470 µF
4.7 kΩ
inputs
31
16
15
13
11
14
17
18
20
22
3
4
TEA6321
outputs to
oscilloscope
29
30
2
9 × 220 nF
19
21
47
µF
9 × 600 Ω
4 × 4.7 µF
100
µF
4 × 10 kΩ
MED843
Fig.12 Turn-on/off power supply circuit diagram.
MED433
10
handbook, full pagewidth
(V)
8
(1)
6
4
(2)
2
0
0
1
2
3
(1) VCC.
(2) VO.
Fig.13 Turn-on/off behaviour.
1995 Dec 19
25
4
t (s)
5
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6321
handbook, full pagewidth
3.4 k Ω
220 nF
270 nF
270 nF
5.6 nF
10 nF
100 µF
21 10
VCC = 8.5 V
7
8
6
5
12
31
0.1 µF
10 kΩ
32
SCL
1
SDA
2
TEA6321
1000 µF
19
VP
47 µF
0.2 V (RMS)
600 Ω
220 nF
output right
output left
front and rear
input A to D left and right
and input mono
23
26
25
220 nF
27
270 nF
4.7 µF
VO
28
MED844
5.6 nF
270 nF
3.4 k Ω
Fig.14 Test circuit for power supply ripple rejection (RR).
handbook, full pagewidth
220 nF
3.4 k Ω
270 nF 5.6 nF
270 nF
10 nF
100 µF
21 10
VCC = 8.5 V
8
7
6
5
12
31
0.1 µF
470 µF
32
SCL
1
SDA
2
TEA6321
Vp
19
47 µF
input A to D right and left
220 nF
Vi
600 Ω
220 nF
output left
output right
front and rear
input A to D left and right
and input mono
23
25
220 nF
26
270 nF
27
270 nF
5.6 nF
Fig.15 Test circuit for channel separation (αcs).
26
VO
28
3.4 k Ω
1995 Dec 19
4.7 µF
MED845
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6321
Selection of input signals by using the zero crossing
mute mode
follows the input A signal, until the next zero crossing
occurs and then activates mute.
A selection from input A (IAL) to input B (IBL) left sources
produces a modulation click depending on the difference
of the signal values at the time of switching.
After a fixed delay time at t2, the microcontroller sends the
bits for input switching and mute inactive.
The output signal remains muted until the next signal zero
crossing of input B (IBL) occurs, and then follows that
signal.
At t1 the maximum possible difference between signals is
7 V(p-p) (see Fig.16) and gives a large click. Using the
cross detector no modulation click is audible.
The delay time t2 − t1 is e.g. 40 ms. Therefore the capacity
Cm = 3.3 nF. The zero cross function is working at the
lowest frequency of 40 Hz determined by the Cm capacitor.
For example: The selection is enabled at t1, the
microcontroller sets the zero cross bit (ZCM = 1) and then
the mute bit (GMU = 1) via the I2C-bus. The output signal
handbook, full pagewidth
MED436
V
4
(1)
3
2
1
0
−1
(2)
t1
t
t2
(3)
−2
−3
−4
(1) Input A (IAL).
(2) Output.
(3) Input B (IBL).
Fig.16 Zero cross function; only one channel shown.
1995 Dec 19
27
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6321
Loudness filter calculation example
Figure 17 shows the basic loudness circuit with an
external low-pass filter application. R1 allows an
attenuation range of 21 dB while the boost is determined
by the gain stage V2. Both result in a loudness control
range of +20 to −12 dB.
handbook, halfpage
CKVL
Defining fref as the frequency where the level does not
change while switching loudness on/off. The external
resistor R3 for fref → ∞ can be calculated as:
0 dB
8
V1
R1
33 kΩ
V2
9
C1
Gv
------20
10
R3 = R1 -------------------- . With Gv = −21 dB and R1 = 33 kΩ,
G
R2
R3
v
------20
MED437
1 – 10
R3 = 3.2 kΩ is generated.
For the low-pass filter characteristic the value of the
external capacitor C1 can be determined by setting a
specific boost for a defined frequency and referring the
gain to Gv at fref as indicated above.
Fig.17 Basic loudness circuit.
Gv
------20
( R1 + R3 ) × 10 – R3
1
--------------------- = ------------------------------------------------------------Gv
j ( ωC1 )
------20
1 – 10
handbook, halfpage
220 nF
For example: 3 dB boost at f = 1 kHz
Gv = Gv(ref) + 3 dB = −18 dB; f = 1 kHz and C1 = 100 nF.
0 dB
8
8.2 nF
If a loudness characteristic with additional high frequency
boost is desired, an additional high-pass section has to be
included in the external filter circuit as indicated in the
block diagram. A filter configuration that provides
AC coupling avoids offset voltage problems.
20 kΩ
V1
R1
33 kΩ
9
V2
150 nF
R2
2.2 kΩ
Figure 18 shows an example of the loudness circuit with
bass and treble boost. The calculation of this network is
numeric.
MED846
Fig.18 Loudness circuit with bass and treble boost.
1995 Dec 19
28
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6321
INTERNAL PIN CONFIGURATIONS
Values shown in Figs 19 to 31 are typical DC values;
VCC = 8.5 V.
3
+
4.25 V
1
5V
1.8 kΩ
80 Ω
MBE911
MBE912
Fig.19 Pin 1: SDA (I2C-bus data).
Fig.20 Pins 3, 4, 29, 30: output signals.
+
5
+
4.25 V
6
4.25 V
+
80 Ω
2.4 kΩ
MBE913
MBE914
Fig.21 Pins 5 and 28: treble control capacitors.
1995 Dec 19
Fig.22 Pins 6 and 27: bass control capacitor outputs.
29
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6321
7
4.25 V
8
+
3.52 kΩ
4.25 V
+
150 kΩ
4.25 V
MED847
MBE915
Fig.23 Pins 7 and 26: bass control capacitor inputs.
Fig.24 Pins 8 and 25: input volume 1, control part.
+
9
10
4.25 V
4.25 V
+
80 Ω
1.12 kΩ
MBE905
MBE906
Fig.25 Pins 9 and 24: input loudness, control part.
1995 Dec 19
Fig.26 Pins 10 and 23: output source selector.
30
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6321
12
11
4.25 V
1.3 kΩ
+
8.5 V
constant
2.2 V
+
maximum
200µA
35 kΩ
0.6 µA
constant
4.25 V
4.5 kΩ
MBE907
MBE908
Fig.27 Pins 11, 13 to 18, 20, 22: inputs.
Fig.28 Pin 12: mute control.
+
19
4.7 kΩ
8.5 V
300 Ω
+
3.4 kΩ
5 kΩ
4.25 V
21
3.4 kΩ
MED439
Fig.29 Pin 19: filtering for supply; pin 21: reference voltage.
31
32
apply +8.5 V to this pin
5V
MED440
MBE909
Fig.31 Pin 32: SCL (I2C-bus clock).
Fig.30 Pin 31: supply voltage.
1995 Dec 19
1.8 kΩ
31
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6321
PACKAGE OUTLINE
SO32: plastic small outline package; 32 leads; body width 7.5 mm
SOT287-1
D
E
A
X
c
y
HE
v M A
Z
17
32
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
16
1
0
detail X
w M
bp
e
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
2.65
0.3
0.1
2.45
2.25
0.25
0.49
0.36
0.27
0.18
20.7
20.3
7.6
7.4
1.27
10.65
10.00
1.4
1.1
0.4
1.2
1.0
0.25
0.25
0.1
0.95
0.55
0.01
0.02
0.01
0.011
0.007
0.81
0.80
0.30
0.29
0.419
0.050
0.394
inches
0.10
0.012 0.096
0.004 0.086
0.043
0.055
0.016
0.047
0.039
0.01
0.01
0.037
0.004
0.022
θ
8o
0o
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
95-01-25
97-05-22
SOT287-1
1995 Dec 19
EUROPEAN
PROJECTION
32
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6321
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
Repairing soldered joints
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Reflow soldering
Reflow soldering techniques are suitable for all SO
packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
Wave soldering
Wave soldering techniques can be used for all SO
packages if the following conditions are observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
• The package footprint must incorporate solder thieves at
the downstream end.
1995 Dec 19
33
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6321
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1995 Dec 19
34
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6321
NOTES
1995 Dec 19
35
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SCDS47
© Philips Electronics N.V. 1995
All rights are reserved. Reproduction in whole or in part is prohibited without the
prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation
or contract, is believed to be accurate and reliable and may be changed without
notice. No liability will be accepted by the publisher for any consequence of its
use. Publication thereof does not convey nor imply any license under patent- or
other industrial or intellectual property rights.
Printed in The Netherlands
513061/1100/02/pp36
Document order number:
Date of release: 1995 Dec 19
9397 750 00534