Ordering number : ENA1868 Bi-CMOS IC LV8414CS Microstep Driver Motor Driver IC Overview The LV8414CS is a motor driver IC that incorporates two channels of PWM constant-current control micro-step drivers. Miniaturization using the wafer level package (WLP) makes the IC ideally suited for driving the stepping motors used to control the lenses in digital still cameras, cell phone camera modules and other such devices. Features • Two channels of 256-division micro-step drivers • Excitation step proceeds only by step signal input • Peak excitation current switchable to one of 16 levels • Serial data control using I2C interface • Built-in thermal protection circuit • Low supply voltage protection circuit incorporated • On-chip photo sensor drive transistors • On-chip Schmitt buffer Specifications Maximum Ratings at Ta = 25°C Parameter Symbol Conditions Ratings Unit Maximum supply voltage 1 VM max 6.0 Maximum supply voltage 2 VCC max 6.0 V Output peak current IOpeak 600 mA Continuous output current 1 IO max1 ch1 to 4 Continuous output current 2 IO max2 PI Allowable power dissipation Pd max *Mounted on a specified board. 1.0 W Operating temperature Topr -30 to +85 °C Storage temperature Tstg -55 to +150 °C ch1 to 4 V t ≤ 10ms, ON-duty ≤ 20% 400 mA 30 mA * Specified circuit board : 40mm×50mm×0.8mm, glass epoxy four-layer board. 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D1510 SY PC 20101025-S00003 No.A1868-1/36 LV8414CS Allowable Operating Conditions at Ta = 25°C Parameter Symbol Conditions Ratings Unit Operating supply voltage range1 VM op 2.5 to 5.5 V Operating supply voltage range2 VCC op 2.5 to 5.5 V Logic input voltage VIN CLK input frequency FIN 0 to VCC+0.3 CLK1 to 2 100 V kHz Electrical Characteristics at Ta = 25°C, VM = 5.0V, VCC = 3.3V Parameter Symbol Ratings Conditions min Standby mode current drain Istn ENA = "L" VM current drain IM ENA = "H", IM1 + IM2, with no load VCC current drain ICC ENA = "H" typ Unit max 1.0 μA 50 100 200 μA 0.75 1.5 3.0 mA VCC low-voltage cutoff voltage VthVCC 2.0 2.25 2.5 V Low-voltage hysteresis voltage VthHYS 100 150 200 mV Thermal shutdown temperature TSD Design guarantee value * 160 180 200 °C Thermal hysteresis width ΔTSD Design guarantee value * 10 30 50 °C Rin ENA, CLK1 to 2, FR1 to 2 50 100 200 kΩ 1.0 μA 16.5 33 66 μA Micro-step driver Logic pin internal pull-down resistance Logic pin input current IinL VIN = 0, ENA, CLK1 to 2, FR1 to 2 IinH VIN = 3.3V, ENA, CLK1 to 2, FR1 to 2 Logic high-level voltage VinH ENA, SCL, SDA, CLK1 to 2, FR1 to 2 Logic low-level voltage VinL ENA, SCL, SDA, CLK1 to 2, FR1 to 2 Output on-resistance Ronu IO = 100mA, upper ON resistance 0.38 Ω Rond IO = 100mA, lower ON resistance 0.22 Ω Ron IO = 100mA, sum of upper- and lower-side on resistance 0.6×VCC V 0.2×VCC 0.6 V 1.0 Ω 1.0 μA Output leakage current IOleak Diode forward voltage VD 0.45 0.75 1.1 V Chopping frequency Fchop00 280 400 520 kHz Fchop01 140 200 260 kHz Fchop10 420 600 780 kHz kHz Current setting reference voltages ID = -100mA Fchop11 210 300 390 VSEN00 0.185 0.200 0.215 V VSEN01 0.175 0.190 0.205 V VSEN02 0.165 0.180 0.195 V VSEN03 0.155 0.170 0.185 V VSEN04 0.145 0.160 0.175 V VSEN05 0.135 0.150 0.165 V VSEN06 0.125 0.140 0.155 V VSEN07 0.115 0.130 0.145 V VSEN08 0.105 0.120 0.135 V VSEN09 0.095 0.110 0.125 V VSEN10 0.085 0.100 0.115 V VSEN11 0.075 0.090 0.105 V VSEN12 0.065 0.080 0.095 V VSEN13 0.055 0.070 0.085 V VSEN14 0.045 0.060 0.075 V VSEN15 0.035 0.050 0.065 V 1.5 2.5 Ω 1.0 μA PI (Photo sensor driving transistor) Output on-resistance Ron Output leakage current IOleak IO = 10mA Schmitt buffer Logic input high-level voltage VinH BI1, BI2 Logic input low-level voltage VinL BI1, BI2 0.5×VCC V 0.25×VCC V * : Design target value, not to be measured at production test. No.A1868-2/36 LV8414CS Package Dimensions unit : mm (typ) 3406 0.235 0.4 F E D 2.47 0.4 C B A 2.47 6 4 3 2 1 0.65 MAX 0.245 0.42 SIDE VIEW 5 Pd max – Ta 1.2 BOTTOM VIEW Allowable power dissipation, Pd max -- W SIDE VIEW 0.235 TOP VIEW Specified board : 40 × 50 × 0.8mm3 glass epoxy four-layer board 1.00 1.0 0.8 0.6 0.52 0.4 0.2 0 --30 --20 0 20 40 60 80 85 100 0.175 Ambient temperature, Ta -- °C SANYO : WLP32J(2.47X2.47) Pin Assignment 2.47 BI1 OUT1A PGND1 0.4 PGND2 OUT3A BI2 A BI2 OUT3A PGND2 PGND1 OUT1A BI1 0.4 SGND RF3 B RF3 SGND CLK2 OUT3B C OUT3B CLK2 FR2 OUT4A D OUT4A FR2 PI MO RF4 E RF4 MO PI VM1 VM2 OUT4B BO2 F BO2 OUT4B 3 4 5 6 6 5 RF1 N.C OUT1B CLK1 OUT2A FR1 RF2 ENA VCC BO1 OUT2B 1 2 2.47 SCL SDA Top View SDA SCL N.C RF1 CLK1 OUT1B FR1 OUT2A VCC ENA RF2 VM2 VM1 OUT2B BO1 4 3 2 1 Bottom View No.A1868-3/36 + - + + OUT2B VM2 OUT3A + OUT4A + OUT4B VCC SGND ENA CLK1 CLK2 FR1 FR2 SCL SDA MO PI VCC 30mA max BI1 BI2 BO1 I2C Interface Start-up control block Excitation signal generator Monitor selector Microstep current setting PGND2 BO2 Excitation signal generator Microstep current setting Oscillator circuit Microstep current setting Output control logic OUT3B Thermal shutdown circuit LVS circuit Monitor selector Microstep current setting Output control logic OUT2A RF3 OUT1B RF4 OUT1A RF2 VM1 RF1 PGND1 + - LV8414CS Block Diagram No.A1868-4/36 LV8414CS Pin Functions Pin No. Pin Name A1 BI1 A6 BI2 B3 SCL Function Equivalent Circuit Schmitt buffer input pin VCC I2C Interface IN SGND B4 SDA I2C Interface VCC SDA SGND E2 ENA Chip enable pin C2 CLK1 Step signal input pin C5 CLK2 D2 FR1 D5 FR2 VCC Forward/reverse rotation setting signal input pin IN 100kΩ SGND A2 OUT1A A5 OUT3A C1 OUT1B C6 OUT3B D1 OUT2A D6 OUT4A F2 OUT2B H bridge output pin VM OUT F5 OUT4B B1 RF1 B6 RF2 E1 RF3 E6 RF4 E5 MO Monitor output pin F1 BO1 Schmitt buffer output pin F6 BO2 Current-sense resistor connection pins RF VCC 500Ω OUT SGND Continued on next page. No.A1868-5/36 LV8414CS Continued from preceding page. Pin No. E4 Pin Name PI Function Photo sensor drive transistor output pin Equivalent Circuit PI SGND E3 VCC B5 SGND Signal ground F3 VM1 Motor power supply connection pin F4 VM2 A3 PGND1 A4 PGND2 B2 N.C. Logic power supply connection pin Power ground Unused pin No.A1868-6/36 LV8414CS Serial Bus Communication Specifications I2C serial transfer timing conditions twH SCL th1 twL tbuf SDA th1 ts2 th2 ts1 ts3 Resend start condition Start condition ton Stop condition tof Input waveform condition Standard mode Parameter symbol Conditions min typ SCL clock frequency Data setup time ts1 Setup time of SCL with respect to the falling edge of SDA 4.7 ts2 Setup time of SDA with respect to the rising edge of SCL 250 ns ts3 Setup time of SCL with respect to the rising edge of SDA 4.0 μs μs Pulse width 100 unit fscl Data hold time 0 max SCL clock frequency kHz μs th1 Hold time of SCL with respect to the rising edge of SDA 4.0 th2 Hold time of SDA with respect to the falling edge of SCL 0.08 μs twL SCL low period pulse width 4.7 μs 4.0 twH SCL high period pulse width Input waveform conditions ton SCL, SDA (input) rising time tof SCL, SDA (input) falling time Bus free time tbuf Interval between stop condition and start condition μs 1000 μs 300 μs μs 4.7 High-speed mode Parameter Symbol Conditions min typ SCL clock frequency Data setup time ts1 Setup time of SCL with respect to the falling edge of SDA 0.6 ts2 Setup time of SDA with respect to the rising edge of SCL 100 ns ts3 Setup time of SCL with respect to the rising edge of SDA 0.6 μs μs Pulse width 400 unit fscl Data hold time 0 max SCL clock frequency kHz μs th1 Hold time of SCL with respect to the rising edge of SDA 0.6 th2 Hold time of SDA with respect to the falling edge of SCL 0.08 μs twL SCL low period pulse width 1.3 μs 0.6 twH SCL high period pulse width Input waveform conditions ton SCL, SDA (input) rising time tof SCL, SDA (input) falling time Bus free time tbuf Interval between stop condition and start condition 1.3 μs 300 μs 300 μs μs No.A1868-7/36 LV8414CS 2 I C bus transmission method Start and stop conditions The I2C bus requires that the state of SDA be preserved while SCL is high as shown in the timing diagram below during a data transfer operation. SCL SDA ts2 th2 When data is not being transferred, both SCL and SDA are in the high state. The start condition is generated and access is started when SDA is changed from high to low while SCL and SDA are high. Conversely, the stop condition is generated and access is ended when SDA is changed from low to high while SCL is high. Start condition Stop condition th1 ts3 SCL SDA Data transfer and acknowledgement response After the start condition is generated, data is transferred one byte (8 bits) at a time. Any number of data bytes can be transferred consecutively. An ACK signal is sent to the sending side from the receiving side every time 8 bits of data are transferred. The transmission of an ACK signal is performed by setting the receiving side SDA to low after SDA at the sending side is released immediately after the clock pulse of SCL bit 8 in the data transferred has fallen low. After the receiving side has sent the ACK signal, if the next byte transfer operation is to receive only the byte, the receiving side releases SDA on the falling edge of the 9th clock of SCL. There are no CE signals in the I2C bus ; instead, a 7-bit slave address is assigned to each device, and the first byte of the transfer data is allocated to the 7-bit slave address and to the command (R/W) which specifies the direction of subsequent data transfer. The LV8414CS is a drive IC with a dedicated write function and it does not have a read function. The 7-bit address is transferred in sequence starting with MSB, and the eighth bit is set to low. The second and subsequent bytes are transferred in write mode. In the LV8414CS, the slave address is stipulated to be “1110010.”. Start M S B Slave address L S B W A C K M S B Data L S B A C K M S B Data L S B A C K Stop SCL SDA 1 1 1 0 0 1 0 0 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 No.A1868-8/36 LV8414CS Data transfer write format The slave address and Write command must be allocated to the first byte (8 bits) and the register address in the “Serial data truth table” must be designated in the second byte. For the third byte, data transfer is carried out to the address designated by the register address which is written in the second byte. Subsequently, if data continues, the register address value is automatically incremented for the fourth and subsequent bytes. Thus, continuous data transfer starting at the designated address is made possible. When the register address is set to “00000011,” the address to which the next byte is transferred wraps around to "00000000." (1) Data write example S 1 1 1 0 0 1 0 0 A 0 Slave address 0 0 0 0 0 0 1 A Register address set (00000001) Data 1 A Write data to register address 00000001 R/W = 0 written Data 2 A Write data to register address 00000010 S Start condition Data 3 A Write data to register address 00000011 P Stop condition Master side transmission Data 4 A P Write data to register address 00000000 A Acknowledge Slave side transmission (2) Actual example of continuous data transfer Start M S B Slave address L A M S W C S B K B Register address L A M S C S B K B Data L A M S C S B K B Data L A M S C S B K B Data L A M S C S B K B Data L A S C B K Stop SCL SDA 1 1 1 0 0 1 0 0 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 3/4-channel • Output on • Reset release • Forward rotation • Current reference voltage 0.2V 1/2-channel • CLK1 frequency division • 1-2 phase setting 3/4-channel • CLK2 frequency division • 1-2 phase setting • 400kHz chopping • photo sensor OFF • MO output channels set to 1/2 channels • MO output Initial position 1/2-channel • Output on • Reset release • Reverse rotation • Current reference voltage 0.2V Based on the “Serial data truth table” on the next page, the following settings are used for the actual example of the continuous data transfer shown in the above figure. (Data transfer is set at the SCL rising edge of “D0” of each data.) 1/2-channel settings: Output ON, reset release, reverse (CCW) rotation, current reference voltage setting of 0.2V, no CLK1 frequency division, 1-2 phase setting 3/4-channel settings: Output ON, reset release, forward (CW) rotation, current reference voltage setting of 0.2V, no CLK2 frequency division, 1-2 phase setting Other settings: 400kHz chopping frequency, photo sensor OFF, MO output channels set to 1/2 channels, current reference voltage setting of 0.2V No.A1868-9/36 LV8414CS Serial data truth table Register Address A7 0 0 A6 0 0 A5 0 0 A4 0 0 A3 0 0 A2 0 0 Data A1 0 0 A0 0 1 Setting mode Set contents D7 D6 D5 D4 D3 D2 D1 D0 * * * * 0 0 0 0 0.200V * * * * 0 0 0 1 0.190V * * * * 0 0 1 0 0.180V * * * * 0 0 1 1 0.170V * * * * 0 1 0 0 0.160V * * * * 0 1 0 1 0.150V * * * * 0 1 1 0 * * * * 0 1 1 1 * * * * 1 0 0 0 * * * * 1 0 0 1 0.110V * * * * 1 0 1 0 0.100V * * * * 1 0 1 1 0.090V * * * * 1 1 0 0 0.080V * * * * 1 1 0 1 0.070V * * * * 1 1 1 0 0.060V * * * * 1 1 1 1 * * * 0 * * * * * * * 1 * * * * * * 0 * * * * * * * 1 * * * * * * 0 * * * * * * * 1 * * * * * * 0 * * * * * * * 1 * * * * * * * * * * * 0 0 0 0 0.200V * * * * 0 0 0 1 0.190V * * * * 0 0 1 0 0.180V * * * * 0 0 1 1 0.170V * * * * 0 1 0 0 0.160V * * * * 0 1 0 1 0.150V * * * * 0 1 1 0 * * * * 0 1 1 1 * * * * 1 0 0 0 * * * * 1 0 0 1 0.110V * * * * 1 0 1 0 0.100V * * * * 1 0 1 1 0.090V * * * * 1 1 0 0 0.080V * * * * 1 1 0 1 0.070V * * * * 1 1 1 0 0.060V * * * * 1 1 1 1 0.050V * * * 0 * * * * * * * 1 * * * * * * 0 * * * * * * * 1 * * * * * * 0 * * * * * * * 1 * * * * * * 0 * * * * * * * 1 * * * * * * * 0.140V 1/2ch Current reference voltage setting 0.130V 0.120V 0.050V 1/2ch Excitation Direction CW (forward rotation) CCW (reverse rotation) 1/2ch Step/Hold Clear 1/2ch Counter Reset Reset 1/2ch Output Enable Output OFF Hold Clear Output ON 0.140V 3/4ch Current reference voltage setting 3/4ch Excitation Direction 0.130V 0.120V CW (forward rotation) CCW (reverse rotation) 3/4ch Step/Hold Clear 3/4ch Counter Reset Reset 3/4ch Output Enable Output OFF Hold Clear Output ON Continued on next page. No.A1868-10/36 LV8414CS Continued from preceding page. Register Address A7 0 0 A6 0 0 A5 0 0 A4 0 0 A3 0 0 A2 0 0 Data A1 1 1 A0 0 1 Setting mode Set contents D7 D6 D5 D4 D3 D2 D1 D0 * * * * * * 0 0 * * * * * * 0 1 * * * * * * 1 0 * * * * * * 1 1 1/8 * * * * 0 0 * * 1 (frequency division) * * * * 0 1 * * * * * * 1 0 * * * * * * 1 1 * * * * 0 0 * * * * * * 0 1 * * * * * * 1 0 * * * * 1 (frequency division) 1/2ch CLK1 division setting 3/4ch CLK2 division setting 1/2 1/4 1/2 1/4 1/8 Micro-step 1/2ch Excitation mode setting 1-2 phase 1-2 phase (full torque) * * 1 1 * * * * 2 phase 0 0 * * * * * * Micro-step 0 1 * * * * * * 3/4ch Excitation mode setting 1-2 phase 1 0 * * * * * * 1 1 * * * * * * 2 phase * * * * * * 0 0 400kHz * * * * * * 0 1 * * * * * * 1 0 600kHz * * * * * * 1 1 300kHz * * * * * 0 * * * * * * * 1 * * * * * * 0 * * * * * * * 1 * * * * * * 0 * * * * * * * 1 * * * * * * * * * * * * Chopping frequency setting Photo sensor driving 1-2 phase (full torque) 200kHz OFF ON MO output Channel setting MO output position 1/2ch 3/4ch Initial position 1-2 phase position Dummy data - No.A1868-11/36 LV8414CS Precautions for IC operations The supply voltage VCC, ENA pin and I2C output ON setting stand in the following relationship. • VCC, ENA pin, I2C output settings, and outputs VM (3) VCC (1) (2) ENA I2C output setting OFF(Initial state) Output ON OFF setting setting ON OFF setting ON setting setting ON ON OFF(Initial state) ON (1) No output operations are performed unless the ENA pin is set to high and the I2C output setting is set to ON. (2) The I2C setting is accepted even if the ENA pin is in low state. (Other I2C settings are also accepted.) (3) When the supply voltage VCC is set to low, the internal data is reset. (The I2C output setting in the above figure is initialized to OFF state by the fall in the supply voltage VCC.) ENA pin I2C Output Enable setting Output L OFF setting High-impedance state H OFF setting High-impedance state L ON setting High-impedance state H ON setting Output ON state Description of stepping motor drive operations The following state settings related to the control of the stepping motor are established using an I2C serial data communication. ● Excitation mode : ● Excitation direction : ● Step/Hold : ● Counter reset : ● Output enable : ● Current setting reference voltages : ● Chopping frequency : Micro-step (256 divisions), 1-2 phase, 1-2 phase (full torque), or 2-phase CW (clockwise) or CCW (counterclockwise) Clear or Hold Clear or Reset Output Off or Output On Selects one of 16 values Selects one of 4 values 1. CLK pin function CLK input ENA CLK Low * Operating mode Standby mode High Excitation step proceeds High Excitation step is kept The excitation steps are advanced by setting the CLK1 (2) from low to high when the ENA is in high state. No.A1868-12/36 LV8414CS 2. Initial position The excitation mode is set to the initial position when the IC is set to the initial state at power-on or when the counter is reset. Initial position Excitation mode 1ch (3ch) 2ch (4ch) 256 divisions (16W1-2 phase) Micro-step 100% 0% 1-2 phase 100% 0% 1-2 phase (full torque) 100% 0% 2 phase 100% -100% 3. MO pin function By setting the MO output channel and MO output position using the I2C serial data, the MO pin is set to low at the initial position in each excitation mode or at the 1-2 phase position in the micro-step drive mode. * It is assumed that the 1-2 phase setting for the MO output is used in the micro-step drive mode. Even if the MO output position is set to 1-2 phase in the 1-2 phase or 2-phase mode, MO is set to low at the initial position and remains unchanged after it is initialized. * Since the period during which MO is set to low extends from the rising edge of the CLK which is the setting position, to the rising edge of the CLK which moves to the next phase, care must be taken when a frequency division setting has been established. I2C Serial data division setting 1 (frequency division) 1/2 setting ENA CLK1 (CLK2) MO 100% I1 0% -100% 100% I2 0% -100% No.A1868-13/36 LV8414CS 4. Excitation Mode Setting Given below and in the following pages are the timing charts and monitor output pin MO signal in each excitation mode. [1-2 Phase Excitation Timing Chart] CLK1 (CLK2) ENA H MO Position number 100% I1 0% -100% 100% I2 0% -100% 100% 0% 1ch (3ch) current 2ch (4ch) current -100% No.A1868-14/36 LV8414CS [1-2 Phase Excitation (full torque) Timing Chart] CLK1 (CLK2) ENA H MO Position number 100% I1 0% -100% 100% I2 0% -100% 100% 0% 1ch (3ch) current 2ch (4ch) current -100% No.A1868-15/36 LV8414CS [2 Phase Excitation Timing Chart] CLK1 (CLK2) ENA H MO Position number 100% I1 0% -100% 100% I2 0% -100% 100% 0% 1ch (3ch) current 2ch (4ch) current -100% No.A1868-16/36 LV8414CS [Micro-step (16W1-2 Phase Excitation) Timing Chart] CLK1 or CLK2 Expanded view ENA H MO (initial) MO (1-2 Phase) 100% I1 0% -100% 100% I2 0% -100% No.A1868-17/36 LV8414CS 5. Switching the excitation mode during operation The timing at which the results of switching the excitation mode during operation are reflected and the position established after each excitation mode has been switched are as shown below. [Timing at which the results of switching the excitation mode setting are reflected (from 1-2 phase to 2-phase)] The excitation mode switching is set at the rising edge of SCLK (8th bit of SCLK) of “D0” and the setting is reflected starting with the next CLK. I2C Serial data excitation mode setting 1-2 phase setting ENA CLK1 (CLK2) 2 phase setting H 100% I1 0% -100% 100% I2 0% -100% Expanded I2C Serial data excitation mode setting * 2-phase position numbers shown in parentheses 1-2 phase setting 2 phase setting CLK1 (CLK2) 100% I1 0% -100% 100% I2 0% -100% I2C Serial data reflect timing Start M S B Slave address L A S W C B K M S B Register address L A S C B K M S B Data L A S C B K Stop SCL SDA 1 1 1 0 0 1 0 0 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 No.A1868-18/36 LV8414CS [Positions when switching the excitation mode setting] (1) Switching to the micro-step mode When operation has been switched from each excitation mode to the micro-step mode, excitation position proceeds to the next micro step position by the first pulse generated after the switching. 1-channel phase current ratio (%) 100.0 θ64 θ63 θ62 θ32' (2 phase, 1-2 phase full torque) θ34 θ33 θ32 θ31 θ30 66.7 33.3 θ1 0.0 33.3 66.7 100.0 2-channel phase current ratio (%) Before switching the excitation mode Excitation mode Position Micro-step θ64 θ0 -θ1 Step position after the excitation mode is switched 256 divisions Micro-step θ63 to θ33 θ32 θ31 to θ1 θ0 1-2 phase 1-2 phase full torque 2 phase θ64 θ63 θ32 θ31 θ0 -θ1 θ64 θ63 θ32’ θ31 θ0 -θ1 θ32’ θ31 No.A1868-19/36 LV8414CS (2) Switching to the 1-2 phase excitation (1-2 phase excitation full torque) mode When operation has been switched from excitation mode to the 1-2 phase excitation (1-2 phase excitation full torque) mode, excitation position proceeds to position θ32 (θ32’) by the first pulse generated after the switching, and then operation transfers to the 1-2 phase excitation (1-2 phase excitation full torque) mode. However, if the position established before the excitation mode switching is θ32 (θ32’), excitation position proceeds to the next position in the 1-2 phase excitation (1-2 phase excitation full torque) mode by the first pulse generated after the switching. (3) Switching to the 2-phase excitation mode If, in the case of channel 1 to channel 4, operation has been switched from each excitation mode to the 2-phase excitation mode, excitation position proceeds to position θ32’ by the first pulse generated after the switching, and then to the next position in the 2-phase excitation mode. 1-channel phase current ratio (%) 100.0 θ64 θ63 θ62 θ32' (2 phase, 1-2 phase full torque) θ34 θ33 θ32 θ31 θ30 66.7 33.3 θ1 0.0 33.3 66.7 100.0 2-channel phase current ratio (%) Before switching the excitation mode θ0 -θ1 Step position after the excitation mode is switched Excitation mode Position 1-2 phase 1-2 phase full torque Micro-step θ64 θ32 θ32’ θ32’ θ63 to θ33 θ32 θ32’ θ32’ θ32’ 1-2 phase 1-2 phase full torque 2 phase 2 phase θ32 θ0 θ0 θ31 to θ1 θ32 θ32’ θ32’ θ0 -θ32’ -θ32’ -θ32’ θ64 θ32’ θ32’ θ32 θ0 θ32’ θ0 -θ32’ -θ32’ θ64 θ32 θ32’ θ32’ θ0 θ32’ θ0 -θ32 θ32’ θ0 -θ32’ θ0(θ0) No.A1868-20/36 LV8414CS 2 6. ENA pin function and I C serial data output enable setting [ENA pin] VCC consumption current during standby can be reduced to virtually zero by setting the ENA input pin to low. Furthermore, when this pin is set to low, the output becomes OFF state (high-impedance), and the state of the internal logic circuit is set to the initial excitation position (initial position). By setting the ENA pin to high, the output becomes ON state, and the circuit operates from the initial excitation position. ENA Output ON Output OFF Output ON CLK1 (CLK2) 100% I1 0% -100% High-impedance state 100% I2 Internal initial position 0% -100% I2C serial data communication enabled * The output does not operate unless “output enable” is set to the “output ON” state using an I2C serial data communication. [I2C serial data output enable setting] When “output enable” is set to the “output OFF” state, the output is placed in the high-impedance state at the rising edge of the 8th SCL bit in the data transmission. However, since the internal logic circuit is activated, the position number advances if CLK has been input. This means that when “output enable” is set to the “output ON” state after this, the output is set to ON at the rising edge of the 8th SCL bit in the data transmission, and that the output level at this time will be the level at the number to which the position has advanced by the CLK input. No.A1868-21/36 LV8414CS [Timing at which the output enable setting is reflected (output OFF)] The output enable setting is reflected at the rising edge of SCLK (8th bit of SCLK) of “D0” I2C Serial data output enable setting Output ON Output OFF ENA Output ON H CLK1 (CLK2) 100% I1 0% -100% High-impedance state 100% I2 0% -100% Expanded I2C Serial data output enable setting Output ON Output OFF CLK1 (CLK2) 100% I1 0% -100% High-impedance state 100% I2 0% -100% I2C Serial data reflect timing Start M S B Slave address L S B W A C K M S B Register address L S B A C K M S B Data L S B A C K Stop SCL SDA 1 1 1 0 0 1 0 0 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 No.A1868-22/36 LV8414CS [Timing at which the output enable setting is reflected (output ON)] I2C Serial data output enable setting Output ON Output OFF ENA Output ON H CLK1 (CLK2) 100% I1 0% -100% High-impedance state 100% I2 0% -100% Expanded I2C Serial data output enable setting Output OFF Output ON CLK1 (CLK2) 100% I1 0% -100% High-impedance state 100% I2 0% -100% I2C Serial data reflect timing Start M S B Slave address L S B W A C K M S B Register address L S B A C K M S B Data L S B A C K Stop SCL SDA 1 1 1 0 0 1 0 0 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 No.A1868-23/36 LV8414CS 2 7. FR pin function and I C serial data excitation direction setting [FR pin] Using the FR1 (FR2) forward/reverse rotation setting signal input pin, it is possible to switch the excitation direction between forward and reverse rotation. When FR is set to low, the clockwise (CW: forward rotation) direction is set; conversely, when it is set to high, the counterclockwise (CCW: reverse rotation) direction is set. In CW (forward rotation) mode, the channel 2 (channel 4) current phase is delayed by 90° relative to the channel 1 (channel 3) current. In CCW (reverse rotation) mode, the channel 2 (channel 4) current phase is advanced by 90° relative to the channel 1 (channel 3) current. FR1 (FR2) CW (forward rotation) setting ENA CCW (reverse rotation) setting H CLK1 (CLK2) 100% CW rotation ends. I1 CCW rotation starts. 0% -100% 100% I2 0% -100% [I2C serial data excitation direction setting] When the excitation (rotation) direction of the stepping motor is determined using the “excitation direction” setting, the output is switched to forward or reverse rotation at the rising edge of the 8th bit of SCL in the data transmission. In CW (forward rotation) mode, the channel 2 (channel 4) current phase is delayed by 90° relative to the channel 1 (channel 3) current. In CCW (reverse rotation) mode, the channel 2 (channel 4) current phase is advanced by 90° relative to the channel 1 (channel 3) current. * Since the FR1 (FR2) forward/reverse signal input pins are provided with an internal pull-down resistor, these pins are set to the low state when they are open. Furthermore, when these pins are set to low, the excitation direction setting established using an I2C serial data communication takes priority. Conversely, when they are set to high, the excitation direction is always set to “reverse rotation” regardless of the I2C communication setting. FR pin I 2C excitation direction setting Output L CCW (reverse rotation) reverse rotation direction H CCW (reverse rotation) reverse rotation direction L CW (forward rotation) forward rotation direction H CW (forward rotation) reverse rotation direction No.A1868-24/36 LV8414CS [Timing at which excitation direction setting is reflected (CW to CCW)] The excitation direction is set at the rising edge of SCLK (8th bit of SCLK) of “D0” and the setting is reflected starting with the next CLK. I2C Serial data excitation direction setting ENA CW (forward rotation) setting CCW (reverse rotation) setting H CLK1 (CLK2) 100% CW rotation ends. I1 CCW rotation starts. 0% -100% 100% I2 0% -100% Expanded I2C Serial data excitation direction setting CW (forward rotation) setting CCW (reverse rotation) setting CLK1 (CLK2) 100% CW rotation ends. I1 CCW rotation starts. 0% -100% 100% I2 0% -100% I2C Serial data reflect timing Start M S B Slave address L S B W A C K M S B Register address L S B A C K M S B Data L S B A C K Stop SCL SDA 1 1 1 0 0 1 0 0 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 No.A1868-25/36 LV8414CS 2 8. I C serial data Step/Hold setting logic CLK (external) Internal CLK logic Internal logic "Step/Hold" setting signal When the Step/Hold data is set to the Hold state, the state of the external clock signal (CLK) at that time is latched and held as the internal clock signal. Since the state of CLK (external) is low at the timing when step/hold is set for the first time as shown in the figure on the next page, the internal CLK is held in the low state. In contrast, at the timing with which Step/Hold is set to the Hold state for the second time, the internal clock signal will be held at the high level because the external clock (CLK) was at the high level. When Step/Hold is set to the Clear state, the internal clock is synchronized with the external clock (CLK). The output holds the state it was in at the point Step/Hold is set to the Hold state, and advances on the next clock signal rising edge after Step/Hold is set to the Clear state. As long as Step/Hold is in the Hold state, the position number does not advance even if an external clock (CLK) signal is applied. No.A1868-26/36 LV8414CS [Timing at which the step/hold setting is reflected (Clear to Hold)] The step/hold setting is reflected at the rising edge of SCLK (8th bit of SCLK) of “D0” I2C Serial data step/hold setting Clear Hold Clear ENA Hold Clear H CLK1 (CLK2) Held at low level Internal clock Held at high level 100% I1 0% -100% 100% I2 0% -100% Expanded I2C Serial data excitation direction setting CLK1 (CLK2) Clear Hold Internal clock 100% I1 0% -100% 100% I2 0% -100% I2C Serial data reflect timing Start M S B Slave address L S W B A C K M S B Register address L S B A C K M S B Data L A S C B K Stop SCL SDA 1 1 1 0 0 1 0 0 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 No.A1868-27/36 LV8414CS [Timing at which the step/hold setting is reflected (Hold to Clear)] I2C Serial data step/hold setting Clear Hold Clear ENA Hold Clear H CLK1 (CLK2) Held at low level Internal clock Held at high level 100% I1 0% -100% 100% I2 0% -100% Expanded I2C Serial data excitation direction setting CLK1 (CLK2) Hold Clear Internal clock 100% I1 0% -100% 100% I2 0% -100% I2C Serial data reflect timing Start M S B Slave address L S W B A C K M S B Register address L S B A C K M S B Data L A S C B K Stop SCL SDA 1 1 1 0 0 1 0 0 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 No.A1868-28/36 LV8414CS 2 9. I C serial data counter reset setting When “counter reset” setting is set to the “reset” state, the output is set to the default state (initial position) at the rising edge of the 8th SCL bit in the data transmission. When “counter reset” setting is then set to the “release” state, the position number of the output advances from the rising edge of the CLK signal following the rising edge of the 8th SCL bit in the data transmission. [Timing at which the counter reset setting is reflected (Clear to Reset)] The counter reset setting is reflected at the rising edge of SCLK (8th bit of SCLK) of “D0” I2C Serial data counter reset setting Clear Reset ENA Clear H CLK1 (CLK2) 100% I1 0% -100% Initial position 100% I2 Clear 0% -100% Expanded I2C Serial data counter reset setting Clear Reset CLK1 (CLK2) 100% I1 0% -100% Initial position 100% I2 0% -100% I2C Serial data reflect timing Start M S B Slave address L S W B A C K M S B Register address L S B A C K M S B Data L S B A C K Stop SCL SDA 1 1 1 0 0 1 0 0 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 No.A1868-29/36 LV8414CS [Timing at which the counter reset setting is reflected (Reset to Clear)] I2C Serial data counter reset setting Clear Reset ENA Clear H CLK1 (CLK2) 100% I1 0% -100% Initial position 100% I2 Clear 0% -100% Expanded I2C Serial data counter reset setting Reset Clear CLK1 (CLK2) 100% I1 0% -100% Initial position 100% I2 0% -100% I2C Serial data reflect timing Start M S B Slave address L S W B A C K M S B Register address L S B A C K M S B Data L S B A C K Stop SCL SDA 1 1 1 0 0 1 0 0 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 No.A1868-30/36 LV8414CS 2 10. Number of divisions (I C serial data frequency division setting) Since this IC provides 256-division (16W1-2 phase) micro-step drive, a 32kHz excitation step signal is required when driving a stepping motor at 1kHz if 1-2 phase excitation is to be used. I2C communication allows one of four ratios, namely, 1 (no frequency division), 1/2, 1/4, or 1/8 to be selected as the CLK frequency division ratio, so the motor speed can be set. [Timing at which CLK frequency division setting is reflected] The CLK frequency division is set at the rising edge of SCLK (8th bit of SCLK) of “D0” and the setting is reflected starting with the next CLK. I2C Serial data frequency division setting 1 (no frequency division) ENA CLK1 (CLK2) 1/2 setting H 100% I1 0% -100% 100% I2 0% -100% Expanded I2C Serial data frequency division setting 1 (no frequency division) 1/2 setting CLK1 (CLK2) 100% I1 0% -100% 100% I2 0% -100% I2C Serial data reflect timing Start M S B Slave address L A S W C B K M S B Register address L S B A C K M S B Data L S B A C K Stop SCL SDA 1 1 1 0 0 1 0 0 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 No.A1868-31/36 LV8414CS 11. Output current reference voltage I2C communication allows the voltage to be switched to one of 16 steps from 0.200V to 0.050V. This is effective for reducing power consumption when stepping motor holding current is supplied. The output current is determined from the internal reference voltage and the resistance value connected between the current-sense resistor connection pin (RF) and GND. The formula used to calculate the output current is given below. (Output constant current) = (Constant current reference voltage) ÷ (RF resistance value) Example: With a 0.200V internal reference voltage, 1.0Ω RF resistance and 100% current ratio Iout = 0.2V × 100% ÷ 1.0Ω = 200mA Output current reference voltage values for 1/2 channels and 3/4 channels are set as shown below. 1/2 channels setting Register address (A7 = “0”, A6 = “0”, A5 = “0”, A4 = “0”, A3 = “0”, A2 = “0”, A1 = “0”, A0 = “0”) 3/4 channels setting Register address (A7 = “0”, A6 = “0”, A5 = “0”, A4 = “0”, A3 = “0”, A2 = “0”, A1 = “0”, A0 = “1”) D3 D2 D1 D0 Current setting reference voltage 0 0 0 0 0.200V 0 0 0 1 0.190V 0 0 1 0 0.180V 0 0 1 1 0.170V 0 1 0 0 0.160V 0 1 0 1 0.150V 0 1 1 0 0.140V 0 1 1 1 0.130V 1 0 0 0 0.120V 1 0 0 1 0.110V 1 0 1 0 0.100V 1 0 1 1 0.090V 1 1 0 0 0.080V 1 1 0 1 0.070V 1 1 1 0 0.060V 1 1 1 1 0.050V No.A1868-32/36 LV8414CS [Timing at which current setting reference voltage is reflected] The current setting reference voltage is reflected at the rising edge of SCLK (8th bit of SCLK) of “D0” Example: With 1.0Ω for RF and 100% current ratio I2C Serial data current reference voltage setting 0.2V setting ENA H CLK1 (CLK2) L 0.1V setting Iout 200mA 100mA 0mA Expanded I2C Serial data current reference voltage setting 0.2V setting 0.1V setting Iout 200mA 100mA 0mA I2C Serial data reflect timing Start M S B Slave address L S B W A C K M S B Register address L S B A C K M S B Data L S B A C K Stop SCL SDA 1 1 1 0 0 1 0 0 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 No.A1868-33/36 LV8414CS 12. Current control operation specification [Sine wave increasing direction] CLK Set current Set current Coil current Forced CHARGE section fchop (Initial state: 400kHz) Current mode CHARGE SLOW FAST CHARGE SLOW FAST [Sine wave increasing direction] CLK Set current Coil current Forced CHARGE section Set current fchop (Initial state: 400kHz) Current mode CHARGE SLOW FAST Forced CHARGE section FAST CHARGE SLOW [Description of current limiting operation] In each current mode, the operation sequence is as described below : At rise of chopping frequency, the CHARGE mode begins. • The coil current (ICOIL) and setting current (IREF) are compared in the forced CHARGE section. When (ICOIL < IREF) existed in the forced CHARGE section: The CHARGE mode is established until ICOIL ≥ IREF. Then it is switched to the SLOW DECAY mode, and finally it is switched to the FAST DECAY mode. When (ICOIL < IREF) did not exist in the forced CHARGE section: The FAST DECAY mode begins. The coil current is attenuated in the FAST DECAY mode till one cycle of chopping is over. Above operations are repeated. Normally, the SLOW (+FAST) DECAY mode continues in the sine wave increasing direction, then entering the FAST DECAY mode till the current is attenuated to the set level and followed by the SLOW DECAY mode. VM VM VM ON OFF OFF OFF OFF ON OFF ON ON ON ON OFF (Charge mode) (Slow decay mode) (Fast decay mode) No.A1868-34/36 LV8414CS [Timing at which the chopping frequency setting is reflected (400kHz to 200kHz)] The frequency setting is reflected at the rising edge of SCLK (8th bit of SCLK) of “D0” I2C Serial data chopping frequency setting 400kHz setting 200kHz setting ENA H CLK1 (CLK2) 100% I1 0% -100% 100% I2 0% -100% Chopping frequency Expanded I2C Serial data division setting 400kHz setting 200kHz setting CLK1 (CLK2) 100% I1 0% -100% 100% I2 0% -100% Chopping frequency I2C Serial data reflect timing Start M S B Slave address L S B W A C K M S B Register address L S B A C K M S B Data L S B A C K Stop SCL SDA 1 1 1 0 0 1 0 0 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 No.A1868-35/36 LV8414CS SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. 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SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of December, 2010. Specifications and information herein are subject to change without notice. PS No.A1868-36/36