NJRC NJU6573

NJU6573
Preliminary
16COM x 100SEG 1/16 Duty BITMAP LCD Driver
! GENERAL DESCRIPTION
PACKAGE OUTLINE
The NJU6573 is a 16-common x 100-segment
bitmap LCD driver to display graphics or characters.
It incorporates 16 common driver circuits and 100
segment driver circuits. The NJU6573 can display
a 16 x 100 dots graphic or 2-line by 20-character
(5 x 7 dots per character).
In addition, the NJU6573’s useful functions meet
a wide range of applications.
NJU6573
! FEATURES
LCD driving circuit
Bias Ratio
Serial Data Transfer
Oscillator
: 16-common and 100-segment
: 1/5 bias
: Shift clock max. 2MHz
: CR oscillation with external resistor and capacitor, or
external oscillation signal input.
Programmable Contrast Control:16-steps Electrical Variable Resister (EVR)
Voltage Tripler and bleeder resistance on-chip.
Operating Voltage
: VDD=2.4~3.6V
C-MOS Technology
: Substrate : P
Package
: LQFP144 20.0mm x 20.0mm t=1.7mm(Max)
0.5mm pitch
Ver.2009-07-28
-1-
NJU6573
Preliminary
! BLOCK DIAGRAM
SEG0~
SEG0~SEG99
SEG99
COM0~
COM0~COM15
VDD
VDD
VSS
Chip
TESTIN2
VCI
C1P
C1N
V0
COM DRIVER
CIRCUIT(16)
CVON
CVOFF
V0
SVON
SEG DRIVER(100)
SVOFF
VDD
VDD
VOLTAGE
CONVERTER
VDD
VDD
C2P
LINE SELECT
COM CONTRORER
C2N
VDCOUT
DCOUT
VDCIN
VDD
VDD
VREF
REGULATORE
VDD
VREG
VREG
V0
V0
LCD
DRIVER
VOLTAGE
CIRCUIT
V1
V2
SVON
SVOFF
LATCH BLOCK(100x16)
CVON
V3
CVOFF
V4
VDD
VSS
OSCILLATOR
CIRCUIT
OSC
INHb
INHb
RSTb
RSTb
VDD
BOOST
LOGIC CIRCUIT
EXOSC
VDD
CSb
CSb
SCL
SCL
SI
VDD
IF
SERIAL DATA CLOCK
SHIFT REGISTER(105)
DISPLAY DATA
-2-
Ver.2009-07-28
NJU6573
Preliminary
109
110
SEG92
73 COM56
75
74
76
77
79
78
80
82
81
83
85
84
87
86
90
89
88
91
94
93
92
95
100
99
98
97
96
102
101
103
104
106
105
108 COM91
107
! PAD LOCATION
SEG55
72
71
112
70
69
113
114
68
67
111
115
66
116
SEG99
V4
117
118
V3
64
63
119
120
121
122
65
V2
62
V1
61
V0
60
59
VREG
VREF
N.C
123
124
NJU6573
VDCIN
VDCOUT
C2P
C2N
125
126
127
128
58
57
56
55
54
53
C1P
129
130
52
51
C1N
VCI
131
50
TESTIN
VSS
132
133
134
49
48
47
TESTIN2
BOOST
VDD
EXOSC
135
136
137
138
46
45
44
43
OSC
INHb
139
140
42
41
SI
CSb
RSTb
38
37
SEG19 36
33
32
30
31
29
27
28
26
24
25
22
23
19
20
21
18
17
SEG0
COM15 16
14
15
13
11
12
10
8
9
6
7
3
4
5
COM0
Ver.2009-07-28
34
35
SEG20
TESTOUT
1
143
144
40
39
SCL
2
141
142
-3-
NJU6573
Preliminary
! TERMINAL DISCRIPTION
No.
136
Pad Name
VDD
131
122
123
VCI
Booster voltage input terminal(MAX:3.3V)
Voltage Regulator Output
Regulator base voltage input terminal for VREG output (MAX:3.3V)
Display ON or OFF “High”=Display ON, “Low”=Display OFF,
Voltage Regulator Input
Booster voltage output terminal (Internal Booster Circuit Output Terminal)
139
125
126
121
120
119
118
117
133
129
130
127
128
VREG
VREF
INHb
VDCIN
VDCOUT
V0
V1
V2
V3
V4
VSS
C1P
C1N
C2P
C2N
143
RSTb
142
CSb
140
SI
141
SCL
138
137
OSC
EXOSC
1-16
COM0-COM15
Common Driver Outputs
17-116
SEG0-SEG99
Segment Driver Outputs
135
-4-
Function
Power Supply: (2.4V-3.6V)
BOOST
Bias
V0≥ V1 ≥ V2≥ V3≥ V4≥ VSS
GND Terminal VSS =0V
Capacitor Connect Terminal for Voltage Booster
Reset
When RSTb is “Low”, Latch Circuit is Reset.
Chip Select
When CSb is “Low”, Data can be read in.
Serial Data Input Terminal
Serial Clock Input Terminal (Max: 2MHz)
OSC: External Resistor and Capacitor Connect Terminal for CR Oscillation, or External
Clock Input Terminal.
EXOSC: “High”=External Clock Input, “Low”=CR Connect,
Voltage Booster ON or OFF
“High”=Voltage Booster ON, “Low”=Voltage Booster OFF,
BOOST
Internal Booster
Internal Regulator
Circuit
L
OFF
OFF
H
ON
ON
132
TESTIN
134
TESTIN2
Test Terminal (Keep TESTIN-Vss short)
Test2 Terminal (Keep TESTIN2-Vss short)
144
TESTOUT
Test Out Terminal(There is open Terminal electrically)
124
N.C.
There is open Terminal electrically
Ver.2009-07-28
NJU6573
Preliminary
! FUNCTION DESCRIPTION
(1) Shift Resister
105 bits resister
(2) Latch Circuit
Data stored in display data register is assigned to the corresponding SEG/port.
(3) Segment Driver
Basing on display data, segment drivers output LCD SEG driving signal.
(4) Common Driver
Common drivers output LCD COM driving signal.
(5)
Voltage Booster
NJU6573 with a built-in Voltage Booster. The internal voltage booster generates up to 3xVCI voltage(Input:VCI
Terminal, Output: VDCOUT Terminal). The boost voltage VDCOUT must not exceed 10.0V(VCIx3≤ 10V),
otherwise the voltage stress may case a permanent damage to the LSI. When using the internal LCD power
supply, connect the VDCOUT and the VDCIN.
The VREF voltage is tripled to obtain the VREG voltage.(VREFx3=VREG)
Ver.2009-07-28
-5-
NJU6573
Preliminary
(5) Bleeder Resistance
Each LCD driving voltage (V1, V2, V3, V4) is LCD driving high voltage input to the V0 Terminal, generated by
the E.V.R and high impedance bleeder resistance.
LCD driving voltage generation circuit generates LCD driving bias voltages V0, V1, V2, V3 and V4. VREG, V0, V1,
V2, V3 and V4 terminals requires external capacitors for bias voltage stabilization for display quality. These
values of capacitors should be fixed in accordance with evaluation in the application.
LCD Driving Voltage vs Duty Ratio
Duty Ratio
1/16
Power supply
Bias
1/5
VLCD
V0- VSS
VDCOUT
VLCD is the maximum amplitude
for LCD driving voltage.
From Voltage booster
Internal NJU6573
VDCIN
VREF
Regulator
VREG
E.V.R(16Steps)
0~11.25KΩ
V0
V0
4KΩ
V1
V1
4KΩ
V2
V2
4KΩ
V3
V3
VLCD
4KΩ
V4
V4
4KΩ
Vss
Vss
Fig Bleeder Resistance
-6-
Ver.2009-07-28
NJU6573
Preliminary
(6) Oscillator circuit
The oscillator consists of an external capacitor and an resistor. It generates clock signal for LCD driving.
When use external clock, input the clock signal to OSC.(EXOSC Terminal is “High” when use external clock)
VDD
NJU6573
200KΩ
(fOSC=30.8kHz TYP)
OSC
100pF
Fig OSC Circuit
(6-1) Relation between Oscillation frequency and Frame frequency
Frame frequency = fosc / 384
Set the oscillation frequency to obtain the frame frequency.
Ver.2009-07-28
-7-
NJU6573
Preliminary
(7)
Input Data Format and Timing
Data format is shown below.
When the CSb terminal goes to “L” at SCL terminal “H”, I/F is data input. Data fetched at SCL rising edge.
In case of entering less then 105-bit data(Display Data:100bit, COM select data:4bit,E.V.R set data:1bit),
Malfunction. In case of entering over then 105-bit data, valid data is last 105-bit data.
EVR:The Bit set E.V.R or COM
“L”: COM select data
“H”: E.V.R. select data
(7-1) 1/16Duty
Data1
CSb
SCL
SI
D1
D2
D3
D99
D100
0
0
Display Data(1-100)
0
0
EVR
COM0 select data
EVR set
Data2
CSb
SCL
SI
D101
D102
D103
D199
D200
0
0
1
EVR
EVR set
COM1 select data
Display Data(101-200)
Data3
Data3
0
CSb
SCL
SI
D201
D202
D203
D299
D300
0
1
0
EVR
COM2 select data
Display Data(201-300)
Data4
0
EVR set
CSb
SCL
SI
D301
D302
D303
D399
0
D400
Display Data(301-400)
0
1
1
COM3 select data
EVR
EVR set
Data16
Data16
CSb
SCL
SI
D1501
D1502
D1503
D1599
Display Data(1501-1600)
-8-
D1600
1
1
1
COM15 select data
1
EVR
EVR set
Ver.2009-07-28
NJU6573
Preliminary
CSb
SCL
SI
108
107
106
105
Before CSb are
raised, data on
106 bits and more.
(Invalid)
104
103
4
3
2
1
Before CSb are raised, data on 105 bits.(valid)
Fig In case of entering over then 105-bit data
(7-2) Display OFF (INHb)
When INHb is "H", display is ON, and when INHb is "L", display is off.
When INHb=”L”
All segment and common terminal output Vss
(7-3) Voltage Booster Circuit Select (BOOST terminal)
Voltage Booster ON or OFF
BOOST
Voltage Booster Circuit
Regulator Circuit
VLCD operation supply
H
ON
ON
Internal Booster Circuit
using
L
OFF
OFF
External VLCD power supply Input
(7-4) Reset(RSTb)
When RSTb is “Low", latch circuit is reset.
But, Display ON/OFF can not be reset (control).
(7-5) Supply Voltage Sequence
Supply voltage ON
Display OFF(INHb=”L”)
Reset
(Over 1.3msec RSTb=”L”)
Display Data write
Wait time: 100msec
Display ON (INHb=”H”)
Fig
Ver.2009-07-28
Supply Voltage Sequence
-9-
NJU6573
Preliminary
(8) Instructions
The NJU6573 incorporates E.V.R register(high). Instruction code as show below.
Table. Table of Instructions
Instruction
Explanation
When the CSb terminal rising edge eve one bit is High, Data fetched at
SCL rising edge.
In case of entering less then 2-5bit data valid.
Electrical Voltage Resistor
CSb
EVR set
SCL
SI
*
*
*
*
*
C3
*: Even only 5 clock can set E.V.R if the last bit is "1".
C2
C1
C0
1
*:Don’t care
Contrast Control instruction which adjusts the contrast of the LCD is executed when the code "1" is
written into EVR and the codes of C3 to C0 are written into 2 to 5bit as shown below.
The contrast of LCD can be adjusted one of 16 voltage-stages by setting this 4-bit register.
See below "how to adjust the Contrast of LCD".
Set the binary code "1,1,1,1" when contrast adjustment is unused.
C3
C2
C1
C0
VLCD voltage (Spec)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
VOUT x 0.640
VOUT x 0.656
VOUT x 0.672
VOUT x 0.690
VOUT x 0.708
VOUT x 0.727
VOUT x 0.748
VOUT x 0.769
VOUT x 0.792
VOUT x 0.816
VOUT x 0.842
VOUT x 0.870
VOUT x 0.899
VOUT x 0.930
VOUT x 0.964
VOUT x 1.000
Ex.) VLCD voltage by
VOUT=8.4V
5.376
5.508
5.647
5.793
5.947
6.109
6.280
6.462
6.653
6.857
7.074
7.304
7.551
7.814
8.096
8.400
VLCD=VREG x 20 / (31.25-0.75 x M)
M: Contrast control resistor = 0-15
- 10 -
Ver.2009-07-28
NJU6573
Preliminary
•
Input Data v.s output
COM
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
↓
SEG89
SEG90
SEG91
SEG92
SEG93
SEG95
SEG96
SEG97
SEG98
SEG99
Ver.2009-07-28
COM0
0000
COM1
0001
D101
D102
D103
D104
D105
D106
D107
D108
D109
D110
COM2
0010
D201
D202
D203
D204
D205
D206
D207
D208
D209
D210
COM3
0011
D301
D302
D303
D304
D305
D306
D307
D308
D309
D310
↓
↓
↓
↓
D91
D92
D93
D94
D95
D96
D97
D98
D99
D100
D191
D192
D193
D194
D195
D196
D197
D198
D199
D200
D291
D292
D293
D294
D295
D296
D297
D298
D299
D300
D391
D392
D393
D394
D395
D396
D397
D398
D399
D400
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
COM12
1100
D1201
D1202
D1203
D1204
D1205
D1206
D1207
D1208
D1209
D1210
COM13
1101
D1301
D1302
D1303
D1304
D1305
D1306
D1307
D1308
D1309
D1310
COM14
1110
D1401
D1402
D1403
D1404
D1405
D1406
D1407
D1408
D1409
D1410
COM15
1111
D1501
D1502
D1503
D1504
D1505
D1506
D1507
D1508
D1509
D1510
↓
↓
↓
↓
D1291
D1292
D1293
D1294
D1295
D1296
D1297
D1298
D1299
D1300
D1391
D1392
D1393
D1394
D1395
D1396
D1397
D1398
D1399
D1400
D1491
D1492
D1493
D1494
D1495
D1496
D1497
D1498
D1499
D1500
D1591
D1592
D1593
D1594
D1595
D1596
D1597
D1598
D1599
D1600
- 11 -
NJU6573
Preliminary
! ABSOLUTE MAXIMAM RATINGS
PARAMETER
Supply Voltage 1
Supply Voltage 2
Supply Voltage 3
Input Voltage
Operating Temp.
Storage Temp.
SYMBOL
VDD,VREF
VCI
VDCIN, V0
V1~V4,VREG
RATINGS
-0.3 ~ +7.0
-0.3 ~ +10.5
UNIT
V
V
-0.3 ~ +10.5
V
Vt
-0.3 ~ VDD+0.3
V
Topr
Tstg
-40 ~ +105
-55 ~ +125
°C
°C
(VSS=0V, Ta=25°C)
CONDITIONS
VCI Terminal Note-4)
VDCIN, V0, V1~V4 ,VREG Terminal
INHb, CSb, SCL, SI, RSTb, OSC, BOOST
EXOSC,TESTIN,TEST2, applicable.
The power dissipation is value mounted on 4
layer glass
PD
1000
mW
epoxy board in size 76.2mm x 114.3mm x
1.6tmm
Do not exceed the absolute maximum ratings, otherwise the stress may cause a permanent damage to
the IC. It is also recommended that the IC be used within the range specified in the DC electrical
characteristics, or the electrical stress may cause mulfunctions and impact on the reliability.
To stabilize the LSI operation, place decoupling capacitors between VDD-VSS, VCI-VSS and between
VDCIN-VSS.
All voltages are relative to VSS = 0V reference.The following relationship shall be maintained.
VDCIN ≥V0 ≥VDD>VSS, and VSS =0V
When voltage booster circuit, need condition of 10V ≥ VCIx3.
Dissipation
Power
Note-1)
Note-2)
Note-3)
Note-4)
- 12 -
Ver.2009-07-28
NJU6573
Preliminary
ELECTRICAL CHARACTERISTICS
•
DC characteristics
SYMBOL
PARAMETER
Power Supply 1
Power Supply 2
Power Supply 3
VDD
VCI
VDCIN
VIH1
Input voltage 1
VIL1
Driver-on(COM)
Resistance
Driver-on(SEG)
Resistance
Input leakage
current
Operating Current
LCD operating
voltage
Bleeder resistance
RB=V0/IB
RB: Bleeder
resistance 5
IB: Bleeder
resistance
Current
RCOM
RSEG
ILI
Terminal
VDD
VCI
VDCIN
CSb, SCL,
SI, RSTb,
OSC,BOOST
INHb,
EXOSC
COM0COM15
SEG0SEG99
CSb, SCL,
RSTb, INHb,
BOOST,
EXOSC
IDD1
VDD
ICI
VCI
IDD1
ICI
V0
V1
V2
V3
V4
VDD
VCI
V0
V1
V2
V3
V4
RB
VREG
Booster output
voltage
VOUT
VDCOUT
OSC Frequency
fOSC
OSC
External clock
Operating
Frequency
Operate Frame
Frequency range
VREF input voltage
Regulator output
voltage
fCP
OSC
Fr
COM
VREF
VREF
VREG
VREG
Dropout Voltage
Delta VIO
VDCIN-VREG
VDCIN Current
IOUT
VDCIN
Ver.2009-07-28
CONDITIONS
(VDD=2.4 to 3.6V, VSS=0V, Ta=-40 to +105°C)
MIN
TYP
MAX
UNIT Note
2.4
3.6
V
2.4
3.3
V
5
3.6
10.0
6
±Id=1µA(COM Terminal)
VO=V0,VSS, V1,V4
±Id=1µA(SEG Terminal)
VO=V0,VSS, V2,V3
VIN=0~VDD
VDD=VCI=3V, VREF=2.7V,
fosc=30.8kHz,
Checker Display ON,
Booster ON, Ta=25°C
E.V.R: “1111”
SEG/COM open
VDCOUT/VDCIN connect
fOSC=184.8kHz
Other condition same as IDD1
VREG =8.0V
E.V.R: “1111”
VREG =8.0V
E.V.R: “1111”, Ta=25°C
VCI=3.3V, Ta=25°C
fOSC=30.8k-184.8kHz,
BoosterON(COM/SEGopen)
VDCOUT between VDCIN
connect
VDD =3V, Ta=25°C,
ROSC= 200kOhm
COSC= 100pF
ROSC= 30kOhm
Other condition same as fOSC
External input
VDCIN =10V, VREF=3V,
(COM/SEG open)
VDCIN=9V, VREF=3.6V,
IO=-200µA
VDCIN=9.0V, VREF=2.7V
E.V.R: “1111”, INHb=0
Ta=25°C (COM/SEG open)
0.8 VDD
-
VDD
V
VSS
-
0.2 VDD
V
-
-
20
kOhm
7
-
-
20
kOhm
7
-1.0
-
1.0
µA
-
30
50
µA
-
1.5
2.0
mA
7.8
6.2
4.6
3.0
1.4
90
1.7
6.4
4.8
3.2
1.6
150
2.2
8.0
6.6
5.0
3.4
1.8
µA
mA
14.0
20.0
26.0
kOhm
9.0
9.5
-
V
25.3
30.8
36.3
8
8
V
kHz
151.8
184.8
217.8
25.3
-
217.8
kHz
66
-
566
Hz
1.0
VREF x
3 x 0.98
VREF x
3
VDD
VREF x
3 x 1.02
V
-
0.05
0.10
V
-
0.5
0.8
mA
V
- 13 -
9
NJU6573
Preliminary
Note-5) When voltage booster circuit using, need condition of VDCOUT≤10V
Note-6) Condition of VDCIN Voltage: 10V≥VDCIN≥VREF x 3+ 0.6
Note-7) Driver-On resistance (RSEG/RCOM) is measured from V0, VSS, V1 , V2 , V3 or V4 terminal to each
SEG/COM terminal when Id current flows through COM/SEG terminals.
3V
NJU6573
A
VDD
Vss
Note-8) If input voltage is outside of the spec, when operating current increase. Input level must be
condition “H” or “L”. This mesurement condition is SI terminal between VDD short.
Note-9) Frame frequency vs OSC is as the show relation between oscillation frequency and Frame
frequency page7.
Example characteristic)
Condition
C=100[pF]
R=from 27k[ohm] to 200k[ohm]
Temperature=25[°C]
The following graph is the data of example sample, so without guarantee.
fosc vs Resistance (C=100pF)
fosc [kHz]
VDD=3V, Ta=25℃
220
210
200
190
180
170
160
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200
Resistance [kohm]
- 14 -
Ver.2009-07-28
NJU6573
Preliminary
•
AC characteristics
PARAMETER
"L" Level Clock Pulse Width
"H" Level Clock Pulse
Width
Data Setup Time
Data Hold Time
CSb Setup Time
CSb Hold Time
CSb"H" Level Pulse Width
Rising Time
Falling Time
•
SYMBOL
tWCLL
(VDD=V0=2.4 to 3.6V, VSS=0V, Ta=-40 to +105°C)
CONDITIONS
MIN
TYP
MAX
UNIT Note
230
ns
tWCLH
230
-
-
ns
tDS
tDH
tCS
tCH
30
30
50
50
250
-
-
20
20
ns
ns
ns
ns
ns
ns
ns
tWCH
tr
tf
Input Timing
tWCH
CSb
tCS
tWCLH
tWCLL
tf
tCH
tr
SCL
tDS
tDH
SI
•
Input condition when hardware reset circuit is used
PARAMETER
Reset Input “L” Level Width
SYMBOL
tRSL
Reset Rising Time
Reset Falling Time
CONDITIONS
fOSC=30.8kHz±18%
fOSC=184.8kHz±18%
trRS
tfRS
tfRS
tRSL
MIN
1.3
0.3
-
TYP
-
(Ta=-40 to +105°C)
MAX
UNIT
ms
ms
100
ns
100
ns
trRS
VIH
RSTb
VIL
Ver.2009-07-28
- 15 -
NJU6573
Preliminary
LCD Operating Wave Form
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM15
SEG
1
COM0
COM1
COM2
COM3
SEG0
SEG1
- 16 -
2
0 1 2 3 4
3
4
・・・・
15 16
1
2
3
4
・・・・
15 16
1
2
3
V0
V1
V2
V3
V4
VSS
V0
V1
V2
V3
V4
VSS
V0
V1
V2
V3
V4
VSS
•
•
•
•
•
•
•
•
V0
V1
V2
V3
V4
VSS
V0
V1
V2
V3
V4
VSS
V0
V1
V2
V3
V4
VSS
Ver.2009-07-28
NJU6573
Preliminary
■
Input and Output Circuit
VDD
VDD
IN
IN
VSS
VSS
RSTb, CSb, SI,SCL
OSC, EXOSC, INHb, TESTIN, BOOST, TESTIN2
V0
Vss
OUT
V0
Vss
SEG0~SEG99, COM0~COM15
Ver.2009-07-28
- 17 -
NJU6573
Preliminary
■
APPLICATION CIRCUIT
1)Circuit1
Booster ON, Internal OSC
VDD
C1
VCI
VDD
VSS
VCI (VCI ×3 ≦ 10V)
C2
VREF (VREF ×3 ≦ (VDCIN-0.1V) )
C1P
C3
C4
C1N
C2P
C5
C6
C7
C8
C9
C10
C11
C12
VDD
VDCIN
VREG
V0
V1
V2
V3
V4
NJU6573
C2N
VDCOUT
BOOST
TESTIN, TESTIN2
EXOSC
R1
C13
CPU
OSC
RSTb
INHb
CSb
SI
SCL
Reference value
R1
C13
C4,5,6,7
C1-C3,C8-C12
- 18 -
200kΩ
100pF
1.0-4.7μF
0.1-1.0μF
Ver.2009-07-28
NJU6573
Preliminary
2)Circuit 2
Booster OFF, Regulator OFF (External power supply mode), External OSC
VDD
VDD
VSS
C1
VCI
VREF
C1P
C1N
C2P
C2
VREG ≦ 10V
C3
C4
C5
C6
C7
VDD
VDCIN
VREG
V0
V1
V2
V3
V4
NJU6573
C2N
VDCOUT
BOOST
TESTIN, TESTIN2
EXOSC
OSC
CPU
RSTb
INHb
CSb
SI
SCL
Reference value
C2
1.0-4.7μF
C1,C3-C7 0.1-1.0μF
Ver.2009-07-28
- 19 -
NJU6573
Preliminary
3)Circuit3
Booster OFF, Regulator ON, External OSC
VDD
VDD
VSS
C1
VCI
VREF
C1P
C2
C1N
C2P
C3
VDCIN ≦ 10V
C4
C5
C6
C7
C8
C9
VDD
VDCIN
VREG
V0
V1
V2
V3
V4
NJU6573
C2N
VDCOUT
BOOST
TESTIN, TESTIN2
EXOSC
OSC
CPU
RSTb
INHb
CSb
SI
SCL
Reference value
C3,4
1.0-4.7μF
C1,C2-C9 0.1-1.0μF
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
- 20 -
Ver.2009-07-28