Ordering number : ENA1626
Bi-CMOS IC
For Digital Still Cameras
LV8048CS
Single-chip motor driver IC for
Overview
LV8048CS is single-chip motor driver IC for digital still cameras.
Features
• The actuator driver for DSC is built into single-chip.
• Two 256-division microstep output channel, and two constant current output channels
• All actuators can be driven at the same time
• AF / ZOOM stepping motor is driven by the clock signal
• Supports PWM control of a DC zoom motor
• The constant current output reference voltage can be set to one of 16 internal reference voltage levels (motor holding
current switching possible).
• Two photosensor drive transistor channels
• Two Schmitt buffer channels (the presence or absence of hysteresis can be set individually).
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
Unit
Supply voltage 1
VB max
6.0
V
Supply voltage 2
VCC max
6.0
V
Peak output curren t
IO peak1
800
mA
600
mA
OUT5 to 6, OUT9 to 10
(t ≤ 10ms, ON-duty ≤ 20%)
IO peak2
OUT1 to 4, OUT7 to 8, OUT11 to 12
(t ≤ 10ms, ON-duty ≤ 20%)
Continuous output current
IO max1
OUT5 to 6, OUT9 to 10
600
mA
IO max2
OUT1 to 4, OUT7 to 8, OUT11 to 12
400
mA
IO max3
PI1, PI2
40
mA
Continued on next page.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer' s products or
equipment.
D2409 SY 20091110-S00001 No.A1626-1/28
LV8048CS
Continued from preceding page.
Parameter
Symbol
Allowable power dissipation
Pd max
Conditions
Ratings
Mounted on a circuit board*
Unit
1100
mW
Operating temperature
Topr
-20 to +85
°C
Storage temperature
Tstg
-55 to +150
°C
* Specified circuit board :
40×50×0.8mm3
: glass epoxy four-layer board(2S-2P).
Recommended Operating Conditions at Ta = 25°C
Parameter
Symbol
Supply voltage range 1
VB
Supply voltage range 2
VCC
Logic level input voltage
Conditions
Ratings
Unit
VB1, VB2 (*1) (*2)
2.7 to 5.5
V
(*2)
2.7 to 5.5
V
VIN
0 to VCC+0.3
Clock frequency
FCLK
CLK1, CLK2/PWM, CLK3/ENA6
PWM frequency
FPWM
CLK2/PWM
V
to 64
kHz
to 100
kHz
(*1) There are no restrictions on the magnitude relationships between the voltages applied to VB1 and VB2.
(*2) There are no restrictions on the magnitude relationships between the voltages applied to each VB and VCC.
Electrical Characteristics at Ta = 25°C, VB = 5V, VCC = 3.3V
Parameter
Quiescent current
Symbol
ICCO
Conditions
Ratings
min
typ
Unit
max
ST = low, BI1, BI2 = low
1
μA
Current drain 1
IB
ST = high, BI1, BI2 = low, With no output load
75
150
μA
Current drain 2
ICC
ST = high, BI1, BI2 = low, With no output load
2.5
4
mA
VCC low-voltage cutoff voltage
VthVCC
2.1
2.4
2.6
V
Low-voltage hysteresis voltage
VthHYS
90
140
190
mV
Thermal shutdown temperature
TSD
Design target value
160
180
200
°C
ΔTSD
Design target value
20
40
60
°C
Thermal hysteresis width
AF/ZOOM Motor Drivers (OUT1-2, OUT3-4, OUT5-6, OUT7-8)
Output on-resistance 1
Ronu1
IO = 200mA, High side on-resistance
0.6
0.85
Ω
Rond1
IO = 200mA, Low side on-resistance
0.25
0.4
Ω
1
μA
0.7
0.9
1.2
V
Fchop1
293
390
488
kHz
Fchop2
146
195
244
kHz
Fchop3
428
570
713
kHz
Fchop4
214
285
356
kHz
VSEN00
0.185
0.200
0.215
V
VSEN01
0.125
0.140
0.155
V
VSEN10
0.085
0.100
0.115
V
0.045
0.060
0.075
V
1.0
μA
50
μA
Output leakage current 1
IOleak1
Diode forward voltage 1
VD1
Chopping frequency
Current setting reference voltage
ID = -400mA
VSEN11
Logic pin input current
IINL
VIN = 0V (ST, CLK1, CLK2/PWM)
IINH
VIN = 3.3V (ST, CLK1, CLK2/PWM)
High-level input voltage
VINH
ST, CLK1, CLK2/PWM
Low-level input voltage
VINL
ST, CLK1, CLK2/PWM
33
2.5
V
1.0
V
Ω
Motor driver for aperture, shutter (OUT9-10, OUT11-12)
Output on-resistance 2
Ronu2
IO = 200mA, High side on-resistance
0.6
0.85
Rond2
IO = 200mA, Low side on-resistance
0.25
0.4
Ω
Output leakage current 2
IOleak2
1
μA
Diode forward voltage 2
VD2
1.2
V
Constant current output
IO
210
mA
ID = -400mA
0.7
0.9
Rf = 1Ω, (D3, D4, D5, D6) = (0, 0, 0, 0)
190
200
Continued on next page.
No.A1626-2/28
LV8048CS
Continued from preceding page.
Parameter
Symbol
Conditions
Ratings
min
typ
max
Unit
Internal current setting
VREF1
(D3, D4, D5, D6) = (0, 0, 0, 0)
0.190
0.200
0.210
V
reference voltages
VREF2
(D3, D4, D5, D6) = (1, 0, 0, 0)
0.162
0.170
0.179
V
VREF3
(D3, D4, D5, D6) = (0, 1, 0, 0)
0.157
0.165
0.173
V
VREF4
(D3, D4, D5, D6) = (1, 1, 0, 0)
0.152
0.160
0.168
V
VREF5
(D3, D4, D5, D6) = (0, 0, 1, 0)
0.147
0.155
0.163
V
VREF6
(D3, D4, D5, D6) = (1, 0, 1, 0)
0.143
0.150
0.158
V
VREF7
(D3, D4, D5, D6) = (0, 1, 1, 0)
0.138
0.145
0.152
V
VREF8
(D3, D4, D5, D6) = (1, 1, 1, 0)
0.133
0.140
0.147
V
VREF9
(D3, D4, D5, D6) = (0, 0, 0, 1)
0.128
0.135
0.142
V
VREF10
(D3, D4, D5, D6) = (1, 0, 0, 1)
0.124
0.130
0.137
V
VREF11
(D3, D4, D5, D6) = (0, 1, 0, 1)
0.119
0.125
0.131
V
VREF12
(D3, D4, D5, D6) = (1, 1, 0, 1)
0.114
0.120
0.126
V
VREF13
(D3, D4, D5, D6) = (0, 0, 1, 1)
0.109
0.115
0.121
V
VREF14
(D3, D4, D5, D6) = (1, 0, 1, 1)
0.105
0.110
0.116
V
VREF15
(D3, D4, D5, D6) = (0, 1, 1, 1)
0.100
0.105
0.110
V
VREF16
(D3, D4, D5, D6) = (1, 1, 1, 1)
0.095
0.100
0.105
V
1.0
μA
50
μA
1.0
V
Motor holding drive switching rate
Rhold
Logic pin input current
33
IINL
VIN = 0V (CLK3/ENA6)
IINH
VIN = 3.3V (CLK3/ENA6)
High-level input voltage
VINH
CLK3/ENA6
Low-level input voltage
VINL
CLK3/ENA6
33
%
2.5
V
Photosensor peripheral circuits (PI1, PI2, BI1, BO1, BI2, BO2)
Output on-resistance 3
Output leakage current 3
Schmitt buffer threshold level
(hysteresis)
Schmitt buffer hysteresis
Schmitt buffer threshold level
Ron3a
IO = 20mA, PI1, PI2
2.4
5
Ω
Ron3b
IO = 40mA, PI1, PI2
2.4
5
Ω
IOleak3
PI1, PI2
1
μA
1.28
1.50
V
V
VthH
1.00
VthL
0.60
0.84
1.10
Vthhys1
0.3
0.44
0.6
V
Vth
0.90
1.20
1.40
V
1.0
μA
50
μA
(no hysteresis)
Serial Data Transfer Pins
Logic pin input current
IINL
VIN = 0V (SCLK, DATA, STB)
IINH
VIN = 3.3V (SCLK, DATA, STB)
High-level input voltage
VINH
SCLK, DATA, STB
Low-level input voltage
VINL
SCLK, DATA, STB
Minimum SCLK high-level pulse width
Tsch
0.125
μS
Minimum SCLK low-level pulse width
Tscl
0.125
μS
Stipulated STB time
Tlat
0.125
μS
33
2.5
V
1.0
V
Tlatw
0.125
μS
Data setup time
Tds
0.125
μS
Data hold time
Tdh
0.125
Maximum CLK frequency
Fclk
Minimum STB pulse width
μS
4
MHz
Fclk
Tsch
Tscl
SCLK
Tds Tdh
DATA
D0
D1
D2
D7
D8
Tlat
STB
Tlatw
No.A1626-3/28
LV8048CS
Package Dimensions
unit : mm (typ)
3389
TOP VIEW
SIDE VIEW
BOTTOM VIEW
F E D C B A
2.47
0.4
5
4
3 2
1
0.175
0.245
SANYO : WLP36(2.87X2.47)
Pd max -- Ta
1.6
Allowable power dissipation, Pd max -- W
6
0.65 MAX
7
SIDE VIEW
0.235
0.4
0.235
2.87
Specified substrate: 40×50×0.8mm3
glass epoxy four-layer board.
1.2
1.10
0.8
0.57
0.4
0
-20
0
20
40
60
80 85
100
Ambient temperature, Ta -- °C
Pin Assignment
Bottom View
Top View
F
RF3
OUT6
OUT7
RF4
OUT8
OUT11
RF6
RF6
OUT11
OUT8
RF4
OUT7
OUT6
RF3
F
E
OUT5
PI1
PI2
BO1
BI1
BI2
OUT12
OUT12
BI2
BI1
BO1
PI2
PI1
OUT5
E
D
VB2
SCLK
BO2
SGND
SGND
BO2
SCLK
VB2
D
C
VB1
DATA
VCC
PGND
PGND
VCC
DATA
VB1
C
B
OUT9
STB
ST
CLK1
CLK2
/PWM
CLK3
/ENA6
OUT2
OUT2
CLK3
/ENA6
CLK2
/PWM
CLK1
ST
STB
OUT9
B
A
RF5
OUT10
OUT3
RF2
OUT4
OUT1
RF1
RF1
OUT1
OUT4
RF2
OUT3
OUT10
RF5
A
1
2
3
4
5
5
4
3
2
1
6
7
7
6
No.A1626-4/28
+
-
+
-
VCC
VB1 OUT1
+
OUT3
Reference voltage circuit
Thermal protection circuit
ST
Excitation signal generation
circuit (microstep, 1-2 phase,
1-2 phase full torque or
2 phase mode)
Oscillation circuit
RF2
Current selection
(microstep, 1-2 phase,
1-2 phase full torque or
2 phase mode)
+
OUT4
Microstep
Output control logic
OUT2
Current selection
(microstep, 1-2 phase,
1-2 phase full torque or
2 phase mode)
SGND
RF1
Microstep
CLK1
VB2 OUT5
+
SCLK
CPU
DATA
STB
Serial-parallel converter
(9 bits)
Excitation signal generation
circuit (microstep, 1-2 phase,
1-2 phase full torque or
2 phase mode)
CLK2
/PWM
OUT7
RF4
CLK3
/ENA6
Current selection
(microstep, 1-2 phase,
1-2 phase full torque or
2 phase mode)
+
OUT8
Microstep
Output control logic
OUT6
Current selection
(microstep, 1-2 phase,
1-2 phase full torque or
2 phase mode)
RF3
Microstep
OUT9
OUT10
RF5
PI1
PI2
40mA max
OUT11
VCC
BI1 BO1
OUT12
BI2 BO2
RF6
to an ASIC
PGND
Reference voltage
selection
(0.1 to 0.2V in 16 steps)
+
Logic/pre-drive circuit
VB2
Constant current
Reference voltage
selection
(0.1 to 0.2V in 16 steps)
40mA max
Excitation signal
generator
(2 phase/1-2 phase)
+
Logic/pre-drive circuit
VB1
Constant current
LV8048CS
Block Diagram
No.A1626-5/28
LV8048CS
Pin Functions
Pin No.
Pin name
Description
C1
VB1
Power supply for OUT1-4, OUT9-10
D1
VB2
Power supply for OUT5-8, OUT11-12
C7
PGND
Power system ground
C6
VCC
Control system power supply
D7
SGND
Control system ground
A6
OUT1
Motor driver output
B7
OUT2
Motor driver output
A3
OUT3
Motor driver output
A5
OUT4
Motor driver output
E1
OUT5
Motor driver output
F2
OUT6
Motor driver output
F3
OUT7
Motor driver output
F5
OUT8
Motor driver output
B1
OUT9
Motor driver output
A2
OUT10
Motor driver output
F6
OUT11
Motor driver output
E7
OUT12
Motor driver output
A7
RF1
Current detection connection for OUT1-2
A4
RF2
Current detection connection for OUT3-4
F1
RF3
Current detection connection for OUT5-6
F4
RF4
Current detection connection for OUT7-8
A1
RF5
Current detection connection for OUT9-10
F7
RF6
Current detection connection for OUT11-12
E2
PI1
Photosensor drive output
E3
PI2
Photosensor drive output
E5
BI1
Schmitt buffer input 1
E4
BO1
Schmitt buffer output 1
E6
BI2
Schmitt buffer input 2
D6
BO2
Schmitt buffer output 2
Chip enable
B3
ST
D2
SCLK
Serial data transfer clock
C2
DATA
Serial data
B2
STB
Serial data latch pulse input
B4
CLK1
Stepping motor clock for OUT1-4
B5
CLK2/PWM
Stepping motor clock for OUT5-8/PWM input for OUT5-8/PWM input for OUT9-10
B6
CLK3/ENA6
Stepping motor clock for OUT9-12/Enable input for OUT11-12
No.A1626-6/28
LV8048CS
Serial Data Input Overview
Serial Data Input Timing Chart
ST
DATA
D0
D1
D2
D3
D4
D5
D6
D7
D8
SCLK
STB
This edge latches the state setting data.
Data is input in order from D0 to D8. Data is transferred on the SCLK rising edge and, after all data has been transferred,
the data is latched by the rising edge of the STB signal.
Note that the IC internal circuits will not accept the SCLK signal while the STB signal is high.
Timing with which the Serial Data is Reflected in the Outputs
Basically, the new values are reflected in the output at the point the data is latched with the STB signal. → Pattern 1
However, the "Excitation direction" and "Excitation mode" settings used in stepping motor clock drive mode for
channels 1 through 4 are an exception. In this case only, after the data is latched with the STB signal, the new values are
reflected on the next rising edge of the CLK1 signal and CLK2 signal. → Pattern 2
(Similarly, the “Excitation direction” and “Excitation “mode settings used in the stepping motor clock drive mode for
channels 5 to 6 are also an exception. After the data is latched with the STB signal, the new values are reflected on the
next rising edge of the CLK3 signal.)
[Pattern 1]
[Pattern 2]
CLK
CLK
STB
STB
Data latch timing
STB timing
Data latch timing
Rising edge timing
No.A1626-7/28
LV8048CS
Detailed Description of Serial Data Input
Note: This IC's channels are assigned as follows.
OUT1/OUT2
→
Channel 1
OUT3/OUT4
→
Channel 2
OUT5/OUT6
→
Channel 3
OUT7/OUT8
→
Channel 4
OUT9/OUT10
→
Channel 5
OUT11/OUT12 →
Channel 6
Stepping motor excitation type for channels 1 through 6
This IC supports connecting stepping motors to channels 1 and 2 and 3 and 4 to channels 5 and 6. Either of these stepping
motors can be controlled by a single clock signal.
When this capability is used, the clock signal input pins and the channels as associated as shown below.
CLK1 :
CLK2/PWM :
CLK3/ENA6 :
Controls channel 1 and 2 drive
Controls channel 3 and 4 drive
Controls channel 5 and 6 drive
The following state settings related to control of these stepping motors are set using the serial data. (See subsection,
Serial Logic Table 1, 2, in section ,Truth Tables, for a detailed description of this data.)
[For channel 1 to 4 drive]
● Excitation mode :
● Microstep division number :
● Excitation direction :
● Step/hold :
● Counter reset:
● Output enable :
● Chopping frequency :
● Current setting reference voltage :
2-phase, 1-2 phase (full torque), 1-2 phase or microstep
256 or 128
CW (clockwise) or CCW (counterclockwise)
Clear or Hold
Clear or Reset
Output Off or Output On
Selects one of four values
Selects one of four values
[For channel 5, 6 drive]
● Excitation mode :
● Excitation direction :
● Step/Hold :
● Counter reset :
● Output enable :
2-phase, 1-2 phase
CW (clockwise) or CCW (counterclockwise)
Clear or Hold
Clear or Reset
Output Off or Output On
No.A1626-8/28
LV8048CS
[CLK1] pin function
input
ST
CLK1
L
*
operational mode
standby mode
H
excitation step sending
H
excitation step maintenance
[CLK2/PWM] possession [CLK3/ENA6] similar
Excitation mode setting : (D0 = [1], D1 = [0], D2 = [0], D3 = [0])
D4
D5
D6
excitation mode
0
1
0
1
0
0
1
1
*
*
*
0
1
2-phase
1-2 phase (full torque)
1-2 phase
microstep (256step)
microstep (128step)
イニシャル位置
1ch
2ch
100%
-100%
100%
0%
100%
0%
100%
0%
It is an initial position in each excitation mode when the counter is reset the state in the early starting up the power supply.
The serial data for standard voltage setting : (D0 = [0], D1 = [1], D2 = [1], D3 = [0])
D6
D7
Current setting and standard voltages
0
0
0.2V
1
0
0.140V
0
1
0.1V
1
1
0.060V
A standard voltage for the current the setting and the standard voltage output current setting can be switched to four
stages by the serial data.
It is effective for the power saving when the motor energizes maintenance.
(Computational method of set current value)
A standard voltage can set the output current from the RF resistance connected between standard voltage and
terminal RF-GND because it is changeability can (0.2V,0.140V,0.1V,0.060V) in the serial data.
IOUT = (Standard voltage x Set current ratio) / RF resistance
(example)The following output current flows in 100% and the RF resistance 1Ω compared with 0.2V in a standard
voltage and set currents at times.
IOUT = 0.2V × 100% / 1Ω = 200mA
Chopping frequency setting
The oscillation circuit is built into in IC, and the chopping frequency of the constant current control can be switched by
setting serial data 0110, D4, D5, and ***.
DATA[4]
DATA[5]
chopping frequency
0
0
390kHz
1
0
195kHz
0
1
570kHz
1
1
285kHz
No.A1626-9/28
LV8048CS
Excitation Mode Setting
This section presents the timing charts for each excitation mode.
Two-Phase Excitation Timing Chart
CLK1 or CLK2/PWM
or CLK3/ENA6
Position number
(%)
100
I1
0
(%) -100
100
I2
0
-100
Channel 1(channel 3) current
100%
Channel 2(channel 4)
current
0%
-100%
-100%
0%
100%
No.A1626-10/28
LV8048CS
1-2 phase (full torque) Excitation Timing Chart
CLK1 or CLK2/PWM
CLK3/ENA6
Position number
(%)
100
I1
0
(%) -100
100
I2
0
-100
Channel 1(channel 3 or channel 5) current
100%
Channel 2(channel 4 or
channel 6) current
0%
-100%
-100%
0%
100%
No.A1626-11/28
LV8048CS
1-2 Phase Excitation Timing Chart
CLK1 or CLK2/PWM
Position number
(%)
100
I1
0
(%) -100
100
I2
0
-100
Channel 1(channel 3) current
100%
Channel 2(channel 4)
current
0%
-100%
-100%
0%
100%
No.A1626-12/28
LV8048CS
128-division microstep Timing Chart
Ichi of the motor also similarly moves 128-division microstep and 256-division microstep at the time of each standing up
of CLK.
CLK1 or
CLK2/PWM
(%)
100
I1
0
-100
(%)
100
I2
0
-100
Expansion
CLK1 or CLK2/PWM
Position number
(128)
1
2
3
4
5
6
7
8
(%)
100
I1
-100
(%)
100
I2
0
-100
No.A1626-13/28
LV8048CS
256-division microstep Timing Chart
CLK1 or
CLK2/PWM
(%)
100
I1
0
-100
(%)
100
I2
0
-100
Expansion
CLK1 or CLK2/PWM
Position number
(256)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
(%)
100
I1
-100
(%)
100
I2
0
-100
No.A1626-14/28
LV8048CS
Operation when excitation mode of operation is changed
Chenge to microstep(256-division or 128-division)
After the change, it moves to the following position of microstep by the first pulse when changing to
microstep(256-division or 128-division) from each excitation mode.
(two aspect, 1-2 aspect full torque)
Channel 1 aspect current ratio(%)
100.0
66.7
33.3
0.0
66.7
33.3
100.0
Channel 2 aspect current ratio(%)
Before the change of the excitation mode
excitation mode
position
θ64
θ63 to θ33
256-division microstep
θ32
θ31 to θ1
θ0
θ64
θ63 to θ33
128-division microstep
θ32
θ31 to θ1
θ0
θ64
1-2 phase
θ32
θ0
θ64
1-2 phase full torque
θ32’
θ0
two phase
θ32’
Step position of excitation mode
256-division microstep
128-division microstep
θ62
θ62 to θ32
θ30
θ30 to θ0
-θ2
θ63
θ62 to θ32
θ31
θ30 to θ0
-θ1
θ63
θ62
θ31
θ30
-θ1
-θ2
θ63
θ62
θ31
θ30
-θ1
-θ2
θ31
θ30
No.A1626-15/28
LV8048CS
Change to 1-2 aspect excitation (1-2 aspect excitation full torque)
It moves to θ32(θ32') by the first pulse after the change when changing to 1-2 aspect excitation (1-2 aspect exciting full
torque) from each excitation mode, and it shifts to 1-2 aspect excitation (1-2 aspect exciting full torque) afterwards.
However, after the change, it moves to the following position of 1-2 aspect excitation (1-2 aspect exciting full torque)
by the first pulse when the position of the previous state of the change is θ32(θ32').
Change to two aspect excitation
It moves to θ32 'by the first pulse after the change when changing from 1ch to two aspect excitation from each
excitation mode for 4ch, and it moves to the following position of two aspect excitation afterwards. However, after the
change, it moves to the following position by the first pulse for 5ch and 6ch.
(two aspect, 1-2 aspect full torque)
Channel 1 aspect current ratio(%)
100.0
66.7
33.3
0.0
33.3
66.7
100.0
Channel 2 aspect current ratio(%)
Before the change of the excitation mode
excitation mode
position
θ64
θ63 to θ33
256-division
θ32
microstep
θ31 to θ1
θ0
θ64
θ63 to θ33
128-division
θ32
microstep
θ31 to θ1
θ0
θ64
1-2 phase
θ32
θ0
1-2 phase full torque
θ64
θ32’
θ0
two phase
θ32’
1-2 phase
θ32
θ32
θ0
θ32
-θ32
θ32
θ32
θ0
θ32
-θ32
θ32
θ0
-θ32
θ0
Step position of excitation mode
1-2 phase full torque
θ32’
θ32’
θ0
θ32’
-θ32’
θ32’
θ32’
θ0
θ32’
-θ32’
θ32’
θ0
-θ32’
two phase
θ32’
θ32’
θ32’
θ32’
-θ32’
θ32’
θ32’
θ32’
θ32’
-θ32’
θ32’
θ32’
-θ32’
θ32’(θ32’)
θ32’(-θ32’)
-θ32’ (-θ32’)
θ0(θ0)
*()In the inside, for 5ch and 6ch
No.A1626-16/28
LV8048CS
Sample Timing Chart for the Excitation Direction Setting
The excitation direction setting sets the excitation (rotation) direction of the stepping motor.
With the CW (clockwise) setting, the phase of the channel 2 current is delayed from that of the channel 1 current by 90°.
With the CCW (counterclockwise) setting, the phase of the channel 2 current leads that of the channel 1 current by 90°.
The same applies for channel 3, 4, 5 and 6 drive.
Excitation direction
CW (clockwise)
CCW (counterclockwise)
CLK1
(CLK2/PWM)
or CLK3/ENA6)
(Position number)
(8)
(1)
(2)
(3)
(4)
(5)
(4)
(3)
(2)
(1)
(8)
(7)
Channel 1 output
Channel 2 output
No.A1626-17/28
LV8048CS
Step/Hold Operation Overview
Internal CLK
logic
CLK (external)
logic
Internal logic
Step/Hold setting signal
Sample Timing Chart for the Step/Hold Setting
When the Step/Hold data is set to the Hold state, the state of the external clock signal (CLK) at that time is latched and
held as the internal clock signal.
At the timing with which Step/Hold is set to the Hold state for the first time in the figure below, the internal clock signal
will be held at the low level because the external clock (CLK) was at the low level. In contrast, at the timing with which
Step/Hold is set to the Hold state for the second time, the internal clock signal will be held at the high level because the
external clock (CLK) was at the high level.
When Step/Hold is set to the Clear state, the internal clock is synchronized with the external clock (CLK). The output
holds the state it was in at the point Step/Hold is set to the Hold state, and advances on the next clock signal rising edge
after Step/Hold is set to the Clear state.
As long as Step/Hold is in the Hold state, the position number does not advance even if an external clock (CLK) signal is
applied.
Step/Hold
Clear
Hold
Clear
Hold
Clear
CLK (external)
Held at the
low level
Internal clock
(Position number)
(%)
I1
(8)
(1)
(2)
(3)
(3)
(3)
Held at the
high level
(3)
(4)
(5)
(6)
(7)
(7)
(7)
(7)
(8)
(1)
100
0
(%) -100
100
I2
0
-100
Hold state
Hold state
No.A1626-18/28
LV8048CS
Sample Timing Chart for the Counter Reset Setting
When the Counter Reset setting is set to the Reset state, the output goes to the initial state on the rising edge of the STB
signal. Then, when the Counter Reset setting is set to the Normal Operation (cleared) state, the output begins to advance
the position number on the rising edge of the CLK signal following the rise of the STB signal.
Counter Reset
Normal Operation
Reset
Normal Operation
CLK
(Position number)
(8)
(1)
(2)
(3)
(4) (5) (8) (8)
(8)
(1)
(8)
(2)
(3)
(4)
(5)
(6)
(8)
(7)
Channel 1 output
Channel 2 output
Initial state
Sample Timing Chart for the Output Enable Setting
When the Output Enable setting is set to the Output Off state, the outputs are turned off and set to the high-impedance
state on the rising edge of the STB signal.
Note, however, that since the internal clock continues to operate, the position number advances as long as a clock signal
(CLK) is input. Therefore, when the Output Enable setting is next set to the Output On (cleared) state, the output is
turned on at the STB signal rising edge and the output levels at that time will be those for the position number to which
the state has advanced due to the CLK signal input.
Output On
Output Enable
Output Off
Output On
CLK
(Position number)
(8)
(1)
(2)
(3)
(4)
(5) (6)
(7)
(8)
(1)
(2) (3)
(4)
(5)
(6)
(7)
(8)
Channel 1 output
Channel 2 output
Outputs are in the high-impedance state
No.A1626-19/28
LV8048CS
DC Motor and Voice Coil Motor Drive Methods (Channel 3, 4)
When channel 3 or channel 4 is used to drive a DC or voice coil motor, the drive polarity is set with the serial data.
Setting Procedure
(1) Set PWM signal input(channel 3 to 4) to CLK2/PWM select with the serial data.
→This sets up the signal input from the CLK2/PWM pin to be accepted as a PWM signal for channel 3 or channel 4.
( It doesn't accept as CLK signal.)
(2) If the output is to be controlled by PWM control, set up PWM mode and PWM signal allocation with the serial data.
(3) Set the drive polarity for each channel with the serial data.
(4) If the output is to be controlled by PWM control, input the CLK2/PWM signal to the PWM pin.
The following tables describe the correspondence between the PWM signal and the output logic.
Operation in Slow Decay Mode (forward/reverse ↔ brake)
Serial input
D4
D5
0
1
D6
PWM input
D7
CLK2/PWM
Output
OUT6
0
OFF
OFF
Standby mode
0
H
L
OUT5 → OUT6
0
1
L
H
OUT6 → OUT5
1
1
L
L
L
OUT7
OUT8
Mode
OUT5
Brake mode
OFF
OFF
Standby mode
H
L
OUT7 → OUT8
1
L
H
OUT8 → OUT7
1
L
L
Brake mode
0
0
1
0
0
1
0
0
L
L
Brake mode
1
0
L
L
Brake mode
0
1
L
L
Brake mode
1
1
L
L
0
0
1
0
0
1
1
1
H
Brake mode
L
L
Brake mode
L
L
Brake mode
L
L
Brake mode
L
L
Brake mode
Operation in Fast Decay Mode (forward/reverse ↔ standby mode)
Serial input
D4
D5
0
1
D6
PWM input
D7
Output
OUT6
0
OFF
OFF
Standby mode
0
H
L
OUT5 → OUT6
0
1
L
H
OUT6 → OUT5
1
1
L
L
0
1
0
0
1
1
1
L
OUT7
OUT8
Mode
OUT5
0
CLK2/PWM
Brake mode
OFF
Standby mode
H
L
OUT7 → OUT8
L
H
OUT8 → OUT7
L
L
OFF
Brake mode
0
0
OFF
OFF
Standby mode
1
0
OFF
OFF
Standby mode
0
1
OFF
OFF
Standby mode
1
1
OFF
OFF
H
Standby mode
OFF
OFF
Standby mode
0
OFF
OFF
Standby mode
0
1
OFF
OFF
Standby mode
1
1
OFF
OFF
Standby mode
0
0
1
No.A1626-20/28
LV8048CS
Voice Coil Motor Drive Methods (channels 5 and 6)
When channel 5 or 6 is used to drive a motor, such as a voice coil motor, the drive polarity is set using the serial data. The
setting procedure for each channel is shown below.
[When channel 5 is used]
Set the drive polarity using the serial data.
→The signal is output between OUT9 and OUT10 when the serial data is set.
Setup steps
The direction where each channel is drive polarity to the serial data.
serial input
D4
output
mode
D5
OUT9
OUT10
0
0
OFF
OFF
standby mode
1
0
H
L
OUT9 → OUT10
0
1
L
H
OUT10 → OUT9
1
1
L
L
Brake mode
Channel 5 when you control PWM.
(1) Set CLK2/PWM selection to “PWM signal input(channel 5)” with the serial data.
→This sets up the signal input from the CLK2/PWM pin to be accepted as a PWM signal for channel 5.
(2) Set CLK3/ENA6 selection to “ENA6 signal input” with the serial data.
→This sets up the signal input from the CLK3/ENA6 pin to be accepted as a ENA signal for channel 6.
→It comes to be able to set the direction where channel 5 and channel 6 are drive polarity to the serial data.
(3) Set the drive polarity using the serial data..
→ The signal is output between OUT9 and OUT10 when the serial data is set.
Operation in Slow Decay Mode (forward/reverse ↔ brake)
Serial input
PWM input
D4
D5
0
0
1
0
0
1
1
Output
Mode
OUT9
OUT10
OFF
OFF
Standby mode
H
L
OUT9 → OUT10
L
H
OUT10 → OUT9
1
L
L
Brake mode
0
0
OFF
OFF
Standby mode
1
0
L
L
Brake mode
0
1
1
1
CLK2/PWM
L
H
L
L
Brake mode
L
L
Brake mode
Operation in Fast Decay Mode (forward/reverse ↔ standby mode)
Serial input
PWM input
D4
D5
0
0
1
0
0
1
1
CLK2/PWM
Output
Mode
OUT9
OUT10
OFF
OFF
Standby mode
H
L
OUT9 → OUT10
L
H
OUT10 → OUT9
1
L
L
Brake mode
0
0
OFF
OFF
Standby mode
1
0
OFF
OFF
Standby mode
0
1
OFF
OFF
Standby mode
1
1
L
L
Brake mode
L
H
No.A1626-21/28
LV8048CS
[When channel 6 is used]
(1) Set CLK3/ENA6 selection to “ENA6 signal input” with the serial data.
→This sets up the signal input from the CLK3/ENA6 pin to be accepted as a ENA signal for channel 6.
→It comes to be able to set the direction where channel 5 and channel 6 are drive polarity to the serial data.
(3) Set the drive polarity using the serial data.
→The signal is output between OUT11 and OUT12 only when ENA6 is set to high.
(When ENA6 is low, the signal output between OUT11 and OUT12 is set to OFF.)
ENA6 input truth table
Serial input
D6
Parallel input
D7
ENA5
L
*
*
0
0
1
0
0
1
1
1
H
Output
OUT11
Mode
OUT12
OFF
OFF
Standby mode
OFF
OFF
Standby mode
H
L
OUT11 → OUT12
L
H
OUT12 → OUT11
L
L
Brake mode
Constant Current Control Settings (channels 5 and 6)
The constant current levels for channels 5 and 6 are set as shown below.
The output constant current is set by the constant current reference voltage set with the serial data and the resistor (RF)
connected between the RF5 and RF6 pins.
The following formula can be used to calculate the output constant current.
(output constant current) = (constant current reference voltage) / (value of the resistor RF)
reference voltage setting: channel 5 setting(D0 = [0], D1 = [0], D2 = [0], D3 = [1])
channel 6 setting(D0 = [1], D1 = [0], D2 = [0], D3 = [1])
D4
D5
D6
D7
constant current reference voltage
0
0
0
0
0.200V
1
0
0
0
0.170V
0
1
0
0
0.165V
1
1
0
0
0.160V
0
0
1
0
0.155V
1
0
1
0
0.150V
0
1
1
0
0.145V
1
1
1
0
0.140V
0
0
0
1
0.135V
1
0
0
1
0.130V
0
1
0
1
0.125V
1
1
0
1
0.120V
0
0
1
1
0.115V
1
0
1
1
0.110V
0
1
1
1
0.105V
1
1
1
1
0.100V
[Motor holding current mode]
The constant current reference voltages for channels 5 and 6 are switched to one-third levels when the motor holding
current is set to ON by the serial data.
PI1, PI2 Output Drive Method
When the PI1 or PI2 output is used to drive a photosensor, the drive on/off state is set using the serial data.
Hysteresis settings of Schmitt buffer
The presence or absence of hysteresis in the Schmitt buffer outputs B01 and B02 can be set individually with the serial
data.
No.A1626-22/28
LV8048CS
Truth Tables Serial Logic Table 1
Input
Setting mode
D0 D1 D2 D3 D4 D5 D6 D7 D8
0 * * * *
1 *
Content set
*
*
*
*
0
1
*
*
*
*
*
*
*
*
*
0
1
*
*
*
*
*
*
*
*
*
0
(Dummy data)
1
*
2-phase excitation
1 0 *
*
*
0
1
*
*
*
*
*
*
0
0 1 *
{
{
{
{
(full torque)
1-2 phase
excitation
Microstep
256 divisions
128 divisions
*
*
*
*
*
0
1
*
*
*
*
*
*
Microstep
* division number
*
(Dummy data)
*
0
(Dummy data)
1
*
CLK2 signal input
CLK2/PWM
select
*
PWM signal input
* 0 *
*
*
1
*
*
*
*
*
*
*
*
Serial data
activation timing
CLK1 CLK2 CLK3 STB
1-2 phase excitation
AF Excitation
mode
*
0
1
*
*
*
*
*
*
1
1 0 0 0
*
*
*
*
*
*
0
1
PI
OUT1-2 OUT3-4 OUT5-6 OUT7-8 OUT9-10 OUT11-12
CW (clockwise)
AF Excitation
CCW
Direction
(counterclockwise)
Clear
AF Step/Hold
Hold
Reset
AF Counter
Reset
Clear
Output Off
AF Output
Enable
Output On
*
*
*
0 0 0 0 *
*
*
*
*
*
0
Channels set
Notes
{
{
{
↓*1
↓*2
Slow Decay
(Forward/reverse ⇔
PWM mode
0 1 0 0 * 1 *
*
*
brake)
Fast Decay
standby mode)
*
*
*
*
*
0
{
{
{
*2
* 0 0 0
*
1 0
*
0 1
*
1 1
* 1 * *
* * * *
1 *
*
*
*
*
*
*
*
1 1 0 0 *
0
1
0
1
*
*
*
*
*
*
{
(Forward/reverse ⇔
1
1
*
*
*
*
*
*
0
0
1
1
*
*
*
*
*
*
OFF
Channel 3 only
PWM signal
Channel 4 only
allocation
Channel 3 and 4
Channel 5 only
CW (clockwise)
Zoom Excitation
CCW
Direction
* * *
(counterclockwise)
* * *
Clear
Zoom step hold
* * *
Hold
0 * * Zoom counter
Reset
reset
1 * *
Clear
* 0 * Zoom output
Output Off
enable
* 1 *
Output On
* * 0
(Dummy data)
* * 1
* * *
OFF
* * *
OUT5-6
OUT5→OUT6
* * * drive polarity
OUT6→OUT5
* * *
Brake
0 0 *
OFF
1 0 *
OUT7-8
OUT7→OUT8
0 1 * drive polarity
OUT8→OUT7
1 1 *
Brake
* * 0
(Dummy data)
* * 1
{
*1
{
{
{
{
{
*2
{
No.A1626-23/28
LV8048CS
Serial Logic Table 2
Input
Setting mode
D0 D1 D2 D3 D4 D5 D6 D7 D8
0 * * * *
1 *
*
*
* 0 *
* 1 *
*
*
*
*
*
*
0
1
*
*
*
*
*
*
0
0
1
1
*
*
*
*
*
*
0
0
1
1
*
*
*
*
*
0
1
*
*
*
*
*
*
*
*
0
(Dummy data)
1
*
Chopping
*
frequency
*
setting
*
*
Chopping
*
current standard
*
voltage select
*
* * *
0 0 *
0
* 1
* *
1 0 *
*
*
0 1 *
*
*
1 1 1 0
1 1 * *
* * 0 *
*
*
*
* 1 *
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
0
0
1
1
*
*
*
*
*
*
0
0
1
1
*
*
*
*
*
0
1
*
*
*
*
*
*
*
*
0
1
0
1
*
*
*
*
*
*
0
1
0
1
*
Channels set
Notes
PI
OUT1-2 OUT3-4 OUT5-6 OUT7-8 OUT9-10 OUT11-12
CW (clockwise)
SH Excitation
CCW
Direction
(counterclockwise)
2-phase excitation
SH Excitation
1-2 phase
mode
excitation
Clear
SH Step/Hold
Hold
Reset
SH Counter
Reset
Clear
Output Off
SH Output
Enable
Output On
OFF
OUT9-10
OUT9→OUT10
drive polarity
OUT10→OUT9
Brake
OFF
OUT11-12
OUT11→OUT12
drive polarity
OUT12→OUT11
Brake
*
*
*
*
*
*
1 0 1 0
*
0
1
0
1
*
*
*
*
*
*
0
1
0
1
*
0 1 1 0
*
*
*
*
Content set
CLK3/ENA6
select
Zoom Excitation
mode
Number of
partitions
to microstep
390KHz
195KHz
570KHz
285KHz
100%(0.2V)
70%(0.140V)
50%(0.1V)
30%(0.060V)
CLK3 signal input
ENA6 signal input
2-phase excitation
1-2 phase
excitation
(full torque)
1-2 phase
excitation
microstep
256 divisions
Serial data
activation timing
CLK1 CLK2 CLK3 STB
{
{
*3
{
{
{
{
*4
{
{
{
{
{
{
{
↑*3
↑*4
{
{
{
{
128 divisions
* 0 *
(Dummy data)
* 1 *
* * 0
(Dummy data)
* * 1
No.A1626-24/28
LV8048CS
Serial Logic Table 3
Input
Setting mode
D0 D1 D2 D3 D4 D5 D6 D7 D8
0 0 0 0 *
1 0 0 0 *
0 1 0 0 *
1 1 0 0 *
0 0 1 0 *
1 0 1 0 *
0 1 1 0 *
OUT9-10
1 1 1 0 *
constant current
0 0 0 1 *
reference voltage
0 0 0 1
1 0 0 1 *
0 1 0 1 *
1 1 0 1 *
0 0 1 1 *
1 0 1 1 *
0 1 1 1 *
1 1 1 1 *
* * * * 0
(Dummy data)
* * * * 1
0
1
0
1
0
1
0
1
0
1 0 0 1 1
0
1
0
1
0
1
*
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
*
*
*
0
1
*
*
*
*
0 1 0 1
*
*
*
*
*
0
1
*
*
*
*
*
*
*
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
*
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
*
*
*
*
*
*
*
*
OUT11-12
*
constant current
*
reference voltage
*
*
*
*
*
*
*
0
1
Maintenance
voltage
* *
(OUT9-10/11-12)
* * * Photo senser1
drive
* * *
* * * Photo senser2
drive
* * *
0 * * Buffer hysteresis
(BI1/BO1)
1 * *
* 0 * Buffer hysteresis
(BI2/BO2)
* 1 *
* * 0
(Dummy data)
* * 1
Content set
Notes
Channels set
PI
OUT1-2 OUT3-4 OUT5-6 OUT7-8 OUT9-10 OUT11-12
0.200V
0.170V
0.165V
0.160V
0.155V
0.150V
0.145V
0.140V
0.135V
0.130V
0.125V
0.120V
0.115V
0.110V
0.105V
0.100V
{
0.200V
0.170V
0.165V
0.160V
0.155V
0.150V
0.145V
0.140V
0.135V
0.130V
0.125V
0.120V
0.115V
0.110V
0.105V
0.100V
OFF(100%)
ON(33%)
OFF
ON
OFF
ON
NOT
Having
NOT
Having
Serial data
activation timing
CLK1 CLK2 CLK3 STB
{
{
{
{
{
{
{
No.A1626-25/28
LV8048CS
Equivalent Circuits
Pin No.
Pin name
E4
BO1
D6
BO2
Equivalent Circuit
VCC
E4 D6
SGND
A6
OUT1
A7
RF1
B7
OUT2
A3
OUT3
A4
RF2
A5
OUT4
E1
OUT5
A6 A3
B7 A5
F1
RF3
E1 F3
F2 F5
F2
OUT6
F3
OUT7
F4
RF4
F5
OUT8
VB
A7 F1
A4 F4
F6
OUT11
F7
RF6
E7
OUT12
VB
VCC
F6
SGND
E7
F7
C2
DATA
B2
STB
D2
SCLK
B4
CLK1
B5
CLK2/PWM
C2 B2
B6
CLK3/ENA6
D2 B4
VCC
B5 B6
SGND
Continued on next page.
No.A1626-26/28
LV8048CS
Continued from preceding page.
Pin No.
B3
Pin name
Equivalent Circuit
ST
VCC
B3
SGND
B2
OUT10
A1
RF5
A2
OUT9
VB
VCC
B2
A2
SGND
E5
BI1
E6
BI2
A1
VCC
E5 E6
SGND
E2
PI1
E3
PI2
E2 E3
SGND
No.A1626-27/28
LV8048CS
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products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
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This catalog provides information as of December, 2009. Specifications and information herein are subject
to change without notice.
PS No.A1626-28/28