MCH12140, MCK12140 Phase-Frequency Detector The MCH/K12140 is a phase frequency−detector intended for phase−locked loop applications which require a minimum amount of phase and frequency difference at lock. When used in conjunction with high performance VCO such as the MC100EL1648, a high bandwidth PLL can be realized. The device is functionally compatible with the MC12040 phase−frequency detector with the maximum frequency extending to 800 MHz. When the Reference (R) and VCO (V) inputs are unequal in frequency and/or phase, the differential UP (U) and DOWN (D) outputs will provide pulse streams which when subtracted and integrated provide an error voltage for control of a VCO. See AND8040 for further information. The device is packaged in a small outline, surface mount 8−lead SOIC package. There are two versions of the device to provide I/O compatibility to the two existing ECL standards. The MCH12140 is compatible with MECL 10H logic levels while the MCK12140 is compatible to 100 K ECL logic levels. This device can also be used in +5.0 V systems. See AND8020 for termination information http://onsemi.com MARKING DIAGRAM 8 1 x140 ALYW 1 x A L Y W Features • • • • • SOIC−8 D SUFFIX CASE 751 8 800 MHz Typical Bandwidth Small Outline 8-Lead SOIC Package 75 k Internal Input Pulldown Resistors >1000 V ESD Protection Pb−Free Package is Available = H or K = Assembly Location = Wafer Lot = Year = Work Week PIN CONNECTIONS U U D D For proper operation, the input edge rate of the R and V inputs should be less than 5.0 ns. 1 8 2 7 3 6 4 5 VCC R V VEE (Top View) ORDERING INFORMATION Device Package Shipping† MCH12140D SOIC−8 98 Units/Rail MCH12140DR2 SOIC−8 2500 Tape & Reel SOIC−8 (Pb−Free) 2500 Tape & Reel MCK12140D SOIC−8 98 Units/Rail MCK12140DR2 SOIC−8 2500 Tape & Reel MCH12140DR2G U (fR > fV) R U (fR > fV) R Q S S Q R V D (fV > fR) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. D (fV > fR) Figure 1. Logic Diagram Semiconductor Components Industries, LLC, 2004 April, 2004 − Rev. 7 1 Publication Order Number: MCH12140/D MCH12140, MCK12140 TRUTH TABLE* Input Output Input Output R V U D U D R V U D U D 0 0 1 0 0 1 1 1 X X X X X X X X X X X X X X X X 1 1 1 1 1 0 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 0 1 1 1 1 1 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 1 1 1 0 0 0 1 1 0 1 1 1 0 0 1 *This is not strictly a functional table; i.e., it does not cover all possible modes of operation. However, it gives a sufficient number of tests to ensure that the device will function properly. H−SERIES DC CHARACTERISTICS (VEE = VEE(min) − VEE(max); VCC = GND (Note 1), unless otherwise noted.) −40°C 0°C 25°C 70°C Symbol Min Max Min Max Min Max Min Max Unit Output HIGH Voltage VOH −1080 −890 −1020 −840 −980 −810 −910 −720 mV Output LOW Voltage VOL −1950 −1650 −1950 −1630 −1950 −1630 −1950 −1595 mV Input HIGH Voltage VIH −1230 −890 −1170 −840 −1130 −810 −1060 −720 mV Input LOW Voltage VIL −1950 −1500 −1950 −1480 −1950 −1480 −1950 −1445 mV Input LOW Current IIL 0.5 − 0.5 − 0.5 − 0.3 − A Characteristic K−SERIES DC CHARACTERISTICS (VEE = VEE(min) − VEE(max); VCC = GND (Note 2), unless otherwise noted.) −40°C 0°C to 70°C Symbol Min Typ Max Min Typ Max Condition Unit Output HIGH Voltage VOH −1085 −1005 −880 −1025 −955 −880 VIN = VIH(max) mV Output LOW Voltage VOL −1830 −1695 −1555 −1810 −1705 −1620 or VIL(min) mV Output HIGH Voltage VOHA −1095 − − −1035 − − VIN = VIH(min) mV Output LOW Voltage VOLA − − −1555 − − −1610 or VIL(max) mV Input HIGH Voltage VIH −1165 − −880 −1165 − −880 − mV Input LOW Voltage VIL −1810 − −1475 −1810 − −1475 − mV Input LOW Current IIL 0.5 − − 0.5 − − VIN = VIL(max) A Characteristic MAXIMUM RATINGS (Note 3) Symbol Value Unit Power Supply (VCC = 0 V) VEE −8.0 to 0 VDC Input Voltage (VCC = 0 V) VI 0 to −6.0 VDC Iout 50 100 mA TA −40 to +70 °C VEE −5.7 to −4.2 V Rating Output Current Continuous Surge Operating Temperature Range Operating Range (Notes 3 and 4) NOTE: ESD data available upon request. 1. 10H circuits are designed to meet the DC specifications shown in the table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. Outputs are terminated through a 50 resistor to −2.0 V except where otherwise specified on the individual data sheets. 2. This table replaces the three tables traditionally seen in ECL 100 K data books. The same DC parameter values at VEE = −4.5 V now apply across the full VEE range of −4.2 V to −5.5 V. Outputs are terminated through a 50 resistor to −2.0 V except where otherwise specified on the individual data sheets. 3. Absolute maximum rating, beyond which, device life may be impaired, unless otherwise specified on an individual data sheet. 4. Parametric values specified at: H−Series: −4.20 V to −5.50 V K−Series: −4.94 V to −5.50 V http://onsemi.com 2 MCH12140, MCK12140 DC CHARACTERISTICS (VEE = VEE(min) − VEE(max); VCC = GND, unless otherwise noted.) −40°C Characteristic 0°C 25°C 70°C Symbol Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit Power Supply Current H K IEE − − 45 45 − − 38 38 45 45 52 52 38 38 45 45 52 52 38 42 45 50 52 58 mA Power Supply Voltage H K VEE −4.75 −4.20 −5.2 −4.5 −5.5 −5.5 −4.75 −4.20 −5.2 −4.5 −5.5 −5.5 −4.75 −4.20 −5.2 −4.5 −5.5 −5.5 −4.75 −4.20 −5.2 −4.5 −5.5 −5.5 V IIH − − 150 − − 150 − − 150 − − 150 A Input HIGH Current AC CHARACTERISTICS (VEE = VEE(min) − VEE(max); VCC = GND, unless otherwise noted.) −40°C 0°C 25°C 70°C Characteristic Symbol Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit Maximum Toggle Frequency FMAX − 800 − 650 800 − 650 800 − 650 800 − − Propagation Delay to Output tPLH tPHL − − − − 440 330 330 440 − − − − 320 210 210 320 440 330 330 440 580 470 470 580 320 210 210 320 440 330 330 440 580 470 470 580 360 240 240 360 480 360 360 480 620 500 500 620 ps − 225 − 100 225 350 100 225 350 100 225 350 R to D R to U V to D V to U Output Rise/Fall Times Q (20 to 80%) tr tf ps APPLICATIONS INFORMATION R lags V in phase The 12140 is a high speed digital circuit used as a phase comparator in an analog phase-locked loop. The device determines the “lead” or “lag” phase relationship and time difference between the leading edges of a VCO (V) signal and a Reference (R) input. Since these edges occur only once per cycle, the detector has a range of ±2 radians. The operation of the 12140 can best be described using the plots of Figure 2. Figure 2 plots the average value of U, D and the difference between U and D versus the phase difference between the V and R inputs. There are four potential relationships between V and R: R lags or leads V and the frequency of R is less than or greater than the frequency of V. Under these four conditions the 12140 will function as follows: Fv > Fr −2 R lags V U R leads V − Fv < Fr 2 When the R and V inputs are equal in frequency and the phase of R lags that of V the U output will stay HIGH while the D output will pulse from HIGH to LOW. The magnitude of the pulse will be proportional to the phase difference between the V and R inputs reaching a minimum 50% duty cycle under a 180° out of phase condition. The signal on D indicates to the VCO to decrease in frequency to bring the loop into lock. V frequency > R frequency When the frequency of V is greater than that of R the 12140 behaves in a similar fashion as above. Again the signal on D indicates that the VCO frequency must be decreased to bring the loop into lock. R leads V in phase When the R and V inputs are equal in frequency and the phase of R leads that of V the D output will stay HIGH while the U output pulses from HIGH to LOW. The magnitude of the pulse will be proportional to the phase difference between the V and R inputs reaching a minimum 50% duty cycle under a 180° out of phase condition. The signal on U indicates to the VCO to increase in frequency to bring the loop into lock. VOH VOH − VOL 2 D VOH −2 − 2 U−D −2 − VOH − VOL 2 V frequency < R frequency When the frequency of V is less than that of R the 12140 behaves in a similar fashion as above. Again the signal on U indicates that the VCO frequency must be decreased to bring the loop into lock. From Figure 2 when V and R are at the same frequency and in phase the value of U − D is zero thus providing a zero error voltage to the VCO. This situation indicates the loop is in lock and the 12140 action will maintain the loop in its locked state. VOH − VOL 2 2 VOL − VOH 2 Figure 2. Average Output Voltage vs. Phase Difference http://onsemi.com 3 MCH12140, MCK12140 PACKAGE DIMENSIONS SOIC−8 D SUFFIX CASE 751−07 ISSUE AB NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. −X− A 8 5 0.25 (0.010) S B 1 M Y M 4 K −Y− G C N DIM A B C D G H J K M N S X 45 SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M J S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0 8 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 8 0.010 0.020 0.228 0.244 SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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