ONSEMI NLAS1053USG

NLAS1053
2:1 Mux/Demux Analog
Switches
The NLAS1053 is an advanced CMOS analog switch fabricated
with silicon gate CMOS technology. It achieves very high speed
propagation delays and low ON resistances while maintaining CMOS
low power dissipation. The device consists of a single 2:1
Mux/Demux (SPDT), similar to ON Semiconductor’s NLAS4053
analog and digital voltages that may vary across the full power supply
range (from VCC to GND).
The inhibit and select input pins have over voltage protection that
allows voltages above VCC up to 7.0 V to be present without damage
or disruption of operation of the part, regardless of the operating
voltage.
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MARKING DIAGRAMS
Features
•
•
•
•
•
•
•
•
•
•
•
US8
US SUFFIX
CASE 493−01
High Speed: tPD = 1 ns (Typ) at VCC = 5.0 V
Low Power Dissipation: ICC = 2 A (Max) at TA = 25°C
High Bandwidth, Improved Linearity, and Low RDSON
INH Pin Allows a Both Channels ‘OFF’ Condition (With a High)
RDSON ≅ 25 , Performance Very Similar to the NLAS4053
Break Before Make Circuitry, Prevents Inadvertent Shorts
Useful For Switching Video Frequencies Beyond 50 MHz
Latchup Performance Exceeds 300 mA
ESD Performance: HBM > 2000 V; MM > 200 V, CDM > 1500 V
Tiny US8 Package, Only 2.1 X 3.0 mm
Pb−Free Package is Available
8
AC M G
G
1
AC = Specific Device Code
M
= Date Code*
G
= Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation may vary depending
upon manufacturing location.
ORDERING INFORMATION
COM 1
8
VCC
INH 2
7
CH0
N/C 3
6
CH1
GND 4
5
Select
May, 2006 − Rev. 2
Package
Shipping†
NLAS1053US
US8
3000 / Tape & Reel
NLAS1053USG
US8
3000 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
FUNCTION TABLE
Figure 1. Pin Assignment
© Semiconductor Components Industries, LLC, 2006
Device
1
INH
Select
Ch 0
Ch 1
H
L
L
X
L
H
OFF
ON
OFF
OFF
OFF
ON
Publication Order Number:
NLAS1053/D
NLAS1053
MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Positive DC Supply Voltage
VCC
−0.5 to +7.0
V
Digital Input Voltage (Select and Inhibit)
VIN
−0.5 ≤ V is ≤ +7.0
V
Analog Output Voltage (VCH or VCOM)
VIS
−0.5 ≤ V is ≤ VCC +0.5
V
DC Current, Into or Out of Any Pin
IIK
50
mA
TSTG
−65 to +150
_C
Lead Temperature, 1 mm from Case for 10 Seconds
TL
260
_C
Junction Temperature under Bias
TJ
+150
_C
Thermal Resistance
JA
250
_C/W
Power Dissipation in Still Air at 85_C
PD
250
mW
Storage Temperature Range
Moisture Sensitivity
Flammability Rating
MSL
Level 1
FR
UL 94 V−0 @ 0.125 in
VESD
> 2000
200
N/A
V
ILatchup
±300
mA
Oxygen Index: 30% − 35%
ESD Withstand Voltage
Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
Latchup Performance
Above VCC and Below GND at 85_C (Note 5)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2−ounce copper trace with no air flow.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Characteristics
Symbol
Min
Max
Unit
Positive DC Supply Voltage
VCC
2.0
5.5
V
Digital Input Voltage (Select and Inhibit)
VIN
GND
5.5
V
Static or Dynamic Voltage Across an Off Switch
VIO
GND
VCC
V
Analog Input Voltage (CH, COM)
VIS
GND
VCC
V
Operating Temperature Range, All Package Types
TA
−55
+125
°C
tr, tf
0
0
100
20
ns/V
Vcc = 3.3 V ± 0.3 V
Vcc = 5.0 V ± 0.5 V
117.8
90
419,300
47.9
100
178,700
20.4
110
79,600
9.4
120
37,000
4.2
130
17,800
2.0
140
8,900
1.0
TJ = 80°C
1,032,200
TJ = 90°C
80
TJ = 100°C
Time, Years
TJ = 110°C
Time, Hours
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
TJ = 120°C
Junction
Temperature 5C
NORMALIZED FAILURE RATE
DEVICE JUNCTION TEMPERATURE VERSUS TIME
TO 0.1% BOND FAILURES
TJ = 130°C
Input Rise or Fall Time
(Enable Input)
1
1
10
100
TIME, YEARS
Figure 2. Failure Rate versus
Time Junction Temperature
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2
1000
NLAS1053
DC CHARACTERISTICS − Digital Section (Voltages Referenced to GND)
Guaranteed Limit
Symbol
VCC
*55_C to 25_C
t85_C
t125_C
Unit
Minimum High−Level Input
Voltage, Select and Inhibit
Inputs
VIH
2.0
2.5
3.0
4.5
5.5
1.5
1.9
2.1
3.15
3.85
1.5
1.9
2.1
3.15
3.85
1.5
1.9
2.1
3.15
3.85
V
Maximum Low−Level Input
Voltage, Select and Inhibit
Inputs
VIL
2.0
2.5
3.0
4.5
5.5
0.5
0.6
0.9
1.35
1.65
0.5
0.6
0.9
1.35
1.65
0.5
0.6
0.9
1.35
1.65
V
Parameter
Condition
Maximum Input Leakage
Current, Select and Inhibit
Inputs
VIN = 5.5 V or GND
IIN
0 V to 5.5 V
$0.1
$1.0
$1.0
A
Maximum Quiescent Supply
Current
Select and Inhibit = VCC or GND
ICC
5.5
1.0
1.0
2.0
A
Symbol
VCC
55 to 255C
855C
1255C
Unit
DC ELECTRICAL CHARACTERISTICS − Analog Section
Guaranteed Limit
Parameter
Condition
Maximum “ON”
Resistance
(Figures 17 − 23)
VIN = VIL or VIH
VIS = GND to VCC
IINI ≤ 10.0 mA
RON
2.5
3.0
4.5
5.5
70
40
20
16
85
46
28
22
105
52
34
28
ON Resistance Flatness
(Figures 17 − 23)
VIN = VIL or VIH
IINI ≤ 10.0 mA
VIS = 1V, 2V, 3.5V
RFLAT
4.5
4
4
5
ON Resistance Match
Between Channels
VIN = VIL or VIH
IINI ≤ 10.0 mA
VCH1 or VCH0 = 3.5 V
RON
4.5
2
2
3
CH1 or CH0 Off Leakage
Current (Figure 9)
VIN = VIL or VIH
VCH1 or VCH0 = 1.0 VCOM 4.5 V
ICH0
ICH1
5.5
1
10
100
nA
COM ON Leakage
Current (Figure 9)
VIN = VIL or VIH
VCH1 1.0 V or 4.5 V with VCH0
floating or
VCH1 1.0 V or 4.5 V with VCH1
floating
VCOM = 1.0 V or 4.5 V
ICOM(ON)
5.5
1
10
100
nA
(ON)
(ON)
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NLAS1053
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns)
Guaranteed Max Limit
55 to 25_C
VCC
85_C
125_C
Test Conditions
Symbol
(V)
Min
Typ*
Max
Min
Max
Min
Max
Unit
Turn−On Time
(Figures 12 and 13)
INH to Output
RL = 300 CL = 35 pF
(Figures 4 and 5)
tON
2.5
3.0
4.5
5.5
2
2
1
1
7
5
4
3
12
10
9
8
2
2
1
1
15
15
12
12
2
2
1
1
15
15
12
12
ns
Turn−Off Time
(Figures 12 and 13)
INH to Output
RL = 300 CL = 35 pF
(Figures 4 and 5)
tOFF
2.5
3.0
4.5
5.5
2
2
1
1
7
5
4
3
12
10
9
8
2
2
1
1
15
15
12
12
2
2
1
1
15
15
12
12
ns
Transition Time (Channel Selection Time)
(Figure )
Select to Output
RL = 300 CL = 35 pF
(Figures and )
ttrans
2.5
3.0
4.5
5.5
5
5
2
2
18
13
12
9
28
21
16
14
5
5
2
2
30
25
20
20
5
5
2
2
30
25
20
20
ns
Minimum
Break−Before−Make Time
VIS = 3.0 V (Figure 3)
RL = 300 CL = 35 pF
tBBM
2.5
3.0
4.5
5.5
1
1
1
1
12
11
6
5
Parameter
1
1
1
1
1
1
1
1
ns
Typical @ 25, VCC = 5.0 V
Maximum Input Capacitance, Select/INH Input
Analog I/O (switch off)
Common I/O (switch off)
Feedthrough (switch on)
CIN
CNO or CNC
CCOM
C(ON)
8
10
10
20
pF
*Typical Characteristics are at 25_C.
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND Unless Noted)
Parameter
Condition
Maximum On−Channel −3dB Bandwidth or
Minimum Frequency Response
(Figure 10)
VIN = 0 dBm
VIN centered between VCC and GND
(Figure 7)
Maximum Feedthrough On Loss
VIN = 0 dBm @ 100 kHz to 50 MHz
VIN centered between VCC and GND
(Figure 7)
Off−Channel Isolation
(Figure 10)
f = 100 kHz; VIS = 1 V RMS
VIN centered between VCC and GND
(Figure 7)
Charge Injection Select Input to
Common I/O
(Figure 15)
VIN = VCC to GND, FIS = 20 kHz
tr = tf = 3 ns
RIS = 0 , CL = 1000 pF
Q = CL * VOUT
(Figure 8)
Total Harmonic Distortion
THD + Noise
(Figure 14)
FIS = 20 Hz to 100 kHz, RL = Rgen = 600 CL = 50 pF
VIS = 5.0 VPP sine wave
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Symbol
VCC
V
Typical
25°C
Unit
BW
3.0
4.5
5.5
170
200
200
MHz
VONL
3.0
4.5
5.5
−3
−3
−3
dB
VISO
3.0
4.5
5.5
−93
−93
−93
dB
3.0
5.5
1.5
3.0
pC
5.5
0.1
%
Q
THD
NLAS1053
VCC
DUT
VCC
Input
Output
GND
VOUT
0.1 F
300
tBMM
35 pF
90% of VOH
90%
Output
Switch Select Pin
GND
Figure 3. tBBM (Time Break−Before−Make)
VCC
DUT
VCC
Input
Output
50%
VOUT
0.1 F
Open
50%
0V
300
VOH
35 pF
90%
90%
Output
INH
Input
VOL
tON
tOFF
Figure 4. tON/tOFF
VCC
VCC
Input
DUT
Output
300 50%
VOUT
Open
50%
0V
VOH
35 pF
Output
10%
VOL
INH
Input
tOFF
Figure 5. tON/tOFF
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5
10%
tON
NLAS1053
VCC
0.1 F
VCC
Output
Input
VOUT
GND
300
50%
50%
0V
35 pF
VCC
90%
Output
Select Pin
10%
GND
ttrans
ttrans
Figure 6. ttrans (Channel Selection Time)
50 DUT
Reference
Transmitted
Input
Output
50 Generator
50 Channel switch control/s test socket is normalized. Off isolation is measured across an off channel. On loss is
the bandwidth of an On switch. VISO, Bandwidth and VONL are independent of the input signal direction.
ǒVVOUT
Ǔ for VIN at 100 kHz
IN
VOUT
Ǔ for VIN at 100 kHz to 50 MHz
VONL = On Channel Loss = 20 Log ǒ
VIN
VISO = Off Channel Isolation = 20 Log
Bandwidth (BW) = the frequency 3 dB below VONL
Figure 7. Off Channel Isolation/On Channel Loss (BW)/Crosstalk
(On Channel to Off Channel)/VONL
DUT
VCC
VIN
Output
Open
GND
CL
Output
Off
VIN
Figure 8. Charge Injection: (Q)
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On
Off
VOUT
NLAS1053
0
10
−20
1
−40
Bandwidth
(ON−RESPONSE)
Off Isolation
(dB)
LEAKAGE (nA)
100
ICOM(ON)
0.1
−60
ICOM(OFF)
0.01
VCC = 5.0 V
TA = 25_C
−80
VCC = 5.0 V
ICH(OFF)
−100
0.01
0.001
−55
−20
25
70
85
125
0.1
TEMPERATURE (°C)
100 200
1
10
FREQUENCY (MHz)
Figure 10. Bandwidth and Off−Channel
Isolation
Figure 9. Switch Leakage versus Temperature
30
0
10
20
TIME (ns)
PHASE (Degree)
25
20
15
VCC = 5.0 V
TA = 25_C
0.01
ttrans (ns)
10
30
0.1
tON/tOFF (ns)
5
1
10
FREQUENCY (MHz)
0
2.5
100 200
3
4.5
Figure 12. tON and tOFF versus VCC at 255C
30
1
VCC = 4.5 V
VINpp = 3.0 V
VCC = 3.6 V
THD + NOISE (%)
25
20
TIME (ns)
4
VCC (VOLTS)
Figure 11. Phase versus Frequency
15
10
ttrans
0.1
VINpp = 5.0 V
VCC = 5.5 V
tON/tOFF
5
0
−55
3.5
0.01
−40
25
85
125
1
10
100
Temperature (°C)
FREQUENCY (kHz)
Figure 13. tON and tOFF versus Temp
Figure 14. Total Harmonic Distortion
Plus Noise versus Frequency
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5
NLAS1053
3.0
100
2.5
10
1
VCC = 5 V
1.5
0.1
ICC (nA)
Q (pC)
2.0
1.0
0.5
0.01
VCC = 3.0 V
0.001
VCC = 3 V
0
0.0001
−0.5
0
1
2
3
4
VCC = 5.0 V
0.00001
−40
5
−20
0
20
60
80
100
120
VCOM (V)
Temperature (°C)
Figure 15. Charge Injection versus COM Voltage
Figure 16. ICC versus Temp, VCC = 3 V & 5 V
100
100
90
VCC = 2.0 V
80
80
60
60
RON ()
RON ()
70
VCC = 2.5 V
40
VCC = 3.0 V
20
50
85°C
40
125°C
30
25°C
20
VCC = 4.5 V
−55°C
10
0
0
0
1
2
3
4
0
5
0.5
1
2
2.5
VCOM (VOLTS)
VCOM (VOLTS)
Figure 17. RON versus VCOM and VCC (@ 255C
Figure 18. RON versus VCOM and Temperature,
VCC 2.0 V
70
40
60
35
25°C
30
RON ()
50
RON ()
1.5
40
30
125°C
25°C
20
125°C
15
85°C
20
10
85°C
10
25
−55°C
−55°C
5
0
0
0
0.5
1
1.5
2
2.5
3
0
VCOM (VOLTS)
0.5
1
1.5
2
2.5
3
3.5
VCOM (VOLTS)
Figure 20. RON versus VCOM and Temperature,
VCC = 3.0 V
Figure 19. RON versus VCOM and Temperature,
VCC = 2.5 V
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NLAS1053
20
18
18
16
16
125°C
12
12
RON ()
85°C
10
8
10
85°C
8
−55°C
6
6
25°C
4
25°C
−55°C
4
2
2
0
0
0
1
2
3
VCOM (VOLTS)
4
5
0
1
2
3
VCOM (VOLTS)
20
15
125°C
10
85°C
25°C
5
−55°C
0
0
1
2
4
5
6
Figure 22. RON versus VCOM and Temperature,
VCC = 5.0 V
Figure 21. RON versus VCOM and Temperature,
VCC = 4.5 V
RON ()
RON ()
125°C
14
14
3
VCOM (VOLTS)
4
5
Figure 23. RON versus VCOM and Temperature,
VCC = 5.5 V
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6
NLAS1053
PACKAGE DIMENSIONS
US8
CASE 493−02
ISSUE B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION “A” DOES NOT INCLUDE MOLD
FLASH, PROTRUSION OR GATE BURR.
MOLD FLASH. PROTRUSION AND GATE
BURR SHALL NOT EXCEED 0.140 MM
(0.0055”) PER SIDE.
4. DIMENSION “B” DOES NOT INCLUDE
INTER−LEAD FLASH OR PROTRUSION.
INTER−LEAD FLASH AND PROTRUSION
SHALL NOT E3XCEED 0.140 (0.0055”) PER
SIDE.
5. LEAD FINISH IS SOLDER PLATING WITH
THICKNESS OF 0.0076−0.0203 MM.
(300−800 “).
6. ALL TOLERANCE UNLESS OTHERWISE
SPECIFIED ±0.0508 (0.0002 “).
−X−
A
8
J
−Y−
5
DETAIL E
B
L
1
4
R
S
G
P
U
DIM
A
B
C
D
F
G
H
J
K
L
M
N
P
R
S
U
V
C
−T−
SEATING
PLANE
D
H
0.10 (0.004) T
K
N
0.10 (0.004)
M
T X Y
R 0.10 TYP
V
M
F
DETAIL E
MILLIMETERS
MIN
MAX
1.90
2.10
2.20
2.40
0.60
0.90
0.17
0.25
0.20
0.35
0.50 BSC
0.40 REF
0.10
0.18
0.00
0.10
3.00
3.20
0_
6_
5_
10 _
0.23
0.34
0.23
0.33
0.37
0.47
0.60
0.80
0.12 BSC
INCHES
MIN
MAX
0.075
0.083
0.087
0.094
0.024
0.035
0.007
0.010
0.008
0.014
0.020 BSC
0.016 REF
0.004
0.007
0.000
0.004
0.118
0.126
0_
6_
5_
10 _
0.010
0.013
0.009
0.013
0.015
0.019
0.024
0.031
0.005 BSC
SOLDERING FOOTPRINT*
3.8
0.15
0.50
0.0197
1.8
0.07
0.30
0.012
1.0
0.0394
SCALE 8:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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NLAS1053/D