HIP7038A8 PRELIMINARY J1850 8-Bit 68HC05 Microcontroller 8K EEPROM Version April 1994 Features Description • Direct Replacement for HIP7030A2/A8 Microcontrollers - All Hardware and Software Features The HIP7038A8 HCMOS Microcomputer is an EEPROM version of the HIP7030A family of low-cost single-chip J1850 microcontrollers. These microcontrollers provide the system designer with a complete set of building blocks for implementing a “Class B” VPW multiplexed communications network interface, which fully complies with SAE Recommended Practice J1850. The HIP7038A8 contains all hardware and software features of the HIP7030A2/A8 microcontrollers with equivalent timing, performance characteristics, and an identical footprint. - Equivalent Timing and Performance • Memory - 176 Bytes of RAM - 7744 Bytes of Programmable EEPROM - 242 Bytes of Bootstrap Program • Single 5V Supply • 10MHz Operating Frequency (5.0MHz Internal Bus Frequency) at 5V. • 28 Lead Small Outline Ceramic Package - Same Terminal Assignment as HIP7030A2 and HIP7030A8 The device can be programmed using the HIP7038A8 EEPROM Programmer available from Intersil. In-circuit Emulation Tools are also provided for system development. Ordering Information PART NUMBER HIP7038A8F TEMPERATURE RANGE PACKAGE -40oC to +85oC 28 Lead Ceramic SOIC Pinout HIP7038A8 (SOIC FLATPACK) TOP VIEW TCAP 1 28 SS TCMP 2 27 MISO VPWIN 3 26 MOSI VPWOUT 4 25 SCK RESET 5 24 OSCIN IRQ 6 23 OSCOUT VDD 7 22 VSS PA7 8 21 PD0 PA6 9 20 PD1 PA5 10 19 PD2, V2 PA4 11 18 PD3, V3 PA3 12 17 PD4, VREF PA2 13 16 OSCB PA1 14 15 PA0 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 407-727-9207 | Copyright © Intersil Corporation 1999 9-99 File Number 3647.1 HIP7038A8 Block Diagram INTERNAL OSCIN PROCESSOR 24 CLOCK TCMP OSCOUT 23 2 PORT A I/O LINES TCAP PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 1 15 14 13 12 11 10 9 8 OSCILLATOR AND ÷ 2 TIMER SYSTEM PORT D I/O LINES PD0 PD1 PD2, V2 PD3, V3 PD4, VR 20 19 18 17 OSCB PORT A REG DATA DIR REG 8 PORT D REG + - + - PORT D SFR REG PORT D DIR REG 6 A INDEX REGISTER CONDITION CODE REGISTER STACK POINTER 5 8 PROGRAM COUNTER LOW PCL TCAP CPU CONTROL IRQ 4 VPW SYMBOL ENCODER / DECODER AND ARBITRATION CPU 242 x 8 BUILT-IN-TEST EEPROM 9-100 26 27 28 ALU INTERNAL PROCESSOR CLOCK VSS 22 VDD 7 7744 x 8 EEPROM 3 25 SPI SYSTEM S PROGRAM COUNTER HIGH PCH RESET SYMBOL INT X CC 5 6 ACCUMULATOR 8 5 21 16 176 x 8 STATIC RAM WATCHDOG AND SLOW CLOCK DETECT VPWOUT VPWIN SCK MOSI MISO SS Specifications HIP7038A8 Absolute Maximum Ratings Thermal Information Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V Input or Output Voltage Pins with VDD Diode . . . . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V Pins without VDD Diode. . . . . . . . . . . . . . . . . . . . . -0.3V to +10.0V Current Drain Per Pin, I (Excluding VDD and VSS) . . . . . . . . 25mA ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2 Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21000 Gates Operating Temperature Range (TA) . . . . . . . . . . . . -40oC to +125oC Storage Temperature Range (TSTG) . . . . . . . . . . . . -65oC to +150oC Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . +265oC 1/16in. ± 1/32in. (1.59 ± 0.79mm) from case for 10s Max. CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Operating Conditions Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range . . . . . . . . . . . . . . . . . -40oC to +85oC Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V DC Electrical Specifications PARAMETERS Input High Voltage. . . . . . . . . . . . . . . . . . . . . . . . . .(0.8•VDD) to VDD Input Rise and Fall Time CMOS Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ns Max. CMOS Schmitt Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . .Unlimited VDD = 5VDC ±10%, VSS = 0VDC , TA = -40oC to +85oC Unless Otherwise Specified. SYMBOL CONDITIONS MIN TYP MAX UNITS SUPPLY CURRENT RUN IRUN - 50 - mA WAIT IWAIT - 4 - mA STOP ISTOP TA = +25oC - 100 - µA TA = -40oC to +85oC - 100 - µA -0.3 - 9 V Powerdown Input Voltage: RESET, IRQ, VPWIN, OSCIN VINPD VDD = 0 NOTE: 1. This device contains circuitry to protect the inputs against damage due to high static voltages of electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation it is recommended that VIN and VOUT be constrained to the range VSS<(VIN or VOUT)<VDD. Reliability of operation is enhanced if unused inputs except OSC2 are connected to an appropriate logic voltage level (e.g., either VSS or VDD). 9-101 HIP7038A8 Functional Description Memory Organization The HIP7038A8 MCU is functionally identical to the HIP7030A2 and HIP7030A8 microcontrollers. The device differs only in that the on-board masked ROM has been replaced with EEPROM, which allows the device to be rapidly programmed by the user. For detailed information about the functions included on the HIP7038A8 refer to File Number 3646, the technical specification of the HIP7030A2 Microcontroller. Only differences are presented here. The HIP7038A8 MCU addresses 8192 bytes of memory and I/O registers with its program counter. Of these locations, 8184 have been implemented as shown in Figure 1. The first 256 bytes of memory (page zero) include: 24 bytes of I/O features such as data ports, the port DDRs, Timer, serial peripheral interface (SPI), and J1850 VPW Registers; 48 bytes of user ROM, and 176 bytes of RAM. The next 7680 bytes complete the user ROM. The Built-In-Test ROM (242 bytes) is contained in memory locations $1F00 through $1FF1. The 14 highest address bytes contain the user defined reset and the interrupt vectors. Eight bytes of the lowest 32 memory locations are unused and the 176 bytes of user RAM include up to 64 bytes for the stack. Since most programs use only a small part of the allocated stack locations for interrupts and/or subroutine stacking purposes, the unused bytes are usable for program data storage. The availability of the HIP7038A8 dramatically reduces the time-to-market of new products by providing the development engineer rapid feedback during the design phase of a HIP7030A2/8 project. The EEPROM is reusable and can be reprogrammed up to 104 times. 0000 $0000 PORTS 1 BYTE I/O 32 BYTES UNUSED 2 BYTES PORTS 2 BYTES UNUSED $05 PORTS 2 BYTES UNUSED $06 PORT D DATA DIRECTION REGISTER $07 UNUSED 1 BYTE PORT D SPECIAL FUNCTION REGISTER $08 SERIAL PERIPHERAL INTERFACE 3 BYTES UNUSED $09 SERIAL PERIPHERAL CONTROL REGISTER $0A SERIAL PERIPHERAL STATUS REGISTER $0B UNUSED 2 BYTES SERIAL PERIPHERAL DATA I/O REGISTER $0C SENDEC INTERFACE 3 BYTES UNUSED $0D UNUSED $0E TIMER 10 BYTES SENDEC CONTROL REGISTER $0F SENDEC STATUS REGISTER $10 0255 0256 UNUSED 1 BYTE TEST 1 BYTE USER ROM 7680 BYTES WATCHDOG 2 BYTES 0031 7935 7936 $1EFF $1F00 SENDEC DATA REGISTER $11 TIMER CONTROL REGISTER $12 TIMER STATUS REGISTER $13 INPUT CAPTURE HIGH REGISTER $14 INPUT CAPTURE LOW REGISTER $15 OUTPUT COMPARE HIGH REGISTER $16 OUTPUT COMPARE LOW REGISTER $17 COUNTER HIGH REGISTER $18 COUNTER LOW REGISTER $19 ALTERNATE COUNTER HIGH REGISTER $1A ALTERNATE COUNTER LOW REGISTER $1B UNUSED $1C BUILT-IN-TEST $1FE1 $1FE2 256 BYTES BUILT-IN-TEST VECTORS $1FF1 $1FF2 $1FFF USER VECTORS 14 BYTES $02 $04 STACK 64 BYTES $00FF $0100 $01 UNUSED UNUSED 2 BYTES 0191 0192 $00BF $00C0 UNUSED $03 0079 0080 RAM 176 BYTES $00 PORT D DATA REGISTER USER ROM 48 BYTES $004F $0050 PORT A DATA REGISTER PORT A DATA DIRECTION REGISTER 0031 0032 $001F $0020 0000 8177 8178 WATCHDOG RESET REGISTER $1D WATCHDOG STATUS REGISTER $1E 8191 TEST REGISTER (SEE NOTE) $1F NOTE: Accessable in test mode only. FIGURE 1. MEMORY MAP OF THE HIP7038A8 9-102 HIP7038A8 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. 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