NCV4269 5.0 V Micropower 150 mA LDO Linear Regulator with DELAY, Adjustable RESET, and Sense Output The NCV4269 is a 5.0 V precision micropower voltage regulator with an output current capability of 150 mA. The output voltage is accurate within ±2.0% with a maximum dropout voltage of 0.5 V at 100 mA. Low quiescent current is a feature drawing only 240 mA with a 1.0 mA load. This part is ideal for any and all battery operated microprocessor equipment. Microprocessor control logic includes an active reset output RO with delay and a SI/SO monitor which can be used to provide an early warning signal to the microprocessor of a potential impending reset signal. The use of the SI/SO monitor allows the microprocessor to finish any signal processing before the reset shuts the microprocessor down. The active Reset circuit operates correctly at an output voltage as low as 1.0 V. The Reset function is activated during the power up sequence or during normal operation if the output voltage drops outside the regulation limits. The reset threshold voltage can be decreased by the connection of an external resistor divider to the RADJ lead. The regulator is protected against reverse battery, short circuit, and thermal overload conditions. The device can withstand load dump transients making it suitable for use in automotive environments. The device has also been optimized for EMC conditions. • • • • • • • 5.0 V ± 2.0% Output Low 240 mA Quiescent Current Active Reset Output Low Down to VQ = 1.0 V Adjustable Reset Threshold 150 mA Output Current Capability Fault Protection ♦ +60 V Peak Transient Voltage ♦ −40 V Reverse Voltage ♦ Short Circuit ♦ Thermal Overload Early Warning through SI/SO Leads Internally Fused Leads in SO−14 and SO−20L Packages Integrated Pullup Resistor at Logic Outputs (To Use External Resistors, Select the NCV4279) Very Low Dropout Voltage Electrical Parameters Guaranteed Over Entire Temperature Range NCV Prefix for Automotive and Other Applications Requiring Site and Control Changes Pb−Free Packages are Available © Semiconductor Components Industries, LLC, 2007 February, 2007 − Rev. 10 MARKING DIAGRAMS 8 SO−8 D SUFFIX CASE 751 8 1 4269 ALYW G 1 8 8 1 SO−8 EXPOSED PAD D SUFFIX CASE 751AC V4269 ALYW G 1 14 SO−14 D SUFFIX CASE 751A 14 1 NCV4269 AWLYWWG 1 20 20 Features • • • • • • http://onsemi.com 1 NCV4269 AWLYYWWG 1 SO−20L DW SUFFIX CASE 751D A WL, L YY, Y WW, W G, G 1 = Assembly Location = Wafer Lot = Year = Work Week = Pb Free ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 12 of this data sheet. Publication Order Number: NCV4269/D NCV4269 I Q Error Amplifier Current and Saturation Control Reference and Trim RSO RRO RO D or Reference SO RADJ + SI − GND Figure 1. Block Diagram PIN CONNECTIONS 1 I 1 8 SI RADJ D GND GND GND GND RO Q SO RO RADJ D GND SO−8 1 20 SI I NC GND GND GND GND NC Q SO RADJ D NC GND GND GND GND NC NC RO 14 SI I GND GND GND Q SO SO−14 SO−20L PACKAGE PIN DESCRIPTION Package Pin Number SO−8 SO−14 SO−20L Pin Symbol 3 1 1 RADJ 4 2 2 D 5 3, 4, 5, 6, 10, 11, 12 4, 5, 6, 7, 14, 15, 16, 17 GND − − 3, 8, 9, 13, 18 NC No connection to these pins from the IC. 6 7 10 RO Reset Output; The Open−Collector Output has a 20 kW Pullup Resistor to Q. Leave Open if Not Used. 7 8 11 SO Sense Output; This Open−Collector Output is Internally Pulled Up by 20 kW pullup resistor to Q. If not used, keep open. 8 9 12 Q 5 V Output; Connect to GND with a 10 mF Capacitor, ESR < 10 W. 1 13 19 I Input; Connect to GND Directly at the IC with a Ceramic Capacitor. 2 14 20 SI Function Reset Threshold Adjust; if not used to connect to GND. Reset Delay; To Set Time Delay, Connect to GND with Capacitor Ground Sense Input; If not used, Connect to Q. http://onsemi.com 2 NCV4269 MAXIMUM RATINGS (TJ = −40°C to 150°C) Parameter Input to Regulator Symbol Min Max Unit VI II −40 Internally Limited 45 Internally Limited V Input Transient to Regulator VI − 60 V Sense Input VSI ISI −40 −1 45 1 V mA VRADJ IRADJ −0.3 −10 7 10 V mA Reset Delay VD ID −0.3 Internally Limited 7 Internally Limited V Ground Iq 50 − mA Reset Output VRO IRO −0.3 Internally Limited 7 Internally Limited V Sense Output VSO ISO −0.3 Internally Limited 7 Internally Limited V Regulated Output VQ IQ −0.5 −10 7.0 − V mA TJ TSTG − −50 150 150 °C °C VI TJ − −40 45 150 V °C Reset Threshold Adjust Junction Temperature Storage Temperature Input Voltage Operating Range Junction Temperature Operating Range Lead Temperature Soldering and MSL Parameter Symbol Value MSL, 20−Lead LS Temperature 265°C Peak (Note 3) MSL 3 MSL, 20−Lead, LS Temperature 240°C Peak (Note 4) MSL 1 MSL, 8−Lead, 14−Lead, LS Temperature 265°C Peak (Note 3) MSL 1 MSL, 8−Lead EP, LS Temperature 260°C MSL 2 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. This device series incorporates ESD protection and exceeds the following ratings: Human Body Model (HBM) ≤ 2.0 kV per JEDEC standard: JESD22–A114. Machine Model (MM) ≤ 200 V per JEDEC standard: JESD22–A115. 2. Latchup Current Maximum Rating: ≤ 150 mA per JEDEC standard: JESD78. 3. +5°C/−0°C, 40 Sec Max−at−Peak, 60 − 150 Sec above 217°C. 4. +5°C/−0°C, 30 Sec Max−at−Peak, 60 − 150 Sec above 183°C. THERMAL CHARACTERISTICS Characteristic Test Conditions (Typical Values) Unit Junction−to−Pin 4 ( Y − JL4, YL4) 53.8 °C/W Junction−to−Ambient Thermal Resistance (RqJA, qJA) 170.9 °C/W Junction−to−Pin 8 ( Y − JL8, YL8) 23.7 °C/W Junction−to−Ambient Thermal Resistance (RqJA, qJA) 71.4 °C/W Junction−to−Pad ( Y − JPad) 7.7 °C/W Junction−to−Pin 4 ( Y − JL4, YL4) 18.4 °C/W Junction−to−Ambient Thermal Resistance (RqJA, qJA) 111.6 °C/W Junction−to−Pin 4 ( Y − JL4, YL4) 21.8 °C/W Junction−to−Ambient Thermal Resistance (RqJA, qJA) 95.3 °C/W SO−8 Package (Note 5) SO−8 EP Package (Note 5) SO−14 Package (Note 5) SO−20 Package (Note 5) 5. 2 oz copper, 50 mm2 copper area, 1.5 mm thick FR4 http://onsemi.com 3 NCV4269 ELECTRICAL CHARACTERISTICS (TJ = −40°C ≤ TJ ≤ 125°C, VI = 13.5 V unless otherwise specified) Characteristic Symbol Test Conditions Min Typ Max Unit Output Voltage VQ 1 mA v IQ v 100 mA 6 V v VI v 16 V 4.90 5.00 5.10 V Current Limit IQ − 150 200 500 mA Current Consumption; Iq = II – IQ Iq IQ = 1 mA, RO, SO High − 240 250 mA Current Consumption; Iq = II – IQ Iq IQ = 10 mA, RO, SO High − 250 450 mA Current Consumption; Iq = II – IQ Iq IQ = 50 mA, RO, SO High − 2.0 3.0 mA Dropout Voltage Vdr VI = 5 V, IQ = 100 mA − 0.25 0.5 V Load Regulation DVQ IQ = 5 mA to 100 mA − 10 20 mV Line Regulation DVQ VI = 6 V to 26 V IQ = 1 mA − 10 30 mV VRT − 4.50 4.65 4.80 V VRAD,JTH VQ > 3.5 V 1.26 1.35 1.44 V Reset Pullup Resistance RSO,INT − 10 20 40 kW Reset Output Saturation Voltage VRO,SAT VQ < VRT, RRO, INT − 0.1 0.4 V Upper Delay Switching Threshold VUD − 1.4 1.8 2.2 V Lower Delay Switching Threshold VLD − 0.3 0.45 0.60 V VD,SAT VQ < VRT − − 0.1 V Charge Current ID VD = 1 V 3.0 6.5 9.5 mA Delay Time L ³ H td CD = 100 nF 17 28 − ms Delay Time H ³ L tt CD = 100 nF − 1.0 − ms Sense Threshold High VSI,High − 1.24 1.31 1.38 V Sense Threshold Low VSI,Low − 1.16 1.20 1.28 V Sense Output Saturation Voltage VSO,Low VSI < 1.20 V; VQ > 3 V; RSO − 0.1 0.4 V Sense Resistor Pullup RSO,INT − 10 20 40 kW ISI − −1.0 0.1 1.0 mA REGULATOR RESET GENERATOR Reset Switching Threshold Reset Adjust Switching Threshold Saturation Voltage on Delay Capacitor INPUT VOLTAGE SENSE Sense Input Current http://onsemi.com 4 NCV4269 II I CI 470 nF 1000 mF IQ Q CQ 22 mF RADJ1 ISI VI SI D GND ID VSI RADJ SO RO Iq VRO IRADJ VQ VSO VRADJ VD CD 100 nF RADJ2 Figure 2. Measuring Circuit VI t < tRR VQ VRT t dV I + D dt CD VD VUD VLD t td tRR VRO VROSAT t Power−on−Reset Thermal Shutdown Voltage Dip at Input Undervoltage Figure 3. Reset Timing Diagram http://onsemi.com 5 Secondary Spike Overload at Output NCV4269 Sense Input Voltage VSI,HIGH VSI,LOW t Sense Output Voltage tPDSOLH tPDSOHL HIGH LOW t Figure 4. Sense Timing Diagram TYPICAL PERFORMANCE CHARACTERISTICS 16 3.2 VI = 13.5 V VD = 1.0 V 2.8 12 2.4 10 2.0 VD, (V) ID, (mA) 14 8 1.2 4 0.8 2 0.4 0 40 80 120 0 −40 160 VUD 1.6 6 0 −40 VI = 13.5 V VLD 0 40 80 120 TJ, (°C) TJ, (°C) Figure 5. Charge Current ID vs. Temperature TJ Figure 6. Switching Voltage VUD and VLD vs. Temperature TJ http://onsemi.com 6 160 NCV4269 TYPICAL PERFORMANCE CHARACTERISTICS 500 1.7 1.6 400 1.5 300 VRAD,JTH, (V) Vdr, (mV) TJ = 125°C TJ = 25°C 200 TJ = −40°C 1.4 1.3 1.2 1.1 100 1.0 0 0 30 60 90 120 150 0.9 −40 180 40 120 160 IQ, (mA) Figure 7. Drop Voltage Vdr vs. Output Current IQ Figure 8. Reset Adjust Switching Threshold, VRAD,JTH vs. Temperature TJ 35 12 30 10 8 15 VQ (V) 20 RL = 33 W RL = 100 W 10 0 0 10 6 RL = 50 W 4 RL = 200 W RL = 50 W 5 2 20 30 40 0 0 50 2 4 VI, (V) 10 5.2 VI = 13.5 V 5.1 VI = 13.5 V 1.4 5.0 VQ, (V) VSI, High 1.3 VSI, Low 4.9 1.2 4.8 1.1 4.7 1.0 −40 8 Figure 10. Output Voltage VQ vs. Input Voltage VI 1.6 1.5 6 VI, (V) Figure 9. Current Consumption Iq vs. Input Voltage VI VSI, (V) 80 TJ, (°C) 25 Iq, (mA) 0 0 40 80 120 4.6 −40 160 TJ, (°C) 0 40 80 120 160 TJ, (°C) Figure 11. Sense Threshold VSI vs. Temperature TJ Figure 12. Output Voltage VQ vs. Temperature TJ http://onsemi.com 7 NCV4269 TYPICAL PERFORMANCE CHARACTERISTICS 350 12 300 10 TJ = 25°C 8 200 Iq, (mA) IQ, (mA) 250 TJ = 125°C 150 6 4 100 2 50 0 0 10 20 30 40 0 0 50 20 40 80 60 100 120 VI, (V) IQ, (mA) Figure 13. Output Current Limit IQ vs. Input Voltage VI Figure 14. Current Consumption Iq vs. Output Current IQ 1.6 1.4 VI = 13.5 V TJ = 25°C 7 VI = 13.5 V TJ = 25°C TJ = 125°C 6 1.2 5 IQ = 100 mA Iq, (mA) Iq, (mA) 1.0 0.8 0.6 4 3 2 0.4 0.2 1 0.0 0 0 6 10 20 40 30 50 IQ = 50 mA IQ = 10 mA 8 10 12 14 16 20 22 VI, (V) Figure 15. Current Consumption Iq vs. Output Current IQ Figure 16. Quiescent Current Iq vs. Input Voltage VI 250 200 26 Stable Region for 0.1 mF to 10 mF ESR (W) 10 IQ = 100 mA 150 24 Unstable Region for all caps 100 TJ = 25°C Iq, (mA) 18 IQ, (mA) 1 Unstable Region for 0.1 mF ONLY 100 50 6 8 10 12 14 16 18 20 22 24 0.1 0 26 25 50 Stable Region for 1 mF to 10 mF 75 100 125 150 VI, (V) OUTPUT CURRENT IN MILLIAMPS Figure 17. Quiescent Current Iq vs. Input Voltage VI Figure 18. Output Stability, Capacitance ESR vs. Output Load Current http://onsemi.com 8 NCV4269 TYPICAL THERMAL CHARACTERISTICS 200 180 160 qJA (°C/W) 140 120 100 80 60 40 20 0 0 100 200 300 400 500 600 700 COPPER HEAT−SPREADER AREA (mm2) SO−8 Std Package NCV4269, 1.0 oz SO−8 Std Package NCV4269, 2.0 oz SO−14 w/6 Thermal Leads NCV4269, 1.0 oz SO−14 w/6 Thermal Leads NCV4269, 2.0 oz SO−20 w/8 Thermal Leads NCV4269, 1.0 oz SO−20 w/8 Thermal Leads NCV4269, 2.0 oz Figure 19. Junction−to−Ambient Thermal Resistance (qJA) vs. Heat Spreader Area 1000 R(t) (°C/W) 100 10 1 0.1 0.000001 0.00001 0.0001 0.001 0.01 0.1 PULSE TIME (s) Single Pulse (SO−8 Std Package) PCB = 50 mm2, 2.0 oz Single Pulse (SO−8 EP Package) Single Pulse (SO−14 w/6 Thermal Leads) PCB = 50 mm2, 2.0 oz Single Pulse (SO−20 w/8 Thermal Leads) PCB = 50 mm2, 2.0 oz YLA (SO−8) YLA (SO−14) YLA (SO−20) Figure 20. R(t) vs. Pulse Time http://onsemi.com 9 1 10 100 1000 NCV4269 APPLICATION DESCRIPTION OUTPUT REGULATOR If the reset adjust option is not needed, the RADJ pin should be connected to GND causing the reset threshold to go to its default value (typically 4.65 V). The output is controlled by a precision trimmed reference. The PNP output has base drive quiescent current control for regulation while the input voltage is low, preventing over saturation. Current limit and voltage monitors complement the regulator design to give safe operating signals to the processor and control circuits. RESET DELAY (D) The reset delay circuit provides a delay (programmable by capacitor CD) on the reset output lead RO. The delay lead D provides charge current ID (typically 6.5 mA) to the external delay capacitor CD during the following times: 1. During Powerup (once the regulation threshold has been exceeded). 2. After a reset event has occurred and the device is back in regulation. The delay capacitor is set to discharge when the regulation (VRT, reset threshold voltage) has been violated. When the delay capacitor discharges to VLD, the reset signal RO pulls low. RESET OUTPUT (RO) A reset signal, Reset Output, RO, (low voltage) is generated as the IC powers up. After the output voltage VQ increases above the reset threshold voltage VRT, the delay timer D is started. When the voltage on the delay timer VD passes VUD, the reset signal RO goes high. A discharge of the delay timer VD is started when VQ drops and stays below the reset threshold voltage VRT. When the voltage of the delay timer VD drops below the lower threshold voltage VLD the reset output voltage VRO is brought low to reset the processor. The reset output RO is an open collector NPN transistor with an internal 20 kW pullup resistor connected to the output Q, controlled by a low voltage detection circuit. The circuit is functionally independent of the rest of the IC, thereby guaranteeing that RO is valid for VQ as low as 1.0 V. SETTING THE DELAY TIME The delay time is set by the delay capacitor CD and the charge current ID. The time is measured by the delay capacitor voltage charging from the low level of VDSAT to the higher level VUD. The time delay follows the equation: td + [CD (VUD * VDSAT)]ńID Example: Using CD = 100 nF. Use the typical value for VDSAT = 0.1 V. Use the typical value for VUD = 1.8 V. Use the typical value for Delay Charge Current ID = 6.5 mA. RESET ADJUST (RADJ) The reset threshold VRT can be decreased from a typical value of 4.65 V to as low as 3.5 V by using an external voltage divider connected from the Q lead to the pin RADJ, as shown in Figure 21. The resistor divider keeps the voltage above the VRADJ,TH (typical 1.35 V) for the desired input voltages, and overrides the internal threshold detector. Adjust the voltage divider according to the following relationship: VRT + VRADJ, TH @ (RADJ1 ) RADJ2) ń RADJ2 I CI* td + [100 nF (1.8 * 0.1 V)] ń 6.5 mA + 26.2 ms (eq. 3) (eq. 1) Q VDD CQ** 10 mF RADJ1 0.1 mF RADJ RADJ2 NCV4269 D Microprocessor VBAT RSI1 SI RSI2 CD RO SO (eq. 2) I/O GND *CI required if regulator is located far from the power supply filter. ** CQ required for Stability. Cap must operate at minimum temperature expected. Figure 21. Application Diagram http://onsemi.com 10 I/O NCV4269 SENSE INPUT (SI) / SENSE OUTPUT (SO) VOLTAGE MONITOR instability. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (−25°C to −40°C), both the value and ESR of the capacitor will vary considerably. The capacitor manufacturer’s data sheet usually provides this information. The value for the output capacitor CQ shown in Figure 21 should work for most applications; however, it is not necessarily the optimized solution. Stability is guaranteed at values CQ = 10 mF and an ESR = 10 W within the operating temperature range. Actual limits are shown in a graph in the typical data section. An on−chip comparator is available to provide early warning to the microprocessor of a possible reset signal. The output is from an open collector driver with an internal 20 kW pull up resistor to output Q. The reset signal typically turns the microprocessor off instantaneously. This can cause unpredictable results with the microprocessor. The signal received from the SO pin will allow the microprocessor time to complete its present task before shutting down. This function is performed by a comparator referenced to the band gap voltage. The actual trip point can be programmed externally using a resistor divider to the input monitor SI (Figure 21). The values for RSI1 and RSI2 are selected for a typical threshold of 1.20 V on the SI Pin. CALCULATING POWER DISSIPATION IN A SINGLE OUTPUT LINEAR REGULATOR The maximum power dissipation for a single output regulator (Figure 21) is: SIGNAL OUTPUT PD(max) + [VI(max) * VQ(min)] IQ(max) ) VI(max) Iq (eq. 4) Figure 22 shows the SO Monitor timing waveforms as a result of the circuit depicted in Figure 21. As the output voltage (VQ) falls, the monitor threshold (VSILOW), is crossed. This causes the voltage on the SO output to go low sending a warning signal to the microprocessor that a reset signal may occur in a short period of time. TWARNING is the time the microprocessor has to complete the function it is currently working on and get ready for the reset shutdown signal. where: VI(max) is the maximum input voltage, VQ(min) is the minimum output voltage, IQ(max) is the maximum output current for the application, and Iq is the quiescent current the regulator consumes at IQ(max). Once the value of PD(max) is known, the maximum permissible value of RqJA can be calculated: RqJA = (150°C – TA) / PD VQ (eq. 5) The value of RqJA can then be compared with those in the package section of the data sheet. Those packages with RqJA’s less than the calculated value in equation 2 will keep the die temperature below 150°C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required. The current flow and voltages are shown in the Measurement Circuit Diagram. SI VSILOW VRO HEATSINKS A heatsink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of RqJA: SO TWARNING Figure 22. SO Warning Waveform Time Diagram RqJA + RqJC ) RqCS ) RqSA STABILITY CONSIDERATIONS The input capacitor CI in Figure 21 is necessary for compensating input line reactance. Possible oscillations caused by input inductance and input capacitance can be damped by using a resistor of approximately 1.0 W in series with CI. The output or compensation capacitor helps determine three main characteristics of a linear regulator: startup delay, load transient response and loop stability. The capacitor value and type should be based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR can cause (eq. 6) where: RqJC = the junction−to−case thermal resistance, RqCS = the case−to−heat sink thermal resistance, and RqSA = the heat sink−to−ambient thermal resistance. RqJC appears in the package section of the data sheet. Like RqJA, it too is a function of package type. RqCS and RqSA are functions of the package type, heatsink and the interface between them. These values appear in data sheets of heatsink manufacturers. Thermal, mounting, and heatsinking considerations are discussed in the ON Semiconductor application note AN1040/D, available on the ON Semiconductor website. http://onsemi.com 11 NCV4269 ORDERING INFORMATION Device Output Voltage Package NCV4269D1 Shipping † SO−8 NCV4269D1G SO−8 (Pb−Free) NCV4269D1R2 SO−8 98 Units/Rail 2500 Tape & Reel NCV4269D1R2G SO−8 (Pb−Free) NCV4269PDG SO−8 EP (Pb−Free) 98 Units/Rail NCV4269PDR2G SO−8 EP (Pb−Free) 2500 Tape & Reel NCV4269D2 NCV4269D2G SO−14 5.0 V SO−14 (Pb−Free) NCV4269D2R2 55 Units/Rail SO−14 NCV4269D2R2G SO−14 (Pb−Free) NCV4269DW 2500 Tape & Reel SO−20L NCV4269DWG SO−20L (Pb−Free) NCV4269DWR2 SO−20L NCV4269DWR2G SO−20L (Pb−Free) 38 Units/Rail 1000 Tape & Reel †For information on tape and reel specifications,including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 12 NCV4269 PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AH NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. −X− A 8 5 0.25 (0.010) S B 1 M Y M 4 K −Y− G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M J S SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 13 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8 _ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 NCV4269 PACKAGE DIMENSIONS SOIC−8 EP CASE 751AC−01 ISSUE B 2X NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS (ANGLES IN DEGREES). 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 MM TOTAL IN EXCESS OF THE “b” DIMENSION AT MAXIMUM MATERIAL CONDITION. 4. DATUMS A AND B TO BE DETERMINED AT DATUM PLANE H. 0.10 C A−B D 8 E1 2X 0.10 C D PIN ONE LOCATION DETAIL A D A 5 ÉÉÉ ÉÉÉ ÉÉÉ 1 F EXPOSED PAD 5 8 G E h 2X 0.20 C 4 e 4 8X b 0.25 C A−B D B 1 BOTTOM VIEW A END VIEW TOP VIEW 0.10 C A2 0.10 C SEATING PLANE C b1 GAUGE PLANE SIDE VIEW ÇÇ ÉÉ ÉÉ ÇÇ ÉÉ ÇÇ c H A 8X A A1 L 0.25 (L1) DETAIL A q c1 (b) SECTION A−A SOLDERING FOOTPRINT* 2.72 0.107 1.52 0.060 7.0 0.275 Exposed Pad 4.0 0.155 2.03 0.08 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 14 DIM A A1 A2 b b1 c c1 D E E1 e L L1 F G h q MILLIMETERS MIN MAX 1.35 1.75 0.00 0.10 1.35 1.65 0.31 0.51 0.28 0.48 0.17 0.25 0.17 0.23 4.90 BSC 6.00 BSC 3.90 BSC 1.27 BSC 0.40 1.27 1.04 REF 2.24 3.20 1.55 2.51 0.25 0.50 0_ 8_ NCV4269 PACKAGE DIMENSIONS SO−14 D SUFFIX CASE 751A−03 ISSUE G NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. −A− 14 8 −B− 1 P 7 PL 0.25 (0.010) 7 G M B M F R X 45 _ C −T− SEATING PLANE D 14 PL 0.25 (0.010) M T B J M K S A S http://onsemi.com 15 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 NCV4269 −PACKAGE DIMENSIONS SO−20L DW SUFFIX CASE 751D−05 ISSUE G q A 20 X 45 _ h H M E 0.25 10X NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. 11 B M D 1 10 20X B B 0.25 M T A S B S L A 18X e A1 SEATING PLANE C T DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ SMART REGULATOR is a registered trademark of Semiconductor Components Industries, LLC (SCILLIC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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