CS8129 5.0 V, 750 mA Low Dropout Linear Regulator with Lower RESET Threshold The CS8129 is a precision 5.0 V linear regulator capable of sourcing 750 mA. The RESET threshold voltage has been lowered to 4.2 V so that the regulator can be used with 4.0 V microprocessors. The lower RESET threshold also permits operation under low battery conditions (5.5 V plus a diode). The RESET’s delay time is externally programmed using a discrete RC network. During powerup, or when the output goes out of regulation, RESET remains in the low state for the duration of the delay. This function is independent of the input voltage and will function correctly as long as the output voltage remains at or above 1.0 V. Hysteresis is included in the Delay and the RESET comparators to improve noise immunity. A latching discharge circuit is used to discharge the delay capacitor when it is triggered by a brief fault condition. The regulator is protected against a variety of fault conditions: i.e. reverse battery, overvoltage, short circuit and thermal runaway conditions. The regulator is protected against voltage transients ranging from −50 V to +40 V. Short circuit current is limited to 1.2 A (typ). The CS8129 is packaged in a 5 lead TO−220 and a 16 lead surface mount package. http://onsemi.com TO−220 FIVE LEAD T SUFFIX CASE 314D 1 • TO−220 FIVE LEAD TVA SUFFIX CASE 314K 1 1 Features • • • • • • 5.0 V ±3.0% Regulated Output Low Dropout Voltage (0.6 V @ 0.5 A) 750 mA Output Current Capability Reduced RESET Threshold for Use with 4.0 V Microprocessors Externally Programmed RESET Delay Fault Protection − Reverse Battery − 60 V, −50 V Peak Transient Voltage − Short Circuit − Thermal Shutdown Pb−Free Packages are Available* 5 TO−220 FIVE LEAD THA SUFFIX CASE 314A 5 SO−16WB DW SUFFIX CASE 751G 16 1 ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. DEVICE MARKING INFORMATION See general marking information in the device marking section on page 8 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 June, 2006 − Rev. 8 1 Publication Order Number: CS8129/D CS8129 PIN CONNECTIONS TO−220 5−LEAD Pin 1. VIN 2. RESET 3. GND 4. Delay 5. VOUT VIN NC NC GND GND RESET NC Delay 1 SO−16 WB 16 VOUT NC VOUT(SENSE) GND GND GND NC NC 1 VIN Over Voltage Shutdown VOUT Regulated Supply for Circuit Bias Pre−Regulator Bandgap Reference − + Charge Current Generator Delay Error Amplifier Anti−Saturation and Current Limit VOUT (SENSE) Thermal Shutdown Latching Discharge − Q S + R − + VDISCHARGE RESET Delay Comparator + − GND Figure 1. Block Diagram ABSOLUTE MAXIMUM RATINGS Rating Value Unit −0.5 to 26 V Internally Limited − −50, 60 V Internally Limited − 4.0 kV Junction Temperature −55 to +150 °C Storage Temperature Range −55 to +150 °C 260 peak 230 peak °C Input Operating Range Power Dissipation Peak Transient Voltage (46 V Load Dump @ 14 V VIN) Output Current Electrostatic Discharge (Human Body Model) Lead Temperature Soldering: Wave Solder (through hole styles only) (Note 1) Reflow (SMD styles only) (Note 2) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. 10 second maximum. 2. 60 seconds max above 183°C. http://onsemi.com 2 CS8129 ELECTRICAL CHARACTERISTICS (−40°C ≤ TA ≤ 125°C, −40 ≤ TJ ≤ 150°C, 6.0 ≤ VIN ≤ 26 V, 5.0 mA ≤ IOUT ≤ 500 mA, RRESET = 4.7 kW to VOUT unless otherwise noted.) (Note 3) Characteristic Test Conditions Min Typ Max Unit − 4.85 5.0 5.15 V OUTPUT STAGE (VOUT) Output Voltage Dropout Voltage IOUT = 500 mA − 0.35 0.60 V Supply Current IOUT = 10 mA IOUT = 100 mA IOUT = 500 mA − − − 2.0 6.0 55 7.0 12 100 mA mA mA Line Regulation 6.0 V ≤ VIN ≤ 26 V, IOUT = 50 mA − 5.0 50 mV Load Regulation 50 mA ≤ IOUT ≤ 500 mA, VIN = 14 V − 10 50 mV Ripple Rejection f = 120 Hz, VIN = 7.0 to 17 V, IOUT = 250 mA 54 75 − dB Current Limit − 0.75 1.20 − A Overvoltage Shutdown − 32 − 40 V Reverse Polarity Input Voltage DC VOUT ≥ −0.6 V, 10 W Load −15 −30 − V Thermal Shutdown Guaranteed by Design 150 180 210 °C Delay Charge Current VDELAY = 2.0 V 5.0 10 15 mA RESET Threshold VOUT Increasing, VRT(ON) VOUT Decreasing, VRT(OFF) 4.05 4.00 4.35 4.20 4.50 4.45 V V RESET Hysteresis VRH = VRT(ON) − VRT(OFF) 50 150 250 mV Delay Threshold Charge, VDC(HI) Discharge, VDC(LO) 3.25 2.85 3.50 3.10 3.75 3.35 V V 200 400 800 mV RESET AND DELAY FUNCTIONS Delay Hysteresis − RESET Output Voltage Low 1.0 V < VOUT < VRT(L), 3.0 kW to VOUT − 0.1 0.4 V RESET Output Leakage VOUT > VRT(H) Current − 0 10 mA Delay Capacitor Discharge Voltage Discharge Latched “ON”, VOUT > VRT − 0.2 0.5 V Delay Time CDELAY = 0.1 mF, (Note 4) 16 32 48 ms 3. To observe safe operating junction temperatures, low duty cycle pulse testing is used in tests where applicable. 4. Assuming ideal capacitor. CDelay VDelay Threshold Charge Delay Time + + CDelay 3.5 105 (typ) ICharge PACKAGE LEAD DESCRIPTION PACKAGE LEAD # SO−16WB TO−220 5 LEAD LEAD SYMBOL 1 1 VIN 16 5 VOUT Regulated 5.0 V output. 4, 5, 11, 12, 13 3 GND Ground Connection. 8 4 Delay Timing capacitor for RESET function. 6 2 RESET 14 N/A VOUT(SENSE) FUNCTION Unregulated supply voltage to IC. CMOS/TTL compatible output lead. RESET goes low whenever VOUT drops below 6.0% of it’s regulated value. Remote sensing of output voltage. http://onsemi.com 3 CS8129 TYPICAL PERFORMANCE CHARACTERISTICS 55 50 120 RLOAD = 25 W Room Temp RLOAD = 6.67 W 100 45 35 30 25 ICQ. (mA) ICQ (mA) 40 125°C 20 60 RLOAD = 10 W 40 15 25°C 10 RLOAD = 25 W 20 −40°C 5 0 80 RLOAD = NO LOAD 0 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 VIN (V) 4.5 4.5 4.0 4.0 3.5 3.5 3.0 125°C 2.5 2.0 1.0 9 10 RLOAD = 6.67 W 3.0 RLOAD = NO LOAD 2.5 1.0 −40°C 25°C 0.5 0 1 2 3 RLOAD = 10 W 0.5 4 5 6 7 8 9 0 10 0 1 2 3 Figure 4. Output Voltage vs. Input Voltage Over Temperature 100 6 7 8 9 10 100 80 40 Load Regulation (mV) 60 TEMP = 25°C 20 TEMP = −40°C 0 −20 −40 TEMP = 125°C −60 5 Figure 5. VOUT vs. VIN Over RLOAD VIN = 6−26 V 80 4 VIN (V) VIN (V) Line Reg. (mV) 8 2.0 1.5 1.5 0 7 Room Temp 5.0 VOUT (V) VOUT (V) 5.5 RLOAD = 25 W 5.0 6 Figure 3. Quiescent Current vs. Input Voltage Over Load Resistance Figure 2. Quiescent Current vs. Input Voltage Over Temperature 5.5 5 VIN (V) TEMP = −40°C 60 40 20 TEMP = 25°C 0 VIN = 14 V −20 −40 −60 TEMP = 125°C −80 −80 −100 −100 0 100 200 300 400 500 600 700 0 800 100 200 300 400 500 600 700 800 Output Current (mA) Output Current (mA) Figure 6. Line Regulation vs. Output Current Figure 7. Load Regulation vs. Output Current http://onsemi.com 4 900 800 100 90 700 80 Quiescent Current (mA) Dropout Voltage (mV) CS8129 25°C 600 500 125°C 400 300 −40°C 200 100 0 VIN = 14 V 70 25°C 125°C 60 50 40 30 20 −40°C 10 0 0 100 200 300 400 500 600 700 800 0 100 200 300 Figure 8. Dropout Voltage vs. Output Current ESR (ohms) Rejection (dB) 50 Stable Region 100 10−1 COUT = 10 mF, ESR = 1.0 W CO = 47 mF 10−2 20 COUT = 10 mF, ESR = 1.0 W 10 0 800 CO = 47/68 mF 101 60 30 700 102 70 40 600 103 COUT = 10 mF, ESR = 1.0 & 0.1 mF, ESR = 0 80 500 Figure 9. Quiescent Current vs. Output Current IOUT = 250 mA 90 400 Output Current (mA) Output Current (mA) 100 101 VOUT 102 103 104 105 106 CO = 68 mF 10−3 107 10−4 108 100 101 102 Frequency (Hz) Output Current (mA) Figure 10. Ripple Rejection Figure 11. Output Capacitor ESR VRH (1) = No Delay Capacitor (2) = With Delay Capacitor (3) = Max: RESET Voltage (1.0 V) VRT(ON) VRT(OFF) RESET 103 (1) (3) (2) VRL tDELAY DELAY VDH VDC(HI) VDC(LO) (2) VDIS Figure 12. RESET Circuit Waveform http://onsemi.com 5 CS8129 CIRCUIT DESCRIPTION The CS8129 RESET function has hysteresis on both the reset and delay comparators, a latching Delay capacitor discharge circuit, and operates down to 1.0 V. The RESET circuit output is an open collector type with ON and OFF parameters as specified. The RESET output NPN transistor is controlled by the two circuits described (see Block Diagram on page 2). condition. The circuit allows the RESET output transistor to go to the OFF (open) state only when the voltage on the Delay lead is higher than VDC(HI). VOUT VIN CIN* 100 nF RRST 4.7 kW CS8129 COUT** 10 mF to 100 mF RESET Low Voltage Inhibit Circuit Delay This circuit monitors output voltage, and when output voltage is below the specified minimum causes the RESET output transistor to be in the ON (saturation) state. When the output voltage is above the specified level, this circuit permits the RESET output transistor to go into the OFF state if allowed by the RESET Delay circuit. GND Delay 0.1 mF *CIN is required if regulator is far from the power source filter. **COUT is required for stability. Reset Delay Circuit Figure 13. Test & Application Circuit This circuit provides a programmable (by external capacitor) delay on the RESET output lead. The Delay lead provides source current to the external delay capacitor only when the “Low Voltage Inhibit” circuit indicates that output voltage is above VRT(ON). Otherwise, the Delay lead sinks current to ground (used to discharge the delay capacitor). The discharge current is latched ON when the output voltage is below VRT(OFF). The Delay capacitor is fully discharged anytime the output voltage falls out of regulation, even for a short period of time. This feature ensures that a controlled RESET pulse is generated following detection of an error The Delay time for the RESET function is calculated from the formula: Delay time + CDelay VDelay Threshold ICharge Delay time + CDelay(mF) 3.2 105 If CDelay = 0.1 mF, Delay time (ms) = 32 ms ±50%: i.e. 16 ms to 48 ms. The tolerance of the capacitor must be taken into account to calculate the total variation in the delay time. APPLICATION NOTES STABILITY CONSIDERATIONS connected in series with the capacitor will simulate the higher ESR of an aluminum capacitor. Leave the decade box outside the chamber, the small resistance added by the longer leads is negligible. Step 2: With the input voltage at its maximum value, increase the load current slowly from zero to full load while observing the output for any oscillations. If no oscillations are observed, the capacitor is large enough to ensure a stable design under steady state conditions. Step 3: Increase the ESR of the capacitor from zero using the decade box and vary the load current until oscillations appear. Record the values of load current and ESR that cause the greatest oscillation. This represents the worst case load conditions for the regulator at low temperature. Step 4: Maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. This point represents the worst case input voltage conditions. Step 5: If the capacitor is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. A smaller capacitor will usually cost less and occupy less board space. If the output oscillates within the range of expected operating conditions, repeat steps 3 and 4 with the next larger standard capacitor value. The output or compensation capacitor helps determine three main characteristics of a linear regulator: start−up delay, load transient response and loop stability. The capacitor value and type should be based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR can cause instability. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (−25°C to −40°C), both the value and ESR of the capacitor will vary considerably. The capacitor manufacturers data sheet usually provides this information. The value for the output capacitor COUT shown in Figure 13 should work for most applications, however it is not necessarily the optimized solution. To determine an acceptable value for COUT for a particular application, start with a tantalum capacitor of the recommended value and work towards a less expensive alternative part. Step 1: Place the completed circuit with a tantalum capacitor of the recommended value in an environmental chamber at the lowest specified operating temperature and monitor the outputs with an oscilloscope. A decade box http://onsemi.com 6 CS8129 IIN Step 6: Test the load transient response by switching in various loads at several frequencies to simulate its real working environment. Vary the ESR to reduce ringing. Step 7: Raise the temperature to the highest specified operating temperature. Vary the load current as instructed in step 5 to test for any oscillations. VIN Figure 14. Single Output Regulator With Key Performance Parameters Labeled HEAT SINKS A heat sink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of RqJA. The maximum power dissipation for a single output regulator (Figure 14) is: (1) RqJA + RqJC ) RqCS ) RqSA where: VIN(max) is the maximum input voltage, VOUT(min) is the minimum output voltage, IOUT(max) is the maximum output current for the application, and IQ is the quiescent current the regulator consumes at IOUT(max). Once the value of PD(max) is known, the maximum permissible value of RqJA can be calculated: 150°C * TA PD VOUT IQ CALCULATING POWER DISSIPATION IN A SINGLE OUTPUT LINEAR REGULATOR RqJA + IOUT Control Features Once the minimum capacitor value with the maximum ESR is found, a safety factor should be added to allow for the tolerance of the capacitor and any variations in regulator performance. Most good quality aluminum electrolytic capacitors have a tolerance of ± 20% so the minimum value found should be increased by at least 50% to allow for this tolerance plus the variation which will occur at low temperatures. The ESR of the capacitor should be less than 50% of the maximum allowable ESR found in step 3 above. PD(max) + NJVIN(max) * VOUT(min)NjIOUT(max) ) VIN(max)IQ SMART REGULATOR® (3) where: RqJC = the junction−to−case thermal resistance, RqCS = the case−to−heatsink thermal resistance, and RqSA = the heatsink−to−ambient thermal resistance. RqJC appears in the package section of the data sheet. Like RqJA, it too is a function of package type. RqCS and RqSA are functions of the package type, heatsink and the interface between them. These values appear in heat sink data sheets of heat sink manufacturers. (2) The value of RqJA can then be compared with those in the package section of the data sheet. Those packages with RqJA’s less than the calculated value in equation 2 will keep the die temperature below 150°C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required. http://onsemi.com 7 CS8129 MARKING DIAGRAMS SO−16 WB TO−220 5−LEAD 16 CS8129 AWLYYWWG CS 8129 AWLYWWG CS 8129 AWLYWWG CS8129 AWLYWWG 1 1 1 1 A WL YY, Y WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package ORDERING INFORMATION Device Package CS8129YT5 TO−220* STRAIGHT CS8129YT5G TO−220* STRAIGHT (Pb−Free) CS8129YTHA5 TO−220* HORIZONTAL CS8129YTHA5G TO−220* HORIZONTAL (Pb−Free) CS8129YTVA5 TO−220* VERTICAL CS8129YTVA5G TO−220* VERTICAL (Pb−Free) CS8129YDW16 SO−16WB CS8129YDW16G SO−16WB (Pb−Free) CS8129YDWR16 SO−16WB CS8129YDWR16G SO−16WB (Pb−Free) Shipping † 50 Units / Rail 47 Units / Rail 1000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 8 CS8129 PACKAGE DIMENSIONS TO−220 CASE 314D−04 ISSUE F −T− B −Q− DETAIL A−A B1 SEATING PLANE C E A U L J H G D DIM A B B1 C D E G H J K L Q U 1234 5 K 5 PL 0.356 (0.014) M T Q NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION D DOES NOT INCLUDE INTERCONNECT BAR (DAMBAR) PROTRUSION. DIMENSION D INCLUDING PROTRUSION SHALL NOT EXCEED 10.92 (0.043) MAXIMUM. M B B1 DETAIL A−A http://onsemi.com 9 INCHES MIN MAX 0.572 0.613 0.390 0.415 0.375 0.415 0.170 0.180 0.025 0.038 0.048 0.055 0.067 BSC 0.087 0.112 0.015 0.025 0.977 1.045 0.320 0.365 0.140 0.153 0.105 0.117 MILLIMETERS MIN MAX 14.529 15.570 9.906 10.541 9.525 10.541 4.318 4.572 0.635 0.965 1.219 1.397 1.702 BSC 2.210 2.845 0.381 0.635 24.810 26.543 8.128 9.271 3.556 3.886 2.667 2.972 CS8129 PACKAGE DIMENSIONS TO−220 TVA SUFFIX CASE 314K−01 ISSUE O −T− SEATING PLANE C B −Q− E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION D DOES NOT INCLUDE INTERCONNECT BAR (DAMBAR) PROTRUSION. DIMENSION D INCLUDING PROTRUSION SHALL NOT EXCEED 10.92 (0.043) MAXIMUM. DIM A B C D E F G J K L M Q R S U W W A U F L 1 2 3 4 K 5 M D 0.356 (0.014) M J 5 PL T Q G M INCHES MIN MAX 0.560 0.590 0.385 0.415 0.160 0.190 0.027 0.037 0.045 0.055 0.530 0.545 0.067 BSC 0.014 0.022 0.785 0.800 0.321 0.337 0.063 0.078 0.146 0.156 0.271 0.321 0.146 0.196 0.460 0.475 5° MILLIMETERS MIN MAX 14.22 14.99 9.78 10.54 4.06 4.83 0.69 0.94 1.14 1.40 13.46 13.84 1.70 BSC 0.36 0.56 19.94 20.32 8.15 8.56 1.60 1.98 3.71 3.96 6.88 8.15 3.71 4.98 11.68 12.07 5° S R TO−220 THA SUFFIX CASE 314A−03 ISSUE E −T− B −P− Q C E OPTIONAL CHAMFER A U F L G 5X K 5X S D 0.014 (0.356) NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION D DOES NOT INCLUDE INTERCONNECT BAR (DAMBAR) PROTRUSION. DIMENSION D INCLUDING PROTRUSION SHALL NOT EXCEED 0.043 (1.092) MAXIMUM. SEATING PLANE M T P M http://onsemi.com 10 J DIM A B C D E F G J K L Q S U INCHES MIN MAX 0.572 0.613 0.390 0.415 0.170 0.180 0.025 0.038 0.048 0.055 0.570 0.585 0.067 BSC 0.015 0.025 0.730 0.745 0.320 0.365 0.140 0.153 0.210 0.260 0.468 0.505 MILLIMETERS MIN MAX 14.529 15.570 9.906 10.541 4.318 4.572 0.635 0.965 1.219 1.397 14.478 14.859 1.702 BSC 0.381 0.635 18.542 18.923 8.128 9.271 3.556 3.886 5.334 6.604 11.888 12.827 CS8129 PACKAGE DIMENSIONS SO−16 WB CASE 751G−03 ISSUE C A D q 9 h X 45 _ H E 0.25 8X M B M 16 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. 1 MILLIMETERS DIM MIN MAX A 2.35 2.65 A1 0.10 0.25 B 0.35 0.49 C 0.23 0.32 D 10.15 10.45 E 7.40 7.60 e 1.27 BSC H 10.05 10.55 h 0.25 0.75 L 0.50 0.90 q 0_ 7_ 8 16X M 14X e T A S B S L A 0.25 B B A1 SEATING PLANE C T PACKAGE THERMAL DATA Parameter TO−220 FIVE LEAD SO−16WB Unit RqJC Typical 2.1 23 °C/W RqJA Typical 50 105 °C/W SMART REGULATOR is a registered trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 http://onsemi.com 11 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative CS8129/D