ONSEMI NTHD2102P

NTHD2102P
Power MOSFET
−8.0 V, −4.6 A Dual P−Channel ChipFET
Features
• Offers an Ultra Low RDS(on) Solution in the ChipFET Package
• Miniature ChipFET Package 40% Smaller Footprint than TSOP−6
•
•
•
•
•
making it an Ideal Device for Applications where Board Space is at a
Premium
Low Profile (<1.1 mm) Allows it to Fit Easily into Extremely Thin
Environments such as Portable Electronics
Designed to Provide Low RDS(on) at Gate Voltage as Low as 1.8 V, the
Operating Voltage used in many Logic ICs in Portable Electronics
Simplifies Circuit Design since Additional Boost Circuits for Gate
Voltages are not Required
Operated at Standard Logic Level Gate Drive, Facilitating Future
Migration to Lower Levels using the same Basic Topology
Pb−Free Package is Available
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V(BR)DSS
RDS(on) TYP
ID MAX
50 m @ −4.5 V
−8.0 V
68 m @ −2.5 V
−4.6 A
100 m @ −1.8 V
S1
S2
G1
G2
Applications
• Optimized for Battery and Load Management Applications in
•
•
Portable Equipment such as MP3 Players, Cell Phones, Digital
Cameras, Personal Digital Assistant and other Portable Applications
Charge Control in Battery Chargers
Buck and Boost Converters
D1
D2
P−Channel MOSFET
P−Channel MOSFET
ChipFET
CASE 1206A
STYLE 2
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Symbol
Value
Unit
Drain−to−Source Voltage
Rating
VDSS
−8.0
V
Gate−to−Source Voltage − Continuous
8.0
V
ID
ID
−3.4
−4.6
A
Total Power Dissipation
Continuous @ TA = 25°C
(5 sec) @ TA = 25°C
Continuous @ 85°C
(5 sec) @ 85°C
PD
Operating Junction and Storage Temperature
Range
Continuous Source Current
(Diode Conduction)
Thermal Resistance (Note 1)
Junction−to−Ambient, 5 sec
Junction−to−Ambient, Continuous
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
W
1.1
2.1
0.6
1.1
TJ, Tstg
−55 to
+150
°C
Is
−1.1
A
RJA
RJA
60
113
TL
260
°C/W
December, 2004 − Rev. 4
MARKING
DIAGRAM
D1 8
1 S1
1
8
D1 7
2 G1
2
7
D2 6
3 S2
3
D2 5
4 G2
4
6
5
D5 = Specific Device Code
M = Month Code
ORDERING INFORMATION
°C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.27 in sq
[1 oz] including traces).
 Semiconductor Components Industries, LLC, 2004
PIN
CONNECTIONS
D5 M
VGS
Drain Current − Continuous
− 5 seconds
1
Package
Shipping†
NTHD2102PT1
ChipFET
3000/Tape & Reel
NTHD2102PT1G
ChipFET
(Pb−Free)
3000/Tape & Reel
Device
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Publication Order Number:
NTHD2102P/D
NTHD2102P
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
Test Condition
Min
Typ
Max
Unit
V(Br)DSS
VGS = 0 V, ID = −250 A
−8.0
−
−
V
Gate−Body Leakage Current Zero
IGSS
VDS = 0 V, VGS = 8.0 V
−
100
nA
Zero Gate Voltage Drain Current
IDSS
VDS = −6.4 V, VGS = 0 V
VDS = −6.4 V, VGS = 0 V,
TJ = 85°C
−
−
−1.0
−5.0
A
Gate Threshold Voltage
VGS(th)
VDS = VGS, ID = −250 A
−0.45
−
−1.5
V
Static Drain−to−Source On−Resistance
RDS(on)
VGS = −4.5 V, ID = −3.4 A
VGS = −2.5 V, ID = −2.7 A
VGS = −1.8 V, ID = −1.0 A
−
−
−
50
68
100
58
85
160
m
Forward Transconductance
gFS
VDS = −5.0 V, ID = −3.4 A
−
8.0
−
S
Diode Forward Voltage
VSD
IS = −1.1 A, VGS = 0 V
−
−0.8
−1.2
V
Input Capacitance
Ciss
VDS = −6.4 V
−
715
−
pF
Output Capacitance
Coss
VGS = 0 V
−
160
−
Transfer Capacitance
Crss
f = 1.0 MHz
−
120
−
td(on)
VDD = −6.4 V
8.0
−
tr
VGS = −4.5 V
20
−
td(off)
ID = −3.2 A
20
−
tf
RG = 2.0 15
−
Qg
VGS = −2.5 V
8.0
16
Qgs
ID = −3.2 A
2.2
−
Qgd
VDS = −6.4 V
4.0
−
trr
IF = −0.9 A, di/dt = 100
15
30
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage (Note 2)
Temperature Coefficient (Positive)
ON CHARACTERISTICS (Note 2)
DYNAMIC CHARACTERISTICS
SWITCHING CHARACTERISTICS (Note 3
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Gate Charge
Source−Drain Reverse Recovery Time
2. Pulse Test: Pulse Width = 250 s, Duty Cycle = 2%.
3. Switching characteristics are independent of operating junction temperatures.
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2
ns
nC
nA
NTHD2102P
TYPICAL ELECTRICAL CHARACTERISTICS
10
10
−2.4 thru −8 V
TJ = 25°C
8
−ID,Drain Current (A)
−ID,Drain Current (A)
8
−2 V
6
−1.8 V
4
−1.6 V
2
6
4
Tj = 100°C
2
25°C
−1.4 V
0
0
1
2
3
4
5
−VDS, Drain−to−Source Voltage (V)
0
6
0
0.5
Figure 1. On−Region Characteristics
1.0
1.5
2.0
2.5
−VGS, Gate−to−Source Voltage (V)
3.0
Figure 2. Transfer Characteristics
0.30
1.2
VGS = −4.5 V
r DS(on),On−Resistance ( Ω )
(Normalized)
r DS(on),On−Resistance ( Ω )
−55°C
0.25
VGS = −1.8 V
0.20
0.15
VGS = −2.5 V
0.10
0.05
1.1
1.0
0.9
VGS = −4.5 V
0
0
2
3
5
4
6
−ID, Drain Current (A)
7
0.8
−50
8
Figure 3. On−Resistance vs. Drain Current and
Gate Voltage
−25
0
25
50
75
100
TJ, Junction Temperature (°C)
150
Figure 4. On−Resistance Variation vs.
Temperature
10000
1800
VGS = 0 V
TJ = 25°C
1500
TJ =
125°C
1000
C, Capacitance (pF)
−IDSS, Leakage (nA)
125
100
Tj = 100°C
10
Ciss
1200
Crss
900
Ciss
600
300
1
Coss
Crss
0
0
2
4
6
−VDS, Drain−to−Source Voltage (V)
8
−8
Figure 5. Drain−to−Source Leakage Current
vs. Voltage
−6
0
2
4
−4
−2
−VDS, Drain−to−Source Voltage (V)
Figure 6. Capacitance Variation
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3
6
8
NTHD2102P
TYPICAL ELECTRICAL CHARACTERISTICS
Q1
−VGS
Q2
4
2
1
2
TJ = 25°C
ID = −3.4 A
−VDS
0
VDD = −10 V
ID = −1 A
VGS = −4.5 V
100
td(off)
t, Time (ns)
QT
−VDS, Drain−to−Source Voltage (V)
−V Gate−to−Source Voltage (V)
GS,
6
3
0
1000
8
4
tr
10
0
tf
1
td(on)
Qg, Total Gate Charge (nC)
10
RG, Gate Resistance (Ohms)
Figure 7. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
Figure 8. Resistive Switching Time Variation
vs. Gate Resistance
1
2
3
4
5
6
7
8
0
100
50
5
40
4
Power (W)
−I S,Source Current (A)
VGS = 0 V
TJ = 25°C
3
2
20
10
1
0
0.40
30
0.50
0.60
0.70
0.80
0.90
−VSD, Source−to−Drain Voltage (V)
0
10−4
1.00
Figure 9. Diode Forward Voltage vs. Current
10−3
10−2
10 −1
1
Time (sec)
10
Figure 10. Single Pulse Power
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4
100
600
NTHD2102P
TYPICAL ELECTRICAL CHARACTERISTICS
Normalized Effective Transient
Thermal Impedance
2
1
Duty Cycle = 0.5
Notes:
PDM
0.2
t1
0.1
t2
0.1
t1
1. Duty Cycle, D = t
2
2. Per Unit Base = RJA = 90°C/W
3. TJM − TA = PDMZJA(t)
4. Surface Mounted
0.05
0.02
Single Pulse
0.01
10−4
10−3
10−2
10 −1
1
Square Wave Pulse Duration (sec)
10
100
600
Figure 11. Normalized Thermal Transient Impedance, Junction−to−Ambient
Normalized Effective Transient
Thermal Impedance
2
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
10−4
10−3
10−2
10 −1
Square Wave Pulse Duration (sec)
1
Figure 12. Normalized Thermal Transient Impedance, Junction−to−Foot
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5
10
NTHD2102P
PACKAGE DIMENSIONS
ChipFET
CASE 1206A−03
ISSUE E
A
8
7
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM
PER SIDE.
4. LEADFRAME TO MOLDED BODY OFFSET IN
HORIZONTAL AND VERTICAL SHALL NOT EXCEED
0.08 MM.
5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE
BURRS.
6. NO MOLD FLASH ALLOWED ON THE TOP AND
BOTTOM LEAD SURFACE.
7. 1206A−01 AND 1206A−02 OBSOLETE. NEW
STANDARD IS 1206A−03.
M
6
K
5
S
5
6
7
8
4
3
2
1
B
1
2
3
4
L
D
J
G
STYLE 2:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
C
0.05 (0.002)
DIM
A
B
C
D
G
J
K
L
M
S
SOURCE 1
GATE 1
SOURCE 2
GATE 2
DRAIN 2
DRAIN 2
DRAIN 1
DRAIN 1
MILLIMETERS
MIN
MAX
2.95
3.10
1.55
1.70
1.00
1.10
0.25
0.35
0.65 BSC
0.10
0.20
0.28
0.42
0.55 BSC
5 ° NOM
2.00
1.80
INCHES
MIN
MAX
0.116
0.122
0.061
0.067
0.039
0.043
0.010
0.014
0.025 BSC
0.004
0.008
0.011
0.017
0.022 BSC
5 ° NOM
0.072
0.080
SOLDERING FOOTPRINTS*
2.032
0.08
2.032
0.08
0.457
0.018
0.635
0.025
1.092
0.043
0.635
0.025
0.178
0.007
0.457
0.018
0.711
0.028
0.66
0.026
SCALE 20:1
mm
inches
0.254
0.010
0.66
0.026
SCALE 20:1
Basis
mm inches
Style 2
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ChipFET is a trademark of Vishay Siliconix.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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6
For additional information, please contact your
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NTHD2102P/D