MC74LCX573 Low−Voltage CMOS Octal Transparent Latch Flow Through Pinout With 5 V−Tolerant Inputs and Outputs (3−State, Non−Inverting) The MC74LCX573 is a high performance, non−inverting octal transparent latch operating from a 2.3 to 3.6 V supply. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance. A VI specification of 5.5 V allows MC74LCX573 inputs to be safely driven from 5.0 V devices. The MC74LCX573 contains 8 D−type latches with 3−state standard outputs. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition, the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time preceding the HIGH−to−LOW transition of LE. The 3−state standard outputs are controlled by the Output Enable (OE) input. When OE is LOW, the standard outputs are enabled. When OE is HIGH, the standard outputs are in the high impedance state, but this does not interfere with new data entering into the latches. The LCX573 flow through design facilitates easy PC board layout. http://onsemi.com MARKING DIAGRAMS 20 20 1 Designed for 2.3 to 3.6 V VCC Operation 5.0 V Tolerant − Interface Capability With 5.0 V TTL Logic Supports Live Insertion and Withdrawal IOFF Specification Guarantees High Impedance When VCC = 0 V LVTTL Compatible LVCMOS Compatible 24 mA Balanced Output Sink and Source Capability Near Zero Static Supply Current in All Three Logic States (10 A) Substantially Reduces System Power Requirements Latchup Performance Exceeds 500 mA • • ESD Performance: • Human Body Model >2000 V Machine Model >200 V Pb−Free Packages are Available* LCX573 AWLYYWWG 1 20 20 1 TSSOP−20 DT SUFFIX CASE 948E 1 LCX 573 ALYW 20 Features • • • • • • • • SOIC−20 DW SUFFIX CASE 751D 20 1 SOEIAJ−20 M SUFFIX CASE 967 1 74LCX573 AWLYWWG A = Assembly Location L, WL = Wafer Lot Y, YY = Year W, WW = Work Week G = Pb−Free Package = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Semiconductor Components Industries, LLC, 2005 May, 2005 − Rev. 7 1 Publication Order Number: MC74LCX573/D MC74LCX573 OE VCC O0 O1 O2 O3 O4 O5 O6 O7 LE 20 19 18 17 16 15 14 13 12 11 LE 1 11 2 D0 D1 2 3 4 5 6 7 8 9 OE D0 D1 D2 D3 D4 D5 D6 D7 18 nLE O1 Q D 10 4 GND O0 Q D 3 1 19 nLE D2 17 nLE O2 Q D Figure 1. Pinout (Top View) 5 D3 PIN NAMES D4 FUNCTION OE LE D0−D7 O0−O7 Output Enable Input Latch Enable Input Data Inputs 3−State Latch Outputs 15 nLE D5 14 nLE D6 13 nLE O6 Q D 9 D7 12 nLE Q D Figure 2. Logic Diagram TRUTH TABLE OUTPUTS OE LE Dn On OPERATING MODE L L H H H L H L Transparent (Latch Disabled); Read Latch L L L L h l H L Latched (Latch Enabled) Read Latch L L X NC Hold; Read Latch H L X Z Hold; Disabled Outputs H H H H H L Z Z Transparent (Latch Disabled); Disabled Outputs H H L L h l Z Z Latched (Latch Enabled); Disabled Outputs H = High Voltage Level; h = High Voltage Level One Setup Time Prior to the Latch Enable High−to−Low Transition L = Low Voltage Level l = Low Voltage Level One Setup Time Prior to the Latch Enable High−to−Low Transition NC = No Change, State Prior to the Latch Enable High−to−Low Transition X = High or Low Voltage Level or Transitions are Acceptable Z = High Impedance State For ICC Reasons DO NOT FLOAT Inputs 2 O5 Q D 8 http://onsemi.com O4 Q D 7 INPUTS O3 Q D 6 PINS 16 nLE O7 MC74LCX573 MAXIMUM RATINGS Symbol Parameter Value Condition Unit VCC DC Supply Voltage VI DC Input Voltage −0.5 ≤ VI ≤ +7.0 −0.5 to +7.0 V VO DC Output Voltage −0.5 ≤ VO ≤ +7.0 Output in 3−State −0.5 ≤ VO ≤ VCC + 0.5 Output in HIGH or LOW State (Note 1) V IIK DC Input Diode Current −50 VI< GND mA IOK DC Output Diode Current −50 VO < GND mA +50 VO > VCC mA V V IO DC Output Source/Sink Current ±50 mA ICC DC Supply Current Per Supply Pin ±100 mA IGND DC Ground Current Per Ground Pin ±100 mA TSTG Storage Temperature Range −65 to +150 °C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. IO absolute maximum rating must be observed. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Operating Data Retention Only Min Typ Max Unit 2.0 1.5 2.5, 3.3 2.5, 3.3 3.6 3.6 V 0 5.5 V 0 0 VCC 5.5 V VCC Supply Voltage VI Input Voltage VO Output Voltage IOH HIGH Level Output Current VCC = 3.0 V − 3.6 V VCC = 2.7 V − 3.0 V VCC = 2.3 V − 2.7 V − 24 − 12 −8 mA IOL LOW Level Output Current VCC = 3.0 V − 3.6 V VCC = 2.7 V − 3.0 V VCC = 2.3 V − 2.7 V + 24 + 12 +8 mA TA Operating Free−Air Temperature t/V Input Transition Rise or Fall Rate, VIN from 0.8 V to 2.0 V, VCC = 3.0 V (HIGH or LOW State) (3−State) −40 +85 °C 0 10 ns/V ORDERING INFORMATION Package Shipping† MC74LCX573DW SOIC−20 38 Units / Rail MC74LCX573DWG SOIC−20 (Pb−Free) 38 Units / Rail MC74LCX573DWR2 SOIC−20 1000 Tape & Reel MC74LCX573DWR2G SOIC−20 (Pb−Free) 1000 Tape & Reel MC74LCX573DT TSSOP−20* 75 Units / Rail MC74LCX573DTG TSSOP−20* 75 Units / Rail MC74LCX573DTR2 TSSOP−20* 2000 Tape & Reel MC74LCX573DTR2G TSSOP−20* 2000 Tape & Reel MC74LCX573M SOEIAJ−20 40 Units / Rail MC74LCX573MG SOEIAJ−20 (Pb−Free) 40 Units / Rail MC74LCX573MEL SOEIAJ−20 2000 Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. http://onsemi.com 3 MC74LCX573 DC ELECTRICAL CHARACTERISTICS TA = −40°C to +85°C Symbol Characteristic VIH HIGH Level Input Voltage (Note 2) VIL LOW Level Input Voltage (Note 2) VOH VOL HIGH Level Output Voltage LOW Level Output Voltage Condition Min 2.3 V ≤ VCC ≤ 2.7 V 1.7 2.7 V ≤ VCC ≤ 3.6 V 2.0 Max Unit V 2.3 V ≤ VCC ≤ 2.7 V 0.7 2.7 V ≤ VCC ≤ 3.6 V 0.8 2.3 V ≤ VCC ≤ 3.6 V; IOL = 100 A VCC − 0.2 VCC = 2.3 V; IOH = −8 mA 1.8 VCC = 2.7 V; IOH = −12 mA 2.2 VCC = 3.0 V; IOH = −18 mA 2.4 VCC = 3.0 V; IOH = −24 mA 2.2 V V 2.3 V ≤ VCC ≤ 3.6 V; IOL = 100 A 0.2 VCC = 2.3 V; IOL= 8 mA 0.6 VCC = 2.7 V; IOL= 12 mA 0.4 VCC = 3.0 V; IOL = 16 mA 0.4 VCC = 3.0 V; IOL = 24 mA 0.55 V II Input Leakage Current 2.3 V ≤ VCC ≤ 3.6 V; 0 V ≤ VI ≤ 5.5 V ±5 A IOZ 3−State Output Current 2.3 ≤ VCC ≤ 3.6 V; 0V ≤ VO ≤ 5.5 V; VI = VIH or V IL ±5 A IOFF Power−Off Leakage Current VCC = 0 V; VI or VO = 5.5 V 10 A ICC Quiescent Supply Current 2.3 ≤ VCC ≤ 3.6 V; VI = GND or VCC 10 A 2.3 ≤ VCC ≤ 3.6 V; 3.6 ≤ VI or VO ≤ 5.5 V ±10 ICC Increase in ICC per Input 2.3 ≤ VCC ≤ 3.6 V; VIH = VCC − 0.6 V 500 A 2. These values of VI are used to test DC electrical characteristics only. AC CHARACTERISTICS tR = tF = 2.5 ns; RL = 500 Limits TA = −40°C to +85°C Symbol Parameter VCC = 3.3 V ± 0.3 V VCC = 2.7 V VCC = 2.5 V ± 0.2 V CL = 50 pF CL = 50 pF CL = 30 pF Waveform Min Max Min Max Min Max Unit tPLH tPHL Propagation Delay Dn to On 1 1.5 1.5 8.0 8.0 1.5 1.5 9.0 9.0 1.5 1.5 9.6 9.6 ns tPLH tPHL Propagation Delay LE to On 3 1.5 1.5 8.5 8.5 1.5 1.5 9.5 9.5 1.5 1.5 10.5 10.5 ns tPZH tPZL Output Enable Time to HIGH and LOW Level 2 1.5 1.5 8.5 8.5 1.5 1.5 9.5 9.5 1.5 1.5 10.5 10.5 ns tPHZ tPLZ Output Disable Time From High and Low Level 2 1.5 1.5 6.5 6.5 1.5 1.5 7.0 7.0 1.5 1.5 7.8 7.8 ns ts Setup TIme, HIGH or LOW Dn to LE 3 2.5 2.5 4.0 th Hold TIme, HIGH or LOW Dn to LE 3 1.5 1.5 2.0 tw LE Pulse Width, HIGH 3 3.3 3.3 4.0 tOSHL tOSLH Output−to−Output Skew (Note 3) 1.0 1.0 ns 3. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (tOSHL) or LOW−to−HIGH (tOSLH); parameter guaranteed by design. http://onsemi.com 4 MC74LCX573 DYNAMIC SWITCHING CHARACTERISTICS TA = +25°C Symbol Characteristic Condition Min Typ Max Unit VOLP Dynamic LOW Peak Voltage (Note 4) VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V VCC = 2.5 V, CL = 30 pF, VIH = 2.5 V, VIL = 0 V 0.8 0.6 V V VOLV Dynamic LOW Valley Voltage (Note 4) VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V VCC = 2.5 V, CL = 30 pF, VIH = 2.5 V, VIL = 0 V −0.8 −0.6 V V 4. Number of outputs defined as “n”. Measured with “n−1” outputs switching from HIGH−to−LOW or LOW−to−HIGH. The remaining output is measured in the LOW state. CAPACITIVE CHARACTERISTICS Condition Typical Unit CIN Symbol Input Capacitance Parameter VCC = 3.3 V, VI = 0 V or VCC 7 pF CI/O Input/Output Capacitance VCC = 3.3 V, VI = 0 V or VCC 8 pF CPD Power Dissipation Capacitance 10 MHz, VCC = 3.3 V, VI = 0 V or VCC 25 pF VCC OE Vmi Vmi VCC Dn Vmi 0V tPZH Vmi On 0V tPLH tPHZ VOH VHZ Vmo tPHL VOH Vmo On tPZL Vmo tPLZ VOL Vmo On VLZ VOL WAVEFORM 1 − PROPAGATION DELAYS tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns WAVEFORM 2 − OUTPUT ENABLE AND DISABLE TIMES tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns 2.7 V Dn 1.5 V 0V ts VCC th 2.7 V LE 1.5 V tw 0V tPLH, tPHL VOH On 3.3 V 0.3 V 2.7 V 2.5 V 0.2 V Vmi 1.5 V 1.5 V VCC/2 Vmo 1.5 V 1.5 V VCC/2 VHZ VOL + 0.3 V VOL + 0.3 V VOL + 0.15 V VLZ VOL − 0.3 V VOL − 0.3 V VOL − 0.15 V Symbol 1.5 V 1.5 V VOL WAVEFORM 3 − LE to On PROPAGATION DELAYS, LE MINIMUM PULSE WIDTH, Dn to LE SETUP AND HOLD TIMES tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns except when noted Figure 3. AC Waveforms http://onsemi.com 5 MC74LCX573 VCC R1 PULSE GENERATOR DUT RT CL TEST RL SWITCH tPLH, tPHL Open tPZL, tPLZ 6 V at VCC = 3.3 0.3 V 6 V at VCC = 2.5 0.2 V Open Collector/Drain tPLH and tPHL 6V tPZH, tPHZ CL = CL = RL = RT = GND 50 pF at VCC = 3.3 0.3 V or equivalent (includes jig and probe capacitance) 30 pF at VCC = 2.5 0.2 V or equivalent (includes jig and probe capacitance) R1 = 500 or equivalent ZOUT of pulse generator (typically 50 ) Figure 4. Test Circuit http://onsemi.com 6 6V OPEN GND MC74LCX573 PACKAGE DIMENSIONS SOIC−20 DW SUFFIX CASE 751D−05 ISSUE G 20 11 X 45 h 1 10 20X DIM A A1 B C D E e H h L B B 0.25 M T A B S S A L H M E 0.25 10X NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. A B M D e 18X MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0 7 SEATING PLANE A1 C T TSSOP−20 DT SUFFIX CASE 948E−02 ISSUE B 20X 0.15 (0.006) T U 2X K REF 0.10 (0.004) S L/2 20 M T U S V S K K1 ÍÍÍÍ ÍÍÍÍ ÍÍÍÍ 11 J J1 B −U− L PIN 1 IDENT SECTION N−N 1 10 0.25 (0.010) N 0.15 (0.006) T U S M A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. N F DETAIL E −W− C D G H DETAIL E 0.100 (0.004) −T− SEATING PLANE http://onsemi.com 7 DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0 8 INCHES MIN MAX 0.252 0.260 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0 8 MC74LCX573 PACKAGE DIMENSIONS SOEIAJ−20 M SUFFIX CASE 967−01 ISSUE O 20 LE 11 Q1 E HE 1 M L 10 DETAIL P Z D VIEW P e A c DIM A A1 b c D E e HE L LE M Q1 Z A1 b 0.13 (0.005) M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). 0.10 (0.004) MILLIMETERS MIN MAX −−− 2.05 0.05 0.20 0.35 0.50 0.18 0.27 12.35 12.80 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 0 0.70 0.90 −−− 0.81 INCHES MIN MAX −−− 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.486 0.504 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 0 0.028 0.035 −−− 0.032 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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