MC100LVEL32 ÷2 Divider The MC100LVEL32 is an integrated ÷2 divider. The differential clock inputs and the VBB allow a differential, single-ended or AC coupled interface to the device. If used, the VBB output should be bypassed to ground with a 0.01µF capacitor. Also note that the VBB is designed to be used as an input bias on the LVEL32 only, the VBB output has limited current sink and source capability.The LVEL32 is functionally identical to the EL32, but operates from a low voltage supply. The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flop will attain a random state; the reset allows for the synchronization of multiple EL32’s in a system. • • • • • 510ps Propagation Delay 3.0GHz Toggle Frequency High Bandwidth Output Transitions 75kΩ Internal Input Pulldown Resistors >1000V ESD Protection http://onsemi.com 8 1 SO–8 D SUFFIX CASE 751 MARKING DIAGRAM 8 A L Y W KVL32 ALYW 1 LOGIC DIAGRAM AND PINOUT ASSIGNMENT = Assembly Location = Wafer Lot = Year = Work Week *For additional information, see Application Note AND8002/D Reset 1 8 VCC PIN DESCRIPTION R CLK 2 7 Q ÷2 CLK 3 6 Q VBB 4 5 VEE PIN FUNCTION CLK Reset VBB Q Clock Inputs Asynch Reset Ref Voltage Output Data Ouputs ORDERING INFORMATION Device Semiconductor Components Industries, LLC, 2000 April, 2000 – Rev. 1 1 Package Shipping MC100LVEL32D SO–8 98 Units/Rail MC100LVEL32DR2 SO–8 2500 Tape & Reel Publication Order Number: MC100LVEL32/D MC100LVEL32 DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = GND) –40°C Symbol Characteristic Min Typ IEE Power Supply Current 25 VEE Power Supply Voltage –3.0 VBB Output Reference Voltage IIH Input HIGH Current –1.38 0°C Max Min Typ 25°C Max Min 25 –3.0 –3.3 –1.26 –1.38 Typ Max Min 25 –3.8 –3.0 –3.3 –1.26 –1.38 150 85°C Typ 25 –3.8 –3.0 –3.3 –1.26 –1.38 150 Max 150 Unit mA –3.8 V –1.26 V 150 µA Max Unit AC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = GND) –40°C Symbol Characteristic Min fMAX Maximum Toggle Frequency tPLH tPHL Propagation Delay CLK to Q (Diff) CLK to Q (S.E.) Reset to Q 350 300 340 Minimum Input Swing1 150 VPP Typ 0°C Max Min Typ 3.0 500 500 540 25°C Max Min 3.0 530 580 540 360 310 350 500 500 540 Typ 540 590 550 370 320 350 510 510 540 150 225 CLK RESET Q Figure 1. Timing Diagram http://onsemi.com 2 Max Min 3.0 150 tr Output Rise/Fall Times Q 225 tf (20% – 80%) 1. Minimum input swing for which AC parameters are guaranteed. 85°C Typ 3.0 550 600 550 410 360 380 540 540 550 150 225 GHz 590 640 580 ps mV 225 ps MC100LVEL32 PACKAGE DIMENSIONS SO–8 D SUFFIX PLASTIC SOIC PACKAGE CASE 751–06 ISSUE T D A 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS ARE IN MILLIMETER. 3. DIMENSION D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. C 5 0.25 H E M B M 1 4 h B e X 45 _ q A C SEATING PLANE L 0.10 A1 B 0.25 M C B S A S DIM A A1 B C D E e H h L q http://onsemi.com 3 MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.35 0.49 0.19 0.25 4.80 5.00 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.25 0_ 7_ MC100LVEL32 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. 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