ETC NTES1P02/D

NTES1P02
Product Preview
Power MOSFET
50 mAmps, 20 Volts
P–Channel SC–75
•
•
•
•
Low Threshold Voltage: Vth = 0.5 to 1.5 V
High Speed
Small Package
Complementary to NTES1N02
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50 mAMPS
20 VOLTS
RDS(on) = 15 MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
VDS
20
Vdc
VGSS
7
Vdc
Drain Current
– Continuous @ TA = 25°C
ID
50
Total Power Dissipation @ TA = 25°C
PD
100
mW
Channel Temperature
Tch
150
°C
Operating and Storage Temperature
Range
Tstg
– 55 to
150
°C
Drain–to–Source Voltage
Gate–to–Source Voltage – Continuous
N–Channel
3
mAdc
1
2
MARKING
DIAGRAM
3
SC–75/SOT–416
CASE 463
STYLE 1
2
P02
D
1
P02
D
= Device Code
= Date Code
PIN ASSIGNMENT
3 Drain
Gate 1
2 Source
Top View
ORDERING INFORMATION
Device
NTES1P02
Package
SC–75
Shipping
3000 Tape & Reel
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
 Semiconductor Components Industries, LLC, 2001
January, 2001 – Rev. 0
1
Publication Order Number:
NTES1P02/D
NTES1P02
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
V(BR)DSS
20
–
–
Vdc
–
–
1.0
–
–
1.0
0.5
–
1.5
–
7.0
15
YFS
15
–
–
mS
pF
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 100 µA)
Drain Cut–off Current
(VDS = 20 Vdc, VGS = 0 Vdc)
IDSS
Gate–Body Leakage Current (VGS = 7.0 Vdc, VDS = 0)
IGSS
µAdc
µAdc
ON CHARACTERISTICS
Gate Threshold Voltage
(VDS = 3.0 Vdc, ID = 0.1 mAdc)
Vth
Drain–to–Source On–Resistance
(VGS = 2.5 Vdc, ID = 10 mAdc)
RDS(on)
Forward Transfer Admittance (VDS = 3.0 Vdc, ID = 10 mAdc)
Vdc
Ω
DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 3.0 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Ciss
–
10.4
–
Output Capacitance
(VDS = 3.0 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Coss
–
8.4
–
Reverse Transfer Capacitance
(VDS = 3.0 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Crss
–
2.8
–
(VDD = 3.0 Vdc, ID = 10 mAdc,
VGS = 0 to 2.5 Vdc)
ton
–
0.15
–
toff
–
0.13
–
SWITCHING CHARACTERISTICS
Turn–On Delay Time
Turn–Off Delay Time
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2
µs
NTES1P02
PACKAGE DIMENSIONS
SC–75 (SC–90, SOT–416)
CASE 463–01
ISSUE B
–A–
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
2
3
D 3 PL
0.20 (0.008)
G –B–
1
M
B
K
J
0.20 (0.008) A
C
L
DIM
A
B
C
D
G
H
J
K
L
S
MILLIMETERS
MIN
MAX
0.70
0.80
1.40
1.80
0.60
0.90
0.15
0.30
1.00 BSC
--0.10
0.10
0.25
1.45
1.75
0.10
0.20
0.50 BSC
STYLE 1:
PIN 1. BASE
2. EMITTER
3. COLLECTOR
H
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3
INCHES
MIN
MAX
0.028
0.031
0.055
0.071
0.024
0.035
0.006
0.012
0.039 BSC
--0.004
0.004
0.010
0.057
0.069
0.004
0.008
0.020 BSC
NTES1P02
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
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alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
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4
NTES1P02/D