FAIRCHILD 74LVQ86SJ

Revised June 2003
74LVQ86
Low Voltage Quad 2-Input Exclusive-OR Gate
General Description
Features
The LVQ86 contains four 2-input exclusive-OR gates.
■ Ideal for low power/low noise 3.3V applications
■ Guaranteed simultaneous switching noise level and
dynamic threshold performance
■ Guaranteed pin-to-pin skew AC performance
■ Guaranteed incident wave switching into 75Ω
Ordering Code:
Order Number
Package Number
Package Description
74LVQ86SC
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74LVQ86SJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
Description
A0–A3
Inputs
© 2003 Fairchild Semiconductor Corporation
B0–B3
Inputs
O0–O3
Outputs
DS011348
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74LVQ86 Low Voltage Quad 2-Input Exclusive-OR Gate
February 1992
74LVQ86
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions (Note 2)
−0.5V to +7.0V
Supply Voltage (VCC)
DC Input Diode Current (IIK)
Supply Voltage (VCC)
VI = −0.5V
−20 mA
VI = VCC + 0.5V
+20 mA
DC Input Voltage (VI)
LVQ
−0.5V to VCC + 0.5V
DC Output Diode Current (IOK)
0V to VCC
Output Voltage (VO)
0V to VCC
Operating Temperature (TA)
VO = −0.5V
−20 mA
VO = VCC + 0.5V
+20 mA
DC Output Voltage (VO)
−40°C to +85°C
74LVQ
Minimum Input Edge Rate (∆V/∆t)
−0.5V to VCC + 0.5V
VIN from 0.8V to 2.0V
DC Output Source
VCC @ 3.0V
±50 mA
or Sink Current (IO)
±200 mA
(ICC or IGND )
125 mV/ns
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
DC VCC or Ground Current
Storage Temperature (TSTG)
2.0V to 3.6V
Input Voltage (VI)
−65°C to +150°C
DC Latch-Up Source or
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
±100 mA
Sink Current
DC Electrical Characteristics
Symbol
VIH
Parameter
Minimum High Level
TA = 25°C
VCC
(V)
Typ
3.0
1.5
TA = −40°C to +85°C
Units
2.0
2.0
V
Maximum Low Level
3.0
1.5
0.8
0.8
V
V OUT = 0.1V
3.0
2.99
2.9
2.9
V
IOUT = −50 µA
2.58
2.48
V
0.1
0.1
V
3.0
0.36
0.44
±0.1
or VCC − 0.1V
Input Voltage
VOH
Minimum High Level
Output Voltage
VOL
Maximum Low Level
Output Voltage
V OUT = 0.1V
or VCC − 0.1V
Input Voltage
VIL
Conditions
Guaranteed Limits
3.0
3.0
0.002
V IN = VIL or VIH (Note 3)
IOH = −12 mA
IOUT = 50 µA
V IN = VIL or VIH (Note 3)
IOL = 12 mA
IIN
Maximum Input Leakage Current
3.6
±1.0
µA
V I = VCC, GND
IOLD
Minimum Dynamic (Note 4)
3.6
36
mA
V OLD = 0.8V Max (Note 5)
IOHD
Output Current
3.6
−25
mA
V OHD = 2.0V Min (Note 5)
ICC
Maximum Quiescent
20.0
µA
V IN = VCC or GND
Supply Current
VOLP
Quiet Output
Maximum Dynamic VOL
VOLV
Quiet Output
VIHD
Maximum High Level
Minimum Dynamic VOL
Dynamic Input Voltage
VILD
Maximum Low Level
Dynamic Input Voltage
3.6
2.0
3.3
0.5
0.8
V
(Note 6)(Note 7)
3.3
−0.5
−0.8
V
(Note 6)(Note 7)
3.3
1.8
2.0
V
(Note 6)(Note 8)
3.3
1.8
0.8
V
(Note 6)(Note 8)
Note 3: All outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 20 ms, one output loaded at a time.
Note 5: Incident wave switching on transmission lines with impedances as low as 75Ω for commercial temperature range is guaranteed for 74LVQ.
Note 6: Worst case package.
Note 7: Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V; one output at GND.
Note 8: Max number of Data Inputs (n) switching. (n − 1) inputs switching 0V to 3.3V. Input-under-test switching: 3.3V to threshold (VILD), 0V to threshold
(VIHD), f = 1 MHz.
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2
TA = +25°C
Symbol
tPLH
tPHL
Parameter
Propagation Delay
Propagation Delay
tOSHL,
Output to Output Skew
tOSLH
(Note 9)
TA = −40°C to +85°C
CL = 50 pF
VCC
CL = 50 pF
(V)
Min
Typ
Max
Min
Units
Max
2.7
2.0
7.2
16.2
1.5
18.0
3.3 ± 0.3
2.0
6.0
11.5
1.5
12.5
2.7
2.0
7.8
16.2
1.5
18.0
3.3 ± 0.3
2.0
6.5
11.5
1.5
12.5
2.7
1.0
1.5
1.5
3.3 ± 0.3
1.0
1.5
1.5
ns
ns
ns
Note 9: Skews defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
Capacitance
Symbol
Parameter
Typ
Units
Conditions
CIN
Input Capacitance
4.5
pF
V CC = Open
CPD (Note 10)
Power Dissipation Capacitance
23
pF
VCC = 3.3V
Note 10: CPD is measured at 10 MHz.
3
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74LVQ86
AC Electrical Characteristics
74LVQ86
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M14A
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4
74LVQ86 Low Voltage Quad 2-Input Exclusive-OR Gate
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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user.
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