NBSG16 2.5V/3.3VSiGe Differential Receiver/Driver with RSECL* Outputs *Reduced Swing ECL http://onsemi.com The NBSG16 is a differential receiver/driver targeted for high frequency applications. The device is functionally equivalent to the EP16 and LVEP16 devices with much higher bandwidth and lower EMI capabilities. Inputs incorporate internal 50 termination resistors and accept NECL (Negative ECL), PECL (Positive ECL), HSTL, LVTTL, LVCMOS, CML, or LVDS. Outputs are RSECL (Reduced Swing ECL), 400 mV. The VBB and VMM pins are internally generated voltage supplies available to this device only. The VBB is used as a reference voltage for single-ended NECL or PECL inputs and the VMM pin is used as a reference voltage for LVCMOS inputs. For all single-ended input conditions, the unused complementary differential input is connected to VBB or VMM as a switching reference voltage. VBB or VMM may also rebias AC coupled inputs. When used, decouple VBB and VMM via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB and VMM outputs should be left open. • • • • • • • MARKING DIAGRAM* FCBGA-16 BA SUFFIX CASE 489 A = Assembly Location L = Wafer Lot Y = Year W = Work Week Maximum Input Data Rate > 12 Gb/s Typical *For further details, refer to Application Note AND8002/D 40 ps Typical Rise and Fall Times RSPECL Output with Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V RSNECL Output with RSNECL or NECL Inputs with Operating Range: VCC = 0 V with VEE = -2.375 V to -3.465 V RSECL Output Level (400 mV Peak-to-Peak Output), Differential Output Only 50 Internal Input Termination Resistors • • Compatible with Existing 2.5 V/3.3 V LVEP, EP, and LVEL Devices • VBB and VMM Reference Voltage Output ORDERING INFORMATION Device Package Shipping NBSG16BA 4x4 mm FCBGA-16 100 Units/Tray NBSG16BAR2 4x4 mm FCBGA-16 500/Tape & Reel NBSG16MN 3x3 mm QFN-16 123 Units/Rail NBSG16MNR2 3x3 mm QFN-16 3000/Tape & Reel Board NBSG16BAEVB Semiconductor Components Industries, LLC, 2003 May, 2003 - Rev. 12 SG16 ALYW QFN-16 MN SUFFIX CASE 485G Maximum Input Clock Frequency > 12 GHz Typical 120 ps Typical Propagation Delay SG 16 LYW 1 Description NBSG16BA Evaluation Board Publication Order Number: NBSG16/D NBSG16 1 2 3 VEE VBB 4 16 A VEE D B NC NC VTD 15 VMM VEE 14 Exposed Pad (EP) 13 VEE VCC Q VTD 1 D 2 12 VCC 11 Q NBSG16 D C VTD VEE D VCC VBB VMM Q D 3 10 Q VTD 4 9 VCC VEE Figure 1. BGA-16 Pinout (Top View) 5 6 7 8 VEE NC NC VEE Figure 2. QFN-16 Pinout (Top View) Table 1. Pin Description Pin BGA QFN Name I/O C2 1 VTD - C1 2 D ECL, CML, LVCMOS, LVDS, LVTTL Input Inverted Differential Input. Internal 75 k to VEE and 36.5 k to VCC. B1 3 D ECL, CML, LVCMOS, LVDS, LVTTL Input Noninverted differential input. Internal 75 k to VEE. B2 4 VTD - Internal 50 Termination Pin. See Table 2. A1,D1,A4, D4 5,8,13,16 VEE - Negative Supply Voltage A2,A3 6,7 NC - No Connect B3,C3 9,12 VCC - Positive Supply Voltage B4 10 Q RSECL Output Noninverted Differential Output. Typically Terminated with 50 to VTT = VCC - 2 V C4 11 Q RSECL Output Inverted Differential Output. Typically Terminated with 50 to VTT = VCC - 2 V D3 14 VMM - LVCMOS Reference Voltage Output. (VCC - VEE)/2 D2 15 VBB - ECL Reference Voltage Output N/A - EP - Exposed Pad. (Note 2) Description Internal 50 Termination Pin. See Table 2. 1. The NC pins are electrically connected to the die and MUST be left open. 2. All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. The thermally exposed pad on package bottom (see case drawing) must be attached to a heat-sinking conduit. 3. In the differential configuration when the input termination pins (VTD, VTD) are connected to a common termination voltage, and if no signal is applied then the device will be susceptible to self-oscillation. http://onsemi.com 2 NBSG16 VCC VTD VMM 36.5 50 D Q D Q 50 75 k 75 k VTD VBB VEE Figure 3. Logic Diagram Table 2. Interfacing Options INTERFACING OPTIONS CONNECTIONS CML Connect VTD and VTD to VCC LVDS Connect VTD and VTD together AC-COUPLED Bias VTD and VTD Inputs within (VIHCMR) Common Mode Range RSECL, PECL, NECL Standard ECL Termination Techniques LVTTL The external voltage should be applied to the unused complementary differential input. Nominal voltage is 1.5 V for LVTTL. LVCMOS VMM should be connected to the unused complementary differential input. http://onsemi.com 3 NBSG16 Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor (D, D) 75 k Internal Input Pullup Resistor (D) ESD Protection 36.5 k Human Body Model Machine Model > 2 kV > 100 V FCBGA-16 QFN-16 Level 3 Level 1 Moisture Sensitivity (Note 1) Flammability Rating Oxygen Index: 28 to 34 UL 94 V-0 @ 0.125 in Transistor Count 167 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Table 4. MAXIMUM RATINGS (Note 2) Symbol Rating Units VCC Positive Power Supply Parameter VEE = 0 V Condition 1 3.6 V VEE Negative Power Supply VCC = 0 V -3.6 V VI Positive Input Negative Input VEE = 0 V VCC = 0 V 3.6 -3.6 V V VINPP Differential Input Voltage 2.8 |VCC - VEE| V V Iout Output Current 25 50 mA mA IBB VBB Sink/Source 1 mA IMM VMM Sink/Source 1 mA TA Operating Temperature Range -40 to +85 °C Tstg Storage Temperature Range -65 to +150 °C JA Thermal Resistance (Junction-to-Ambient) (Note 3) 0 LFPM 500 LFPM 0 LFPM 500 LFPM 16 FCBGA 16 FCBGA 16 QFN 16 QFN 108 86 41.6 35.2 °C/W °C/W °C/W °C/W JC Thermal Resistance (Junction-to-Case) 1S2P (Note 3) 2S2P (Note 4) 16 FCBGA 16 QFN 5 4.0 °C/W °C/W Tsol Wave Solder < 15 sec. 225 °C |D - D| VCC - VEE VCC - VEE < Condition 2 VI VCC VI VEE 2.8 V 2.8 V Continuous Surge 2. Maximum Ratings are those values beyond which device damage may occur. 3. JEDEC standard multilayer board - 1S2P (1 signal, 2 power) 4. JEDEC standard multilayer board - 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad. http://onsemi.com 4 NBSG16 Table 5. DC CHARACTERISTICS, INPUT WITH RSPECL OUTPUT VCC = 2.5 V; VEE = 0 V (Note 5) -40 °C 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 17 23 29 17 23 29 17 23 29 mA Output HIGH Voltage (Note 6) 1450 1530 1575 1525 1565 1600 1550 1590 1625 mV VOUTPP Output Voltage Amplitude 350 410 525 350 410 525 350 410 525 mV VIH Input HIGH Voltage (Single-Ended) (Note 7) VTHR + 75 mV VCC 1.0* VCC VTHR + 75 mV VCC 1.0* VCC VTHR + 75 mV VCC 1.0* VCC V VIL Input LOW Voltage (Single-Ended) (Note 7) VEE VCC 1.4* VTHR 75 mV VEE VCC 1.4* VTHR 75 mV VEE VCC 1.4* VTHR 75 mV V VBB PECL Output Voltage Reference 1080 1140 1200 1080 1140 1200 1080 1140 1200 mV VIHCMR Input HIGH Voltage Common Mode Range (Note 8) (Differential Configuration) 2.5 1.2 2.5 1.2 2.5 V VMM CMOS Output Voltage Reference VCC/2 1100 1250 1400 1100 1250 1400 1100 1250 1400 mV RTIN Internal Input Termination Resistor 45 50 55 45 50 55 45 50 55 IIH Input HIGH Current (@ VIH) 30 100 30 100 30 100 A IIL Input LOW Current (@ VIL) 25 50 25 50 25 50 A Symbol Characteristic IEE Negative Power Supply Current VOH 1.2 NOTE: SiGe circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 5. Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to -0.965 V. 6. All loading with 50 to VCC-2.0 volts. 7. VTHR is the voltage applied to the complementary input, typically VBB or VMM. 8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. *Typicals used for testing purposes. Table 6. DC CHARACTERISTICS, INPUT WITH RSPECL OUTPUT VCC = 3.3 V; VEE = 0 V (Note 9) -40 °C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit IEE Negative Power Supply Current 17 23 29 17 23 29 17 23 29 mA VOH Output HIGH Voltage (Note 10) 2250 2330 2375 2325 2365 2400 2350 2390 2425 mV VOUTPP Output Voltage Amplitude 350 410 525 350 410 525 350 410 525 mV VIH Input HIGH Voltage (Single-Ended) (Note 11) VTHR + 75 mV VCC 1.0* VCC VTHR + 75 mV VCC 1.0* VCC VTHR + 75 mV VCC 1.0* VCC V VIL Input LOW Voltage (Single-Ended) (Note 11) VEE VCC 1.4* VTHR 75 mV VEE VCC 1.4* VTHR 75 mV VEE VCC 1.4* VTHR 75 mV V VBB PECL Output Voltage Reference 1880 1940 2000 1880 1940 2000 1880 1940 2000 mV VIHCMR Input HIGH Voltage Common Mode Range (Note 12) (Differential Configuration) 3.3 1.2 3.3 1.2 3.3 V VMM CMOS Output Voltage Reference VCC/2 1500 1650 1800 1500 1650 1800 1500 1650 1800 mV RTIN Internal Input Termination Resistor 45 50 55 45 50 55 45 50 55 IIH Input HIGH Current (@ VIH) 30 100 30 100 30 100 A IIL Input LOW Current (@ VIL) 25 50 25 50 25 50 A 1.2 NOTE: SiGe Circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 9. Input and output parameters vary 1:1 with VCC. VEE can vary +0.925 V to -0.165 V. 10. All loading with 50 to VCC - 2.0 V. 11. VTHR is the voltage applied to the complementary input, typically VBB or VMM. 12. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. *Typicals used for testing purposes. http://onsemi.com 5 NBSG16 Table 7. DC CHARACTERISTICS, NECL OR RSNECL INPUT WITH NECL OUTPUT VCC = 0 V; VEE = -3.465 V to -2.375 V (Note 13) -40 °C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit IEE Negative Power Supply Current 17 23 29 17 23 29 17 23 29 mA VOH Output HIGH Voltage (Note 14) -1050 -970 -925 -975 -935 -900 -950 -910 -875 mV VOUTPP Output Voltage Amplitude 350 410 525 350 410 525 350 410 525 mV VIH Input HIGH Voltage (Single-Ended) (Note 15) VTHR + 75 mV VCC 1.0* VCC VTHR + 75 mV VCC 1.0* VCC VTHR + 75 mV VCC 1.0* VCC V VIL Input LOW Voltage (Single-Ended) (Note 15) VEE VCC 1.4* VTHR 75 mV VEE VCC 1.4* VTHR 75 mV VEE VCC 1.4* VTHR 75 mV V VBB NECL Output Voltage Reference -1420 -1360 -1300 -1420 -1360 -1300 -1420 -1360 -1300 mV VIHCMR Input HIGH Voltage Common Mode Range (Note 16) (Differential Configuration) 0.0 V VMM CMOS Output Voltage Reference (Note 17) VMMT -150 VMMT VMMT + 150 VMMT -150 VMMT VMMT + 150 VMMT -150 VMMT VMMT + 150 mV RTIN Internal Input Termination Resistor 45 50 55 45 50 55 45 50 55 IIH Input HIGH Current (@ VIH) 30 100 30 100 30 100 A IIL Input LOW Current (@ VIL) 25 50 25 50 25 50 A VEE+1.2 0.0 VEE+1.2 0.0 VEE+1.2 NOTE: SiGe circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 13. Input and output parameters vary 1:1 with VCC. 14. All loading with 50 to VCC -2.0 volts. 15. VTHR is the voltage applied to the complementary input, typically VBB or VMM. 16. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 17. VMM typical = |VCC - VEE|/2 + VEE = VMMT *Typicals used for testing purposes. Table 8. AC CHARACTERISTICS for FCBGA-16 VCC = 0 V; VEE = -3.465 V to -2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V -40 °C Symbol Characteristic fmax Maximum Frequency (See Figure 4. Fmax/JITTER) (Note 18) tPLH, tPHL Propagation Delay to Output Differential tSKEW Duty Cycle Skew (Note 19) tJITTER RMS Random Clock Jitter Min Typ 10.7 12 90 110 130 3 0.2 Input Voltage Swing/Sensitivity (Differential Configuration) (Note 20) tr tf Output Rise/Fall Times @ 1 GHz (20% - 80%) Max 85°C Min Typ Max Min Typ 10.7 12 100 120 140 15 3 1 0.2 Max 10.7 12 105 125 145 ps 15 3 15 ps 1 0.2 1 Unit GHz ps fin < 10 GHz Peak-to-Peak Data Dependent Jitter fin < 10 Gb/s VINPP 25°C TBD 75 Q, Q 30 45 TBD 2600 75 75 20 40 TBD 2600 75 65 20 40 2600 mV 65 ps 18. Measured using a 400 mV source, 50% duty cycle clock source. All loading with 50 to VCC - 2.0 V. Input edge rates 40 ps (20% - 80%). 19. See Figure 6. tskew = |tPLH - tPHL| for a nominal 50% differential clock input waveform. 20. VINPP(max) cannot exceed VCC - VEE http://onsemi.com 6 NBSG16 Table 9. AC CHARACTERISTICS for QFN-16 VCC = 0 V; VEE = -3.465 V to -2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V -40 °C Symbol Characteristic fmax Maximum Frequency (See Figure 4. Fmax/JITTER) (Note 21) tPLH, tPHL Propagation Delay to Output Differential tSKEW Duty Cycle Skew (Note 22) tJITTER RMS Random Clock Jitter 25°C Min Typ Max 10.7 12 90 110 130 3 0.2 85°C Min Typ Max Min Typ 10.7 12 100 120 140 15 3 2 0.2 Max 10.7 12 95 125 145 ps 15 3 15 ps 2 0.2 2 Unit GHz ps fin < 10 GHz Peak-to-Peak Data Dependent Jitter fin < 10 Gb/s VINPP Input Voltage Swing/Sensitivity (Differential Configuration) (Note 23) tr tf Output Rise/Fall Times @ 1 GHz (20% - 80%) TBD 75 Q, Q 20 30 TBD 2600 75 50 20 TBD 30 2600 75 50 20 30 2600 mV 50 ps 21. Measured using a 400 mV source, 50% duty cycle clock source. All loading with 50 to VCC - 2.0 V. Input edge rates 40 ps (20% - 80%). 22. See Figure 6. tskew = |tPLH - tPHL| for a nominal 50% differential clock input waveform. 23. VINPP(max) cannot exceed VCC - VEE 700 8.5 7.5 500 6.5 OUTPUT AMP 5.5 400 4.5 Q Q 300 3.5 200 2.5 1.5 100 RMS JITTER 0.5 0 -0.5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 INPUT FREQUENCY (GHz) Figure 4. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs. Input Frequency (fin) at Ambient Temperature (Typical) http://onsemi.com 7 JITTEROUT ps (RMS) OUTPUT VOLTAGE AMPLITUDE (mV) 9.5 600 NBSG16 X = 17ps/Div Y = 70 mV/Div Figure 5. 10.709 Gb/s Diagram (3.0 V, 25C) D VINPP = VIH(D) - VIL(D) D Q VOUTPP = VOH(Q) - VOL(Q) Q tPHL tPLH Figure 6. AC Reference Measurement Q D Receiver Device Driver Device Q D 50 50 VTT VTT = VCC - 2.0 V Figure 7. Typical Termination for Output Driver and Device Evaluation (Refer to Application Note AND8020 - Termination of ECL Logic Devices) http://onsemi.com 8 NBSG16 PACKAGE DIMENSIONS FCBGA-16 BA SUFFIX PLASTIC 4 X 4 (mm) BGA FLIP CHIP PACKAGE CASE 489-01 ISSUE O LASER MARK FOR PIN 1 IDENTIFICATION IN THIS AREA -XD M -YK E M 0.20 3X e 4 3 2 FEDUCIAL FOR PIN A1 IDENTIFICATION IN THIS AREA 1 A 3 B b 16 X C D S VIEW M-M 0.15 M Z X Y 0.08 M Z 5 0.15 Z A A2 A1 16 X 4 -Z- 0.10 Z DETAIL K ROTATED 90 CLOCKWISE http://onsemi.com 9 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO DATUM PLANE Z. 4. DATUM Z (SEATING PLANE) IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 5. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE. DIM A A1 A2 b D E e S MILLIMETERS MIN MAX 1.40 MAX 0.25 0.35 1.20 REF 0.30 0.50 4.00 BSC 4.00 BSC 1.00 BSC 0.50 BSC NBSG16 PACKAGE DIMENSIONS 16 PIN QFN MN SUFFIX CASE 485G-01 ISSUE O NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION D APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. -XA M -Y- DIM A B C D E F G H J K L M N P R B N 0.25 (0.010) T 0.25 (0.010) T J R MILLIMETERS MIN MAX 3.00 BSC 3.00 BSC 0.80 1.00 0.23 0.28 1.75 1.85 1.75 1.85 0.50 BSC 0.875 0.925 0.20 REF 0.00 0.05 0.35 0.45 1.50 BSC 1.50 BSC 0.875 0.925 0.60 0.80 INCHES MIN MAX 0.118 BSC 0.118 BSC 0.031 0.039 0.009 0.011 0.069 0.073 0.069 0.073 0.020 BSC 0.034 0.036 0.008 REF 0.000 0.002 0.014 0.018 0.059 BSC 0.059 BSC 0.034 0.036 0.024 0.031 C 0.08 (0.003) T -T- K SEATING PLANE E H G L 5 8 4 9 F 12 1 16 D 13 P NOTE 3 0.10 (0.004) M T X Y ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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PUBLICATION ORDERING INFORMATION Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: [email protected] JAPAN: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Phone: 81-3-5773-3850 ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. N. American Technical Support: 800-282-9855 Toll Free USA/Canada http://onsemi.com 10 NBSG16/D