VICOR B048A120T20

V•I Chip – BCM
Bus Converter Module
TM
B048K120T20
+ +
–K –
• >96% efficiency
• 200 Watt (300 Watt for 1 ms)
• 125°C operation
• High density – up to 800 W/in3
• 1 µs transient response
• Small footprint – 200 W/in
• >3.5 million hours MTBF
• Low weight – 0.5 oz (14 g)
• No output filtering required
• ZVS/ZCS isolated sine
amplitude converter
• BGA or J-Lead packages
2
Product Description
The V•I Chip Bus Converter Module
(BCM) is a high efficiency (>96%),
narrow input range Voltage
Transformation Module (VTM) operating
from a 48 Vdc bus to deliver an isolated
12 V secondary for Intermediate Bus
Architecture applications. The BCM may
be used to power non-isolated POL
converters or as an independent 12 V
source. Due to the fast response time and
low noise of the BCM, the need for
limited life aluminum electrolytic or
tantalum capacitors at the input of POL
converters is reduced—or eliminated—
resulting in savings of board area,
materials and total system cost.
The BCM achieves a power density of
800 W/in3 and may be surface mounted
with a profile as low as 0.16" (4mm) over
the PCB. Its V•I Chip power package is
compatible with on-board or in-board
surface mounting. The V•I Chip package
provides flexible thermal management
through its low Junction-to-Case and
Junction-to-BGA thermal resistance.
Owing to its high conversion efficiency
and safe operating temperature range, the
BCM does not require a discrete heat sink
in typical applications. It is also
compatible with heat sink options,
assuring low junction temperatures and
long life in the harshest environments.
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Vin = 42 - 53 V
Vout = 10.5 - 13.25 V
Iout = 17.0 A
K = 1/4
Rout = 25 mΩ max
V•I
• 48 V to 12 V V•I Chip Converter
1
©
Actual size
Absolute Maximum Ratings
Parameter
Values
Unit
-1.0 to 60.0
Vdc
+In to -In
100
Vdc
PC to -In
-0.3 to 7.0
Vdc
TM to -In
-0.3 to 7.0
Vdc
+Out to -Out
-0.5 to 15.0
Vdc
2250
Vdc
-40 to 125
°C
+In to -In
Isolation voltage
Operating junction temperature
Output current
Peak output current
Case temperature during reflow
Storage temperature
Notes
For 100 ms
Input to Output
T grade; See note 2
17.0
A
Continuous
25
A
For 1 ms
208
°C
-40 to 150
°C
Output power
200
W
Continuous
Peak output power
300
W
For 1 ms
Thermal Resistance
Symbol
Parameter
Typ
Max
Units
RθJC
Junction-to-case
1.1
1.5
°C/W
RθJB
Junction-to-BGA
2.1
2.5
°C/W
RθJA
Junction-to-ambient 3
6.5
7.2
°C/W
RθJA
Junction-to-ambient 4
5.0
5.5
°C/W
Notes
1. For complete product matrix see chart on page 10.
2. The referenced junction is defined as the semiconductor having the highest temperature. This
temperature is monitored by the temperature monitor (TM) signal and by a shutdown comparator.
3. B048K120T20 surface mounted in-board to a 2" x 2" FR4 board, 4 layers 2 oz Cu, 300 LFM.
4. B048L120T20 (0.25"H optional Pin Fins) surface mounted on FR4 board, 300 LFM.
V•I Chip Bus Converter
B048K120T20
Rev. 2.2
Page 1 of 16
Specifications
INPUT (Conditions are at 48 Vin, full load, and 25°C ambient unless otherwise specified)
Parameter
Input voltage range
Input dV/dt
Input undervoltage turn-on
Input undervoltage turn-off
Input overvoltage turn-on
Input overvoltage turn-off
Input quiescent current
Inrush current overshoot
Input current
Input reflected ripple current
No load power dissipation
Internal input capacitance
Internal input inductance
Recommended external input capacitance
Min
42
Typ
48
Max
53
1
42
37
53
1.5
2.9
30
2.50
2
20
10
59
1.8
4.65
50
3.00
Unit
Vdc
V/µs
Vdc
Vdc
Vdc
Vdc
mA
A
Adc
mA p-p
W
µF
nH
µF
Note
PC low
Using test circuit in Fig.22; See Fig.1
Using test circuit in Fig.22; See Fig.4
200 nH maximum source inductance; See Fig.22
INPUT WAVEFORMS
Figure 1— Inrush transient current at full load and 48 Vin with
PC enabled
Figure 2— Output voltage turn-on waveform with PC enabled
at full load and 48 Vin
Figure 3—Output voltage turn-on waveform with input turn-on
at full load and 48 Vin
Figure 4— Input reflected ripple current at full load and 48 Vin
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V•I Chip Bus Converter
B048K120T20
Rev. 2.2
Page 2 of 16
Specifications, continued
OUTPUT (Conditions are at 48 Vin, full load, and 25°C ambient unless otherwise specified)
Parameter
Rated DC current
Min
0
Typ
Peak repetitive current
DC current limit
Current share accuracy
Efficiency
10A load
Full load
Internal output inductance
Internal output capacitance
Load capacitance
Output overvoltage setpoint
Output ripple voltage
No external bypass
1µF bypass capacitor
Average short circuit current
Effective switching frequency
Line regulation
K
Load regulation
ROUT
Transient response
17.0
95.5
95.0
21.0
5
Max
17.0
Unit
Adc
25.0
A
26.0
10
Adc
%
96.2
95.7
1.6
12
1000
14.75
150
2.8
95
12
200
3.5
0.245
0.250
0.255
4.2
Response time
Recovery time
Output overshoot
Input turn-on
PC enable
Output turn-on delay
From application of power
From release of PC pin
Max pulse width 1ms, max duty cycle 10%,
baseline power 50%
See Parallel Operation on page 12
%
%
nH
µF
µF
Vdc
See Fig.5
See Fig.5
mV
mV
mA
MHz
See Figs.7 and 9
See Fig.8
Effective value
Fixed, 1.75 MHz per phase
VOUT=K•VIN at no load
25
Voltage overshoot
Note
mΩ
See Fig. 26
230
40
200
1
mV
mV
ns
µs
0-17.0A load step, see Fig.10
1.2-15A load step with 1µF bypass, see Fig. 11
See Figs.10 and 11
See Figs.10 and 11
0
0
mV
mV
No output filter; See Fig.3
No output filter; See Fig.2
ms
ms
No output filter; See Fig.3
No output filter; See Fig.2
250
50
OUTPUT WAVEFORMS
Efficiency vs. Output Power
Power Dissipation
10
96
9
Power Dissipation (W)
97
Efficiency (%)
95
94
93
92
91
90
89
8
7
6
5
4
3
2
1
0
0
25
50
75
100
125
150
175
200
0
Figure 5— Efficiency vs. output power at 12 Vout
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25
50
75
100
125
150
175
200
Output Power (W)
Output Power (W)
Figure 6—Power dissipation as a function of output power
V•I Chip Bus Converter
B048K120T20
Rev. 2.2
Page 3 of 16
Specifications, continued
Figure 7— Output voltage ripple at full load and 48 Vin;
without any external bypass capacitor.
Figure 8—Output voltage ripple at full load and nominal Vin
with 1 µF ceramic external bypass capacitor.
VOUT
IOUT
7 A/div
Figure 9— Output voltage ripple vs. output power at 48 Vin
without any external bypass capacitor.
Figure 10— 0-17 A load step with 100 µF input capacitance and
no output capacitance.
VOUT
IOUT
7 A/div
Figure 11— 17-0A load step with 100 µF input capacitance and
no output capacitance.
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V•I Chip Bus Converter
B048K120T20
Rev. 2.2
Page 4 of 16
Specifications, continued
GENERAL
Parameter
MTBF
MIL-HDBK-217F
Telcordia TR-NT-000332
Telcordia SR-332
Demonstrated
Isolation specifications
Voltage
Capacitance
Resistance
Agency approvals (pending)
Min
Typ
Max
3.6
4.2
TBD
TBD
2,250
5,000
6,500
10
Unit
Note
Mhrs
Mhrs
hrs
hrs
25°C, GB
Vdc
pF
MΩ
Input to Output
Input to Output
Input to Output
UL/CSA 60950, EN 60950
Low Voltage Directive
See mechanical drawing, Figs.15 and 17
cTÜVus
CE Mark
Mechanical parameters
Weight
Dimensions
Length
Width
Height
0.5 / 14
oz / g
1.26 / 32
0.85 / 21.5
0.24 / 6
in / mm
in / mm
in / mm
Auxiliary Pins (Conditions are at nominal line, full load, and 25°C ambient unless otherwise specified)
Parameter
Primary control (PC)
DC voltage
Module disable voltage
Module enable voltage
Current limit
Enable delay time
Disable delay time
Temperature Monitor (TM)
27°C setting
Temperature coefficient
Full range accuracy
Current limit
Min
Typ
Max
Unit
Note
4.8
2.4
5.0
2.5
2.5
2.5
50
4
5.2
V
V
V
mA
ms
µs
Source only
See Fig.2
See Fig.12
3.00
10
±5
3.05
2.4
2.95
100
Figure 12— VOUT at full load vs. PC disable
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2.6
2.9
10
V
mV/°C
°C
µA
Operating junction temperature
Operating junction temperature
Source only
Figure 13— PC signal during fault
V•I Chip Bus Converter
B048K120T20
Rev. 2.2
Page 5 of 16
Specifications, continued
THERMAL
Symbol
Parameter
Over temperature shutdown
Thermal capacity
Min
125
Typ
130
0.61
Max
135
Unit
°C
Ws/°C
RθJC
Junction-to-case thermal impedance
1.1
1.5
°C/W
RθJB
Junction-to-BGA thermal impedance
2.1
2.5
°C/W
RθJA
Junction-to-ambient 1
6.5
7.2
°C/W
RθJA
Junction-to-ambient 2
5.0
5.5
°C/W
Note
Junction temperature
BGA package
Notes
1. B048K120T20 surface mounted in-board to a 2" x 2" FR4 board, 4 layers 2 oz Cu, 300 LFM.
2. B048K120T20 (0.25"H optional Pin Fins) surface mounted on FR4 board, 300 LFM.
V•I CHIP STRESS DRIVEN PRODUCT QUALIFICATION PROCESS
Test
High Temperature Operational Life (HTOL)
Temperature Cycling
High Temperature Storage
Moisture Resistance
Temperature Humidity Bias Testing (THB)
Pressure Cooker Testing (Autoclave)
Highly Accelerated Stress Testing (HAST)
Solvent Resistance/Marking Permanency
Mechanical Vibration
Mechanical Shock
Electro Static Discharge Testing – Human Body Model
Electro Static Discharge Testing – Machine Model
Highly Accelerated Life Testing (HALT)
Dynamic Cycling
Standard
JESD22-A-108-B
JESD22-A-104B
JESD22-A-103A
JESD22-A113-B
EIA/JESD22-A-101-B
JESD22-A-102-C
JESD22-A-110B
JESD22-B-107-A
JESD22-B-103-A
JESD22-B-104-A
EIA/JESD22-A114-A
EIA/JESD22-A115-A
Per Vicor Internal
Test Specification
Environment
125°C, Vmax, 1,008 hrs
-55°C to 125°C, 1,000 cycles
150°C, 1,000 hrs
Moisture Sensitivity Level 5
85°C, 85% RH, Vmax, 1,008 hrs
121°C, 100% RH, 15 PSIG, 96 hrs
130°C, 85% RH, Vmax, 96 hrs
Solvents A, B & C as defined
20 g peak, 20-2,000 Hz, test in X, Y & Z directions
1,500 g peak 0.5 ms pulse duration, 5 pulses in 6 directions
Meets or exceeds 2,000 Volts
Meets or exceeds 200 Volts
Per Vicor Internal
Test Specification
Constant line, 0-100% load,
Operation limits verified, destruct margin determined
-20°C to 125°C
V•I CHIP BALL GRID ARRAY INTERCONNECT QUALIFICATION
Test
BGA Daisy-Chain Thermal Cycling
Ball Shear
Bend Test
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Standard
IPC-SM-785
IPC-9701
IPC-9701
IPC J-STD-029
IPC J-STD-029
V•I Chip Bus Converter
Environment
TC3, -40 to 125°C at <10°C/min,
10 min dwell time.
No failure through intermetallic.
Deflection through 4 mm.
B048K120T20
Rev. 2.2
Page 6 of 16
Pin/Control Functions
+IN/-IN – DC Voltage Input Ports
The V•I Chip input voltage range should not be exceeded. An
internal under/over voltage lockout-function prevents operation
outside of the normal operating input range. The BCM turns
ON within an input voltage window bounded by the “Input
under-voltage turn-on” and “Input over-voltage turn-off” levels,
as specified. The V•I Chip may be protected against accidental
application of a reverse input voltage by the addition of a
rectifier in series with the positive input, or a reverse rectifier in
shunt with the positive input located on the load side of the
input fuse.
The connection of the V•I Chip to its power source should be
implemented with minimal distribution inductance. If the
interconnect inductance exceeds 100 nH, the input should be
bypassed with a RC damper to retain low source impedance and
stable operation. With an interconnect inductance of 200 nH, the
RC damper may be 10 µF in series with 0.3Ω. A single
electrolytic or equivalent low-Q capacitor may be used in place
of the series RC bypass.
4 3
+Out
-Out
+Out
-Out
TM – Temperature Monitor
The Temperature Monitor port monitors the highest junction
temperature of the BCM. This output may be used to provide
feedback and validation of the thermal management of
V•I Chips, as applied in diverse power systems and environments.
At 300°K (+27°C), the TM output is nominally 3.0 Vdc. The
TM output is proportional to temperature and varies at 10 mV/°C.
The TM accuracy is typically +/-5°C. A kelvin connection to
the –IN port of the BCM should be used as the ground return of
the TM signal to maintain the specified accuracy.
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+In
Temp.
Monitor
RSV
Primary Control
-In
Figure 14—BCM BGA configuration
Signal
Name
+In
–In
TM
PC
Enable/Disable – If the PC port is left floating, the BCM
output is enabled. Once this port is pulled lower than
2.4 Vdc with respect to –IN, the output is disabled. This
action can be realized by employing a relay, opto-coupler,
or open collector transistor. Refer to Figures 1-3, 12 and 13
for the typical Enable/Disable characteristics. This port
should not be toggled at a rate higher than 1 Hz. The PC
port should also not be driven by or pulled up to an external
voltage source.
Alarm – The BCM contains circuitry that monitors output
overload, input over voltage or under voltage, and internal
junction temperatures. In response to an abnormal
condition in any of the monitored parameters, the PC port
will toggle. Refer to Figure 13 for PC alarm characteristics.
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
Bottom View
PC – Primary Control
The Primary Control port is a multifunction node that provides
the following functions:
Primary Auxiliary Supply – The PC port can source up to
2.4 mA at 5.0 Vdc. The PC port should never be used to
sink current.
21
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
+Out
–Out
BGA
Designation
A1-L1, A2-L2
AA1-AL1, AA2-AL2
P1, P2
V1, V2
A3-G3, A4-G4,
U3-AC3, U4-AC4
J3-R3, J4-R4,
AE3-AL3, AE4-AL4
+OUT/-OUT – DC Voltage Output Ports
Two sets of contacts are provided for the +OUT port. They
must be connected in parallel with low interconnect resistance.
Similarly, two sets of contacts are provided for the –OUT port.
They must be connected in parallel with low interconnect
resistance. Within the specified operating range, the average
output voltage is defined by the Level 1 DC behavioral model
of Figure 26. The current source capability of the BCM is rated
in the specifications section of this document.
The low output impedance of the BCM, reduces or eliminates
the need for limited life aluminum electrolytic or tantalum
capacitors at the input of POL converters.
Total load capacitance at the output of the BCM should not
exceed the specified maximum. Owing to the wide bandwidth
and low output impedance of the BCM, low frequency bypass
capacitance and significant energy storage may be more
densely and efficiently provided by adding capacitance at the
input of the BCM.
V•I Chip Bus Converter
B048K120T20
Rev. 2.2
Page 7 of 16
Mechanical Drawings
1,00
0.039
5,9
0.23
21,5
0.85
SOLDER BALL
#A1 INDICATOR
0.020
(106) X Ø 0.51
1,00
0.039
18,00
0.709
9,00
0.354
SOLDER BALL
SOLDER BALL #A1
OUTPUT
28,8
1.13
C
L
15,00
0.591
16,0
0.63
C
L
1,6
0.06
TOP VIEW (COMPONENT SIDE)
30,00
1.181
INPUT
32,0
1.26
OUTPUT
INPUT
1,00 TYP
0.039
1,00
0.039
BOTTOM VIEW
3,9
0.15
15,6
0.62
NOTES:
mm
1- DIMENSIONS ARE inch .
2- UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE:
.X/[.XX] = +/-0.25/[.01]; .XX/[.XXX] = +/-0.13/[.005]
3- PRODUCT MARKING ON TOP SURFACE
SEATING PLANE
Figure 15—BCM BGA mechanical outline; In-board mounting
IN-BOARD MOUNTING
BGA surface mounting requires a
cutout in the PCB in which to recess the V•I Chip
1,50
0.059
( 1,00 )
0.039
(ø
0,51
)
0.020
ø 0,53 PLATED VIA
0.021
CONNECT TO
INNER LAYERS
0,50
0.020
SOLDER MASK
DEFINED PADS
0,50
0.020
( 1,00 )
0.039
1,00
0.039
1,00
0.039
18,00
0.709
1,00
0.039
9,00
0.354
SOLDER PAD #A1
1
(4) X 6,00
0.236
+IN
+OUT1
(2) X 10,00
0.394
-OUT1
(COMPONENT SIDE SHOWN)
29,26
1.152
RSV
TM
RECOMMENDED LAND AND VIA PATTERN
PCB CUTOUT
24,00
0.945
-OUT2
-IN
PC
+OUT2
20,00
0.787 17,00
0.669 15,00 13,00
0.591
0.512
16,00
0.630
NOTES:
mm
1- DIMENSIONS ARE inch .
2- UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE:
.X/[.XX] = +/-0.25/[.01]; .XX/[.XXX] = +/-0.13/[.005]
8,00
0.315
31
0,51
(106) X ø
0.020
0,37
0.015
8,08
0.318
SOLDER MASK
DEFINED PAD
16,16
0.636
1,6
(4) X R 0.06
Figure 16—BCM BGA PCB land/VIA layout information; In-board mounting
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V•I Chip Bus Converter
B048K120T20
Rev. 2.2
Page 8 of 16
Mechanical Drawings
6,1
0.24
22,0
0.87
9,3
0.37
15,99
0.630
3,01
0.118
3,01
0.118
(4) PL. 7,10
0.280
OUTPUT
INPUT
INPUT
24,00
0.945
OUTPUT
32,0
1.26
11,10 (2) PL.
0.437
CL
16,00
0.630
15,55
0.612
12,94
0.509
8,00
0.315
(Elevated Option)
20,00
0.787
C
L
0,45
0.018
TOP VIEW (COMPONENT SIDE)
14,94
0.588
16,94
0.667
BOTTOM VIEW
NOTES:
1- DIMENSIONS ARE mm/[INCH].
(Elevated Option)
2- UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE:
.X/[.XX] = +/-0.25/[.01]; .XX/[.XXX] = +/-0.13/[.005]
3.9
0.15
3- PRODUCT MARKING ON TOP SURFACE.
Figure 17—BCM J-lead mechanical outline; On-board mounting
3,26
0.128
3,26
0.128
15,74
0.620
0,51
TYP
0.020
(2) X14,94
0.588
-OUT2
12,94
(2) X 0.509
-IN
20,00
(2) X 0.787
(2) X16,94
0.667
+OUT2
PC RSV TM
1,60
0.063
7,48
(8) X 0.295
-OUT1
(6) X
+OUT1
(4) X 11,48
0.452
+IN
1,38
0.054 TYP
(2) X 24,00
0.945
(2) X 16,00
0.630
8,00
(2) X 0.315
RECOMMENDED LAND PATTERN
(COMPONENT SIDE SHOWN)
NOTES:
1- DIMENSIONS ARE mm/[INCH].
2- UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE:
.X/[.XX] = +/-0.25/[.01]; .XX/[.XXX] = +/-0.13/[.005]
Figure 18— BCM J-lead PCB land layout information; On-board mounting
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V•I Chip Bus Converter
B048K120T20
Rev. 2.2
Page 9 of 16
Part Numbering and Configuration Options
V•I Chip BUS CONVERTER PART NUMBERING
B
048
Bus Converter
Module
Input Voltage
Designator
K
Configuration Options
A = On-board elevated (Fig.21)
F = On-board (Fig.20)
120
T
20
Output Voltage
Designator
(=Vout x10)
Product Grade Temperatures (°C)
Grade
Storage
Operating
T
-40 to150 -40 to125
M
-65 to 150 -55 to 125
Output Power
Designator
(=Pout/10)
K = In-board (Fig.19)
CONFIGURATION OPTIONS
IN-BOARD*
ON-BOARD*
(Package K)
(Package F)
IN-BOARD WITH 0.25"
PIN FINS**
ON-BOARD WITH 0.25"
PIN FINS**
1190 W/in3
800 W/in3
445 W/in3
360 W/in3
Junction-Board
Thermal Resistance
2.1 °C/W
2.4 °C/W
2.1 °C/W
2.4 °C/W
Junction-Case
Thermal Resistance
1.1 °C/W
1.1 °C/W
N/A
N/A
Junction-Ambient
Thermal Resistance 300LFM
6.5 °C/W
6.8 °C/W
5.0 °C/W
5.0 °C/W
CONFIGURATION
Effective Power Density
*Surface mounted to a 2" x 2" FR4 board, 4 layers 2 oz Cu
**Pin Fin heat sink available as a separate item
21.5
0.85
22.0
0.87
32.0
1.26
32.0
1.26
4.0
0.16
6.3
0.25
ON–BOARD MOUNT
IN–BOARD MOUNT
(V•I Chip recessed into PCB)
mm
in
mm
in
Figure 19—In-board mounting – package K
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Figure 20— On-board mounting – package F
V•I Chip Bus Converter
B048K120T20
Rev. 2.2
Page 10 of 16
Configuration Options (Cont.)
22.0
0.87
32.0
1.26
9.5
0.37
mm
in
Figure 21— On-board elevated mounting – package A
Input reflected ripple
measurement point
F1
7A
Fuse
+Out
+In
R1
0.30 Ω
C2
C1
10 µF
ceramic
+
Enable/Disable Switch
R3
-Out
0.47 µF
ceramic
R2
TM
RSV
PC
2K Ω
SW1
0.1 Ω
BCM
D1
-In
K
Ro
+Out
Load
C3
1 µF
ceramic
–
-Out
+
Temperature Monitor
–
Notes:
Source inductance should be no more than 200 nH. If source inductance is
greater than 200 nH, additional bypass capacitance is required.
C3 should be placed close to the load.
D1 power good indicator will dim when a module fault is detected.
TM should always be referenced to SG.
Figure 22—BCM test circuit
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V•I Chip Bus Converter
B048K120T20
Rev. 2.2
Page 11 of 16
Application Note
Parallel Operation
power at up to 80°C ambient temperature. At 100 W of output
power, operating ambient temperature extends to 100°C.
The BCM will inherently current share when properly
configured in an array of BCMs. Arrays may be used for
higher power or redundancy in an application.
CASE 2—Conduction to the PCB
Current sharing accuracy is maximized when the source and
load impedance presented to each BCM within an array are equal.
The low thermal resistance Junction-to-BGA, RθJB, allows
use of the PCB to exchange heat from the V•I Chip,
including convection from the PCB to the ambient or
conduction to a cold plate.
The BCM power train and control architecture allow
bi-directional power transfer, including reverse power
processing from the BCM output to its input. Reverse power
transfer is enabled if the BCM input is within its operating
range and the BCM is otherwise enabled. The BCM’s ability to
process power in reverse improves the BCM transient response
to an output load dump.
Thermal Management
The high efficiency of the V•I Chip results in relatively low
power dissipation and correspondingly low generation of heat.
The heat generated within internal semiconductor junctions is
coupled with low effective thermal resistances, RθJC and RθJB,
to the V•I Chip case and its Ball Grid Array allowing thermal
management flexibility to adapt to specific application
requirements (Fig. 25).
For example, with a V•I Chip surface mounted on a 2" x 2"
area of a multi-layer PCB, with an aggregate 8 oz of effective
copper weight, the total Junction-to-Ambient thermal
resistance, RθJA, is 6.5°C/W in 300 LFM air flow (see
Thermal Resistance section, page 1). Given a maximum
junction temperature of 125°C and 9 W dissipation at 200 W of
output power, a temperature rise of 59°C allows the V•I Chip to
operate at rated output power at up to 66°C ambient temperature.
210
180
Output Power
The recommended method to achieve matched impedances is to
dedicate common copper planes within the PCB to deliver and
return the current to the array, rather than rely upon traces of
varying lengths. In typical applications the current being
delivered to the load is larger than that sourced from the input,
allowing traces to be utilized on the input side if necessary. The
use of dedicated power planes is, however, preferable.
150
120
90
60
30
0
-40
-20
0
20
40
60
80
100
120
140
Operating Junction Temperature
CASE 1 Convection via optional Pin Fins to air.
Figure 24— Thermal derating curve
BCM with 0.25'' optional Pin Fins
10
9
8
Tja
If the application is in a typical environment with forced
convection over the surface of the PCB and greater than 0.4"
headroom, a simple thermal management strategy is to procure
the optional Pin Fins for the V•I Chips. The total Junction-toAmbient thermal resistance, RθJA, of a surface mounted
V•I Chip with optional 0.25" Pin Fins is 5°C/W in 300 LFM air
flow (Fig.26). At full rated output power of 200 W, the heat
generated by the BCM is approximately 9 W (Fig.6). Therefore,
the junction temperature rise to ambient is approximately 45°C.
Given a maximum junction temperature of 125°C, a temperature
rise of 45°C allows the V•I Chip to operate at rated output
7
6
5
4
θJC = 1.1 °C/W
3
0
100
200
300
400
500
600
θJB = 2.1 °C/W
Airflow (LFM)
Figure 23—Thermal resistance
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Figure 25—Junction-to-ambient thermal resistance of BCM
with 0.25" Pin Fins (Pin Fins available as a separate item.)
V•I Chip Bus Converter
B048K120T20
Rev. 2.2
Page 12 of 16
Application Note (continued)
The thermal resistance of the PCB to the surrounding
environment in proximity to V•I Chips may be reduced by low
profile heat sinks surface mounted to the PCB.
The PCB may also be coupled to a cold plate by low thermal
resistance standoff elements as a means of achieving effective
cooling for an array of V•I Chips, without a direct interface to
their case.
external thermal resistances provides an efficient thermal
management strategy as it reduces total thermal resistance. This
may be readily estimated as the parallel network of two pairs of
series configured resistors.
The TM (Temperature Monitor) port monitors the V•I Chip
junction temperature and provides feedback and validation of the
thermal management of V•I Chips, as applied in diverse power
systems and environments.
CASE 3—Combined direct convection to the air and conduction
to the PCB.
Parallel use of the V•I Chip internal thermal resistances
(including Junction-to-Case and Junction-to-BGA) in series with
V•I Chip BUS CONVERTER LEVEL 1 DC BEHAVIORAL MODEL for 48 V to 12 V, 200 W
ROUT
IOUT
+
+
20 mΩ
1/
4
VIN
V•I
• Iout
+
+
–
IQ
52 mA
1/
4 • Vin
VOUT
–
K
-
–
©
Figure 26—This model characterizes the DC operation of the V•I Chip bus converter, including the converter transfer function
and its losses. The model enables estimates or simulations of output voltage as a function of input voltage and output load, as
well as total converter power dissipation or heat generation.
V•I Chip BUS CONVERTER LEVEL 2 TRANSIENT BEHAVIORAL MODEL for 48 V to 12 V, 200 W
8.5 nH
ROUT
IOUT
L IN = 20 nH
+
20 mΩ
RCIN
2.0 mΩ
CIN
VIN
2 µF
IQ
52 mA
1/
4•
40 mΩ
V•I
Iout
+
+
–
1/ •
4
LOUT = 1.6 nH
RCOUT
+
0.3 mΩ
Vin
COUT
12 µF
VOUT
–
K
–
–
©
Figure 27—This model characterizes the AC operation of the V•I Chip bus converter including response to output load or input
voltage transients or steady state modulations. The model enables estimates or simulations of input and output voltages under
transient conditions, including response to a stepped load with or without external filtering elements.
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V•I Chip Bus Converter
B048K120T20
Rev. 2.2
Page 13 of 16
Application Note (continued)
Input Impedance Recommendations
To take full advantage of the BCM capabilities, the impedance
presented to its input terminals must be low from DC to
approximately 5 MHz. The source should exhibit low inductance
(less than 100 nH) and should have a critically damped response.
If the interconnect inductance exceeds 100 nH, the BCM input
pins should be bypassed with an RC damper (e.g., 8 µF in series
with 0.3 ohm) to retain low source impedance and stable
operations. Given the wide bandwidth of the BCM, the source
response is generally the limiting factor in the overall system
response.
Anomalies in the response of the source will appear at the output
of the BCM multiplied by its K factor. The DC resistance of the
source should be kept as low as possible to minimize voltage
deviations. This is especially important if the BCM is operated
near low or high line as the over/under voltage detection circuitry
could be activated.
Input Fuse Recommendations
V•I Chips are not internally fused in order to provide flexibility
in power system configuration. However, input line fusing of
V•I Chips must always be incorporated within the power system.
A fast acting fuse, such as NANO2 FUSE 451 Series 7 A 125 V,
is required to meet safety agency Conditions of Acceptability.
The input line fuse should be placed in series with the +IN port.
Application Circuits
VL = 10.5 - 13.25 V
+Out
+In
-Out
48 Vin
(42 - 53 Vdc)
BCM
TM
RSV
PC
-In
K
Ro
+Out
-Out
NiPOL
1
NiPOL
2
NiPOL
3
NiPOL
4
LOAD
1
LOAD
2
LOAD
3
LOAD
4
Figure 28—The BCM provides an isolated, loosely regulated output from a narrow range input ideal for driving non-isolated point
of load converters (niPOLs)
In the following figure;
K = BCM Transformation Ratio
Ro = BCM Output Resistance
Vo = BCM Output
Vf = PRM Output (Factorized Bus Voltage)
VL = Desired Load Voltage
VS = PRM Output Set Point Voltage
FPA Local Loop
Vo = VL – Io • Ro
VC
PC
TM
IL
IM
PR
PRM-AL
+In
VH
SC
SG
CP
RL
CD
Factorized
Power Bus
+Out
48 Vin
(36 - 75 Vdc)
Vf = Vs =
–In
VL
K
–Out
P048K055T24AL
Vs range = 42 – 53 Vdc
+Out
+In
-Out
TM
RSV
PC
-In
BCM
K
Ro
+Out
L
O
A
D
-Out
B048K120T20
( k=1/4: Ro=25 mΩ)
Figure 29—The PRM regulates its output to provide a constant factorized bus voltage. The output voltage is the nominal load
voltage, Vo, at no load and decreases with load at a constant rate equal to the BCM output resistance Ro.
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V•I Chip Bus Converter
B048K120T20
Rev. 2.2
Page 14 of 16
Application Note (continued)
V•I Chip Soldering Recommendations
V•I Chip modules are intended for reflow soldering processes.
The following information defines the processing conditions
required for successful attachment of a V•I Chip to a PCB.
Failure to follow the recommendations provided can result in
aesthetic and functional failure of the module.
Inspection
For the BGA-version, a visual examination of the post-reflow
solder joints should show relatively columnar solder joints with
no bridges. An inspection using x-ray equipment can be done,
but the module’s materials may make imaging difficult.
Storage
V•I Chip modules are currently rated at MSL 5. Exposure to
ambient conditions for more than 72 hours requires a 24 hour
bake at 125ºC to remove moisture from the package.
The J-Lead version’s solder joints should conform to IPC 12.2
• Properly Wetted Fillet must be evident
• Heel fillet height must exceed lead thickness plus solder thickness.
Solder Paste Stencil Design
Solder paste is recommended for a number of reasons, including
overcoming minor solder sphere co-planarity issues as well as
simpler integration into overall SMD process.
63/37 SnPb, either no-clean or water-washable, solder paste
should be used. Pb-free development is underway.
The recommended stencil thickness is 6 mils. The apertures
should be 20 mils in diameter for the In-Board (BGA)
application and 0.9-0.9:1 for the On-Board (J-Leaded).
Pick & Place
In-Board (BGA) modules should be placed as accurately as
possible to minimize any skewing of the solder joint; a maximum
offset of 10 mils is allowable. On-Board (J-Leaded) modules
should be placed within ±5 mils.
To maintain placement position, the modules should not be
subjected to acceleration greater than 500 in/sec2 prior to reflow.
Reflow
There are two temperatures critical to the reflow process; the
solder joint temperature and the module’s case temperature. The
solder joint’s temperature should reach at least 220ºC, with a
time above liquidus (183ºC) of ~30 seconds.
The module’s case temperature must not exceed 208ºC at
anytime during reflow.
Removal and Rework
V•I Chip modules can be removed from PCBs using special tools
such as those made by Air-Vac. These tools heat a very localized
region of the board with a hot gas while applying a tensile force
to the component (using vacuum). Prior to component heating
and removal, the entire board should be heated to 80-100ºC to
decrease the component heating time as well as local PCB
warping. If there are adjacent moisture-sensitive components, a
125ºC bake should be used prior to component removal to
prevent popcorning. V•I Chip modules should not be expected to
survive a removal operation.
239
Joint Temperature, 220ºC
Case Temperature, 208ºC
183
165
degC
91
16
Soldering Time
Figure 30—Thermal profile diagram
Because of the ∆T needed between the pin and the case, a forcedair convection oven is preferred for reflow soldering. This
reflow method generally transfers heat from the PCB to the
solder joint. The module’s large mass also reduces its
temperature rise. Care should be taken to prevent smaller
devices from excessive temperatures. Reflow of modules onto a
PCB using Air-Vac-type equipment is not recommended due to
the high temperature the module will experience.
Figure 31— Properly reflowed V•I Chip J-Lead.
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V•I Chip Bus Converter
B048K120T20
Rev. 2.2
Page 15 of 16
Warranty
Vicor products are guaranteed for two years from date of shipment against defects in material or workmanship when in normal use and service. This
warranty does not extend to products subjected to misuse, accident, or improper application or maintenance. Vicor shall not be liable for collateral or
consequential damage. This warranty is extended to the original purchaser only.
EXCEPT FOR THE FOREGOING EXPRESS WARRANTY, VICOR MAKES NO WARRANTY, EXPRESS OR IMPLIED, INCLUDING, BUT NOT
LIMITED TO, THE WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
Vicor will repair or replace defective products in accordance with its own best judgement. For service under this warranty, the buyer must contact
Vicor to obtain a Return Material Authorization (RMA) number and shipping instructions. Products returned without prior authorization will be
returned to the buyer. The buyer will pay all charges incurred in returning the product to the factory. Vicor will pay all reshipment charges if the
product was defective within the terms of this warranty.
Information published by Vicor has been carefully checked and is believed to be accurate; however, no responsibility is assumed for inaccuracies.
Vicor reserves the right to make changes to any products without further notice to improve reliability, function, or design. Vicor does not assume any
liability arising out of the application or use of any product or circuit; neither does it convey any license under its patent rights nor the rights of
others. Vicor general policy does not recommend the use of its components in life support applications wherein a failure or malfunction may directly
threaten life or injury. Per Vicor Terms and Conditions of Sale, the user of Vicor components in life support applications assumes all risks of such use
and indemnifies Vicor against all damages.
Vicor’s comprehensive line of power solutions includes high density AC-DC and DC-DC modules
and accessory components, fully configurable AC-DC and DC-DC power supplies,
and complete custom power systems.
Information furnished by Vicor is believed to be accurate and reliable. However, no responsibility is assumed by Vicor for its use.
Vicor components are not designed to be used in applications, such as life support systems, wherein a failure or malfunction could
result in injury or death. All sales are subject to Vicor’s Terms and Conditions of Sale, which are available upon request.
Specifications are subject to change without notice.
Intellectual Property Notice
Vicor and its subsidiaries own Intellectual Property (issued U.S. and Foreign Patents and
pending patent applications) relating to the product described in this data sheet including;
•
•
•
•
•
The electrical and thermal utility of the V•I Chip package
The design of the V•I Chip package
The Power Conversion Topology utilized in the V•I Chip package
The Control Architecture utilized in the V•I Chip package
The Factorized Power Architecture.
Purchase of this product conveys a license to use it. However, no responsibility is assumed by Vicor for any infringement of patents
or other rights of third parties which may result from its use. Except for its use, no license is granted by implication
or otherwise under any patent or patent rights of Vicor or any of its subsidiaries.
Anybody wishing to use Vicor proprietary technologies must first obtain a license.
Potential users without a license are encouraged to first contact Vicor’s Intellectual Property Department.
Vicor Corporation
25 Frontage Road • Andover, MA, USA 01810
Tel: 800-735-6200, Fax: 978-475-6715
email
Vicor Express: [email protected], Technical Support: [email protected]
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V•I Chip Bus Converter
B048K120T20
Rev. 2.2
P/N 26575
Page 16 of 16
07/04/10M