Revised October 1998 V320 8-Bit Registered Bus Transceiver General Description Features The V320 is an 8-bit universal bus transceiver designed for high speed interfacing with the VME320 backplane. It has output characteristics optimized for driving large capacitive loads and features modified input levels (VIH/VIL) for increased noise immunity and reduced input skew. The V320 functionality consists of bus transceiver circuits with 3-STATE, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to a high logic level. OE and direction pins are provided to control the transceiver function. In the transceiver mode, data present at the high impedance port may be stored in either the A or B register or in both. The select controls can multiplex stored and real time (transparent mode) data. The direction control determines which bus will receive data when the enable control OE is active LOW. In the isolation mode (OE HIGH) A data may be stored in the B register and/or B data may be stored in the A register. ■ Independent registers for A and B buses ■ Multiplexed real-time and stored data ■ Guaranteed output skew ■ Guaranteed MOS (Multiple Output Switching) Specifications ■ Output switching specified for both 50 pF and 250 pF, and 500 pF loads ■ Guaranteed simultaneous switching noise level (VOLP/ VOLV) and dynamic threshold performance (VIHD/VILD) ■ Glitch free power up/down high impedance for live insertion ■ BiCMOS technology for high drive and low power dissipation ■ −40°C to 85°C commercial temperature and VCC specifications ■ Modified specifications across VCC and temperature (VCC = 5.0V ±1%, T = 25°C ± 20°C) present more realistic system conditions ■ Available in TSSOP (MTC) Ordering Code: Order Number V320MTC Package Number MTC24 Package Description 24-Lead Thin Shrink Small Outline Package, JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names © 1998 Fairchild Semiconductor Corporation DS500149.prf Description D Direction A-to-B (High) B-to A (Low) OE Output Enable (Active LOW) CLKAB/SELAB A-to-B Clock/Select CLKBA/SELBA B-to-A Clock/Select A0–7 A Inputs/Outputs (TTL) B0–7 B Inputs/Outputs (TTL) www.fairchildsemi.com V320 8-Bit Registered Bus Transceiver April 1998 V320 Functional Table OE D SELAB SELBA CLKAB CLKBA H X X X H or L H or L H X X X LH X H X X X X LH L H L X X X A0–A7 B0–B7 Input Input Function Isolation CLK A Data into A CLK B Data into A Reg. A to B – Transparent L H L X LH X L H H X H or L X CLK A Data into A Reg. L H H X LH X CLK A Data into A Reg. and B output L L X L X X B to A – Transparent L L X L X LH L L X H X H or L L L X H X LH Input Output A Reg. to B (Storage) CLK B Data into B Reg. Output Input B Reg. to A (Storage) CLK B Data into B Reg.and A output L = Low H = High LH = Low to High transition X = Don’t Care Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Recommended Operating Conditions −0.5V to +7.0V DC Input Voltage (VI) DC Output Voltage (VO) Outputs Active (Note 2) Supply Voltage VCC −0.5V to +7.0V Outputs 3-STATE Operating VCC −0.5V to VCC +0.5V DC Output Sink Current into A-port/B-port IOL 4.5V to 5.5V Minimum Input Edge Rate Data Input 64 mA DC Output Source Current from A-port/B-port IOH 50 mV/ns Enable 20 mV/ns Clock −32 mA 100 mV/ns −40°C to +85°C Operating Temperature (TA) DC Input Diode Current (IIK) VI < 0 V V320 Absolute Maximum Ratings(Note 1) Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. −30 mA to +5.0 mA > 2000V ESD Rating typical Storage temperature (TSTG) Note 2: Either voltage limit or current limit is sufficient to protect inputs. −65° C to +15°C Max IOL (Current Applied to a LOW Output) 2 X IOL Spec. DC Electrical Characteristics (4.5V < VCC ≤ 5.5V) Over Recommended Operating Free-Air Temperature Range (Unless Otherwise Noted) VCC Symbol Parameter Min Typ (V) VIH VIL VOH B-Port/A-Port HIGH Level Input Voltage B-Port/A-Port LOW Level Input Voltage B-Port/A-Port HIGH Level Output Voltage 4.5–5.5 2.0 4.95–5.05 1.8 (Note 3) Max 4.5–5.5 0.8 4.95–5.05 1.2 (Note 3) 4.5 2.5 4.5 2.0 Units Conditions V Recognized HIGH Signal V Recognized LOW Signal V −3 mA −32 mA IOH B-Port/A-Port High Level Output Current Drive 4.5 −32 mA VOL B-Port/A-Port LOW Level Output Voltage 4.5 0.55 V IOL B-Port/A-Port Low Level Output Current Drive (Sink) 4.5 64 mA VOL = 0.55V IOS B-Port/A-Port Short Circuit Current 5.5 −100 −275 mA VOUT = 0.0V IOFF A-Port and Control Pins 0.0 100uA uA VOUT = 5.5V, All Others GND ICCH B-Port/A-Port Quiescent Power Supply Current 5.5 250 uA All Outputs HIGH ICCI B-Port/A-Port B-Port/A-Port 5.5 30 mA All Outputs LOW ICCZ B-Port/A-Port 3-STATE Power Supply Current 5.5 50 uA All Outputs 3-STATE Power-OFF Leakage Current VOH = 2.0V 64 mA Note 3: Extended Characteristics (4.95 > VCC > 5.05, T = 25°C ± 20°C) 3 www.fairchildsemi.com V320 Capacitance and Dynamic Switching Characteristics Over Recommended Operating Free-Air Temperature Range (Unless Otherwise Noted) Symbol Parameter Min Typ Max Units Conditions TA = 25°C CIN Input Capacitance (Control Pin) 5 pF VCC = 5.0V VI = VCC or 0 CI/O Output Capacitance (A and B ports) 11 pF VCC = 5.0V VI = VCC or 0 Output Switching Noise (Ground Bounce) VOLP Quiet Output Dynamic Peak VOL V VCC = 5.0V, T= 25°C VOLV Quiet Output Dynamic Valley VOL −1.2 V CL = 50 pF VOHV Quiet Output Dynamic Valley VOH 2.5 V 0.8 Input Noise Immunity (Dynamic Threshold) VIHD High Level Threshold Movement VILD Low Level Threshold Movement 2.2 0.5 V VCC = 5.0V, T= 25°C V CL = 50 pF AC Operating Requirements Over recommended ranges of supply voltage and operating free-air temperature Symbol fCLOCK Max Clock Frequency tWIDTH Pulse Duration tSU tHOLD Min Typ Max Units 200 (Note 4) MHz HIGH or LOW 3.0 ns Setup Time Bus to CLKAB/CLKBA 1.5 ns Hold Time Bus to CLKAB/CLKBA 1.0 ns Note 4: CL = 50 pF www.fairchildsemi.com 4 V320 AC Electrical Characteristics (−40°C to 85°C, VCC = 4.5V to 5.5V) 1 Output Switching From (Input) Symbol To (Output) Mode Min Typ Max Units Output Load: CL = 50 pF, RL= 500Ω, 1 Output Switching tPLH, tPHL CLKAB/CLKBA Register Bus A or B 1.7 5.6 ns tPLH, tPHL Bus A or B Transparent Bus A or B 1.5 4.8 ns tPLH, tPHL SELAB/SELBA Select Bus Bus A or B 1.5 5.9 ns tPLZ, tPHZ OE Output Disable Bus A or B 1.5 6.0 ns tPZH, tPZL OE Output Enable Bus A or B 1.5 6.3 ns tPLZ, tPHZ Direction (D) Dir. Disable Bus A or B 1.5 6.0 ns tPZH, tPZL Direction (D) Dir. Enable Bus A or B 1.5 6.3 ns tRISE Transition Time, Outputs (1V to 2V) 0.3 1.2 ns tFALL Transition Time, Outputs (1V to 2V) 0.3 1.4 ns Output Load: CL = 250 pF, RL = 500Ω, 1 Output Switching tPLH, tPHL CLKAB/CLKBA Register Bus A or B 2.0 7.5 ns tPLH, tPHL Bus A or B Transparent Bus A or B 2.0 7.0 ns tPLH, tPHL SELAB/SELBA Select Bus Bus A or B 2.0 7.5 ns tPLZ, tPHZ OE Output Disable Bus A or B (Note 5) (Note 5) ns tPZH, tPZL OE Output Enable Bus A or B 2.0 8.0 ns ns tPLZ, tPHZ Direction (D) Dir. Disable Bus A or B (Note 5) (Note 5) tPZH, tPZL Direction (D) Dir. Enable Bus A or B 2.0 8.3 ns tRISE Transition Time, Outputs (1V to 2V) 1.7 3.9 ns tFALL Transition Time, Outputs (1V to 2V) 0.8 3.1 ns Output Load: CL = 500 pF, RL = 500Ω, Output Switching tPLHtPHL CLKAB/CLKBA Register Bus A or B 3.0 12.2 ns tPLHtPHL Bus A or B Transparent Bus A or B 3.0 11.6 ns tPLHtPHL SELAB/SELBA Select Bus Bus A or B 3.0 12.4 ns tPLZ, tPHZ OE Output Disable Bus A or B (Note 5) (Note 5) ns tPZH, tPZL OE Output Enable Bus A or B 3.0 12.6 ns tPLZ, tPHZ Direction (D) Dir. Disable Bus A or B (Note 5) (Note 5) ns tPZH, tPZL Direction (D) Dir. Enable Bus A or B 6.3 13.2 ns tRISE Transition Time, Outputs (1V to 2V) 3.5 7.2 ns tFALL Transition Time, Outputs (1V to 2V) 1.4 5.1 ns Note 5: 3-STATE delays are dominated by the RC Network (500 Ω/ 250 pF, or 500 Ω/ 500 pF) on the output and thus have been excluded from this datasheet. 5 www.fairchildsemi.com V320 AC Electrical Characteristics (−40°C to 85°C, VCC = 4.5V to 5.5V) 8 Output Switching From (Input) Symbol To (Output) Mode Min Typ Max Units Output Load: CL = 50 pF, RL = 500Ω, 8 Outputs Switching tPLH, tPHL CLKAB/CLKBA Register Bus A or B 1.5 6.6 ns tPLH, tPHL Bus A or B Transparent Bus A or B 1.5 6.3 ns tPLH, tPHL SELAB/SELBA Select Bus Bus A or B 1.5 6.6 ns tPLZ, tPHZ OE Output Disable Bus A or B 1.5 6.6 ns tPZH, tPZL OE Output Enable Bus A or B 1.5 6.6 ns tPLZ, tPHZ Direction (D) Dir. Disable Bus A or B 1.5 6.6 ns tPZH, tPZL Direction (D) Dir. Enable Bus A or B 1.5 7.6 ns tOSHL Output to Output Skew (Note 6) 1.3 ns tOSHL Output to Output Skew (Note 6) 1.1 ns tRISE Transition Time, Outputs (1V to 2V) 0.5 1.5 ns tFALL Transition Time, Outputs (1V to 2V) 0.4 1.9 ns Output Load: CL = 250 pF, RL = 500Ω, 8 Outputs Switching tPLH, tPHL CLKAB/CLKBA Register Bus A or B 2.5 11.2 ns tPLH, tPHL Bus A or B Transparent Bus A or B 2.5 9.5 ns tPLH, tPHL SELAB/SELBA Select Bus Bus A or B 2.5 11.2 ns tPLZ, tPHZ OE Output Disable Bus A or B (Note 8) (Note 8) ns tPZH, tPZL OE Output Enable Bus A or B 2.5 11.5 ns tPLZ, tPHZ Direction (D) Dir. Disable Bus A or B (Note 8) (Note 8) ns tPZH, tPZL Direction (D) Dir. Enable Bus A or B 2.5 13.5 ns tOSHL Output to Output Skew (Note 8) 2.5 ns tOSLH Output to Output Skew (Note 8) 2.0 ns tRISE Transition Time, Outputs (1V to 2V) 2.0 5.5 ns tFALL Transition Time, Outputs (1V to 2V) 1.4 4.4 ns Output Load: CL = 500 pF, RL = 500Ω, 8 Outputs Switching tPLH, tPHL CLKAB/CLKBA Register Bus A or B 3.5 17.0 ns tPLH, tPHL Bus A or B Transparent Bus A or B 3.5 15.9 ns tPLH, tPHL SELAB/SELBA Select Bus Bus A or B 3.5 17.0 ns tPLZ, tPHZ OE Output Disable Bus A or B (Note 8) (Note 8) ns tPZH, tPZL OE Output Enable Bus A or B 3.5 18.5 ns tPLZ, tPHZ Direction (D) Dir. Disable Bus A or B (Note 8) (Note 8) ns tPZH, tPZL Direction (D) Dir. Enable Bus A or B 3.5 22.3 ns tOSHL Output to Output Skew (Note 6) 3.9 ns tOSLH Output to Output Skew (Note 6) 3.1 ns tRISE Transition Time, Outputs (1V to 2V) 4.4 7.8 ns tFALL Transition Time, Outputs (1V to 2V) 2.5 6.6 ns Note 6: Skew is defined as the absolute value of the difference between the actual propagation delays for any two outputs of the same device. The specification applies to outputs switching in the same direction also. Note 7: Device to Device Skew is defined as the absolute value of the difference between the actual propagation delays for any two outputs from any two devices. Note 8: 3-STATE delays are dominated by the RC Network (500 Ω/ 250 pF, or 500 Ω/ 500 pF) on the output and thus have been excluded from this datasheet. www.fairchildsemi.com 6 V320 Extended AC Electrical Characteristics (5°C to 45°C, VCC = 4.95V to 5.05V), 1 Output Switching From (Input) Symbol To (Output) Mode Min Typ Max Units ns Output Load: CL = 50 pF, RL = 500Ω, 1 Output Switching tPLH, tPHL CLKAB/CLKBA Register Bus A or B 1.5 5.2 tPLH, tPHL Bus A or B Transparent Bus A or B 1.5 4.3 ns tPLH, tPHL SELAB/SELBA Select Bus Bus A or B 2.0 4.8 ns tPLZ, tPHZ OE Output Disable Bus A or B 1.5 6.0 ns tPZH, tPZL OE Output Enable Bus A or B 2.2 5.0 ns tPLZ, tPHZ Direction (D) Dir. Disable Bus A or B 1.5 6.0 ns tPZH, tPZL Direction (D) Dir. Enable Bus A or B 2.2 5.2 ns tPV Device to Device Skew (Note 10) 2.0 ns tRISE Transition Time, Outputs (1V to 2V) 3.0 1.2 ns tFALL Transition Time, Outputs (1V to 2V) 0.4 1.2 ns ns Output Load: CL = 250 pF, RL = 500Ω, 1 Output Switching tPLH, tPHL CLKAB/CLKBA Register Bus A or B 2.5 7.4 tPLH, tPHL Bus A or B Transparent Bus A or B 2.5 6.7 ns tPLH, tPHL SELAB/SELBA Select Bus 3.0 7.2 ns tPLZ, tPHZ OE Output Disable Bus A or B (Note 9) (Note 9) ns tPZH, tPZL OE Output Enable Bus A or B 3.2 7.2 ns tPLZ, tPHZ Direction (D) Dir. Disable Bus A or B (Note 9) (Note 9) ns tPZH, tPZL Direction (D) Dir. Enable Bus A or B 3.2 8.1 ns tPV Device to Device Skew (Note 10) 2.5 ns tRISE Transition Time, Outputs (1V to 2V) 2.1 3.5 ns tFALL Transition Time, Outputs (1V to 2V) 1.0 2.5 ns Bus A or B Output Load: CL = 500 pF, RL = 500Ω, 1 Output Switching tPLH, tPHL CLKAB/CLKBA Register Bus A or B 3.5 10.6 ns tPLH, tPHL Bus A or B Transparent Bus A or B 3.5 10.0 ns tPLH, tPHL SELAB/SELBA Select Bus Bus A or B 4.0 10.6 ns tPLZ, tPHZ OE Output Disable Bus A or B (Note 9) (Note 9) ns tPZH, tPZL OE Output Enable Bus A or B 4.2 10.5 ns tPLZ, tPHZ Direction (D) Dir. Disable Bus A or B (Note 9) (Note 9) ns tPZH, tPZL Direction (D) Dir. Enable Bus A or B 4.2 11.3 ns tPV Device to Device Skew 5.0 ns tRISE Transition Time, Outputs (1V to 2V) 3.8 6.4 ns tFALL Transition Time, Outputs (1V to 2V) 1.7 3.8 ns Note 9: 3-STATE delays are dominated by the RC Network (500 Ω/ 250 pF, or 500 Ω/ 500 pF) on the output and thus have been excluded from this datasheet. Note 10: Device to Device Skew is defined as the absolute value of the difference between the actual propagation delays for any two outputs from any two devices. 7 www.fairchildsemi.com V320 Extended AC Electrical Characteristics (5°C to 45°C, VCC = 4.95V to 5.05V), 8 Outputs Switching From (Input) Symbol To (Output) Mode Min Typ Max Units Output Load: CL = 50 pF, RL = 500Ω, 8 Outputs Switching tPLH, tPHL CLKAB/CLKBA Register Bus A or B 2.5 6.2 ns tPLH, tPHL Bus A or B Transparent Bus A or B 2.5 5.4 ns tPLH, tPHL SELAB/SELBA Select Bus Bus A or B 2.5 5.7 ns tPLZ, tPHZ OE Output Disable Bus A or B 1.5 6.0 ns tPZH, tPZL OE Output Enable Bus A or B 2.5 5.7 ns tPLZ, tPHZ Direction (D) Dir. Disable Bus A or B 1.5 6.0 ns tPZH, tPZL Direction (D) Dir. Enable Bus A or B 2.5 7.2 ns tOSHL Output to Output Skew (Note 12) 1.1 ns tOSLH Output to Output Skew (Note 12) 0.9 ns tPV Device to Device Skew (Note 13) 2.5 ns tRISE Transition Time, Outputs (1V to 2V) 0.5 1.3 ns tFALL Transition Time, Outputs (1V to 2V) 0.6 1.4 ns Output Load: CL = 250 pF, RL = 500Ω, 8 Outputs Switching tPLH, tPHL CLKAB/CLKBA Register Bus A or B 3.5 10.5 ns tPLH, tPHL Bus A or B Transparent Bus A or B 3.5 10.5 ns tPLH, tPHL SELAB/SELBA Select Bus Bus A or B 3.5 10.5 ns tPLZ, tPHZ OE Output Disable Bus A or B (Note 11) (Note 11) ns tPZH, tPZL OE Output Enable Bus A or B 3.5 10.5 ns tPLZ, tPHZ Direction (D) Dir. Disable Bus A or B (Note 11) (Note 11) ns tPZH, tPZL Direction (D) Dir. Enable Bus A or B 3.5 14.8 ns tOSHL Output to Output Skew (Note 12) 2.3 ns tOSLH Output to Output Skew (Note 12) 1.9 ns tPV Device to Device Skew(Note 13) 4.0 ns tRISE Transition Time, Outputs (1V to 2V) 2.7 4.7 ns tFALL Transition Time, Outputs (1V to 2V) 1.8 3.7 ns Output Load: CL = 500 pF, RL = 500Ω, 8 Outputs Switching tPLH, tPHL CLKAB/CLKBA Register Bus A or B 5.0 15.3 ns tPLH, tPHL Bus A or B Transparent Bus A or B 5.0 13.6 ns tPLH, tPHL SELAB/SELBA Select Bus Bus A or B 5.0 15.3 ns tPLZ, tPHZ OE Output Disable Bus A or B (Note 11) (Note 11) ns tPZH, tPZL OE Output Enable Bus A or B 5.0 15.1 ns tPLZ, tPHZ Direction (D) Dir. Disable Bus A or B (Note 11) (Note 11) ns tPZH, tPZL Direction (D) Dir. Enable Bus A or B 5.0 19.4 ns tOSHL Output to Output Skew (Note 12) 3.5 ns tOSLH Output to Output Skew (Note 12) 2.9 ns tPV Device to Device Skew 5.0 ns tRISE Transition Time, Outputs (1V to 2V) 4.6 7.0 ns tFALL Transition Time, Outputs (1V to 2V) 2.9 4.9 ns Note 11: 3-STATE delays are dominated by the RC Network (500 Ω/ 250 pF, or 500 Ω/ 500 pF) on the output and thus have been excluded from this datasheet. Note 12: Skew is defined as the absolute value of the difference between the actual propagation delays for any two outputs of the same device. The specification applies to outputs switching in the same direction also. Note 13: Device to Device Skew is defined as the absolute value of the difference between the actual propagation delays for any two outputs from any two devices. www.fairchildsemi.com 8 V320 AC Loading and Waveforms *Includes jig and probe capacitance FIGURE 4. Propagation Delay, Pulse Width Waveforms FIGURE 1. Standard AC Test Load FIGURE 2. Test Input Signal Levels Input Pulse Requirements FIGURE 5. 3-STATE Output HIGH and LOW Enable and Disable Times Test Input Signal Requirements Amplitude Rep. Rate tW tr tf 3.0V 1 MHz 500 ns 2.5 ns 2.5 ns FIGURE 3. Propagation Delay Waveforms for Inverting and Non-Inverting Functions FIGURE 6. Setup Time, Hold Time and Recovery Time Waveforms 9 www.fairchildsemi.com V320 8-Bit Registered Bus Transceiver Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Thin Shrink Small Outline Package, JEDEC MO-153, 4.4mm Wide Package Number MTC24 LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.