Revised August 2000 100328 Low Power Octal ECL/TTL Bi-Directional Translator with Latch General Description Features The 100328 is an octal latched bi-directional translator designed to convert TTL logic levels to 100K ECL logic levels and vice versa. The direction of this translation is determined by the DIR input. A LOW on the output enable input (OE) holds the ECL outputs in a cut-off state and the TTL outputs at a high impedance level. A HIGH on the latch enable input (LE) latches the data at both inputs even though only one output is enabled at the time. A LOW on LE makes the 100328 transparent. ■ Identical performance to the 100128 at 50% of the supply current The cut-off state is designed to be more negative than a normal ECL LOW level. This allows the output emitter-followers to turn off when the termination supply is −2.0V, presenting a high impedance to the data bus. This high impedance reduces termination power and prevents loss of low state noise margin when several loads share the bus. ■ Available to industrial grade temperature range ■ Bi-directional translation ■ 2000V ESD protection ■ Latched outputs ■ FAST TTL outputs ■ 3-STATE outputs ■ Voltage compensated operating range = −4.2V to −5.7V The 100328 is designed with FAST TTL output buffers, featuring optimal DC drive and capable of quickly charging and discharging highly capacitive loads. All inputs have 50 kΩ pull-down resistors. Ordering Code: Order Number Package Number Package Description 100328SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 100328PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 100328QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 100328QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Industrial Temperature Range (−40°C to +85°C) Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Pin Descriptions Pin Names E0–E7 Description ECL Data I/O T0–T7 TTL Data I/O OE Output Enable Input LE Latch Enable Input DIR Direction Control Input All pins function at 100K ECL levels except for T0–T7. FAST is a registered trademark of Fairchild Semiconductor Corporation. © 2000 Fairchild Semiconductor Corporation DS010219 www.fairchildsemi.com 100328 Low Power Octal ECL/TTL Bi-Directional Translator with Latch April 1989 100328 Connection Diagrams Functional Diagram 24-Pin DIP/SOIC 28-Pin PLCC Truth Table OE DIR LE L X L ECL TTL Port Port LOW Z Notes (Cut-Off) L L H Input Z L H H LOW Input (Cut-Off) (Note 1)(Note 3) Note: LE, DIR, and OE use ECL logic levels (Note 2)(Note 3) Detail H L L L L (Note 1)(Note 4) H L L H H (Note 1)(Note 4) H L H X H H L L L H H L H H (Note 2)(Note 4) H H H Latched X (Note 2)(Note 4) Latched (Note 1)(Note 3) (Note 2)(Note 4) H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High Impedance Note 1: ECL input to TTL output mode. Note 2: TTL input to ECL output mode. Note 3: Retains data present before LE set HIGH. Note 4: Latch is transparent. www.fairchildsemi.com 2 Storage Temperature (TSTG) Recommended Operating Conditions −65°C to +150 °C Maximum Junction Temperature (TJ) +150°C VEE Pin Potential to Ground Pin −7.0V to +0.5V VTTL Pin Potential to Ground Pin −0.5V to +6.0V Case Temperature (TC) −50 mA TTL Input Voltage (Note 6) −0.5V to +6.0V TTL Input Current (Note 6) −30 mA to +5.0 mA Voltage Applied to Output −0.5V to +5.5V Current Applied to TTL Output in LOW State (Max) twice the rated IOL (mA) −5.7V to −4.2V TTL Supply Voltage (VTTL) +4.5V to +5.5V Note 6: Either voltage limit or current limit is sufficient to protect inputs. ≥2000V ESD (Note 7) ECL Supply Voltage (VEE) Note 5: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation. in HIGH State 3-STATE Output −40°C to +85°C Industrial ECL Output Current (DC Output HIGH) 0°C to +85°C Commercial VEE to +0.5V ECL Input Voltage (DC) 100328 Absolute Maximum Ratings(Note 5) Note 7: ESD testing conforms to MIL-STD-883, Method 3015. Commercial Version TTL-to-ECL DC Electrical Characteristics (Note 8) VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = 0°C to +85°C, VTTL = +4.5V to +5.5V Min Typ Max Units VOH Symbol Output HIGH Voltage Parameter −1025 −955 −870 mV VIN = VIH(Max) or VIL(Min) VOL Output LOW Voltage −1830 −1705 −1620 mV Loading with 50Ω to − 2V −2000 −1950 mV Cutoff Voltage Conditions OE or DIR LOW, VIN = VIH(Max) or VIL(Min), Loading with 50Ω to −2V VOHC Output HIGH Voltage Corner Point HIGH VOLC −1035 mV Output LOW Voltage VIN = VIH(Min) or VIL(Max) Loading with 50Ω to −2V −1610 mV VIH Input HIGH Voltage 2.0 5.0 V VIL Input LOW Voltage 0 0.8 V Over VTTL, VEE, TC Range IIH Input HIGH Current 70 µA VIN = +2.7V 1.0 Corner Point LOW Over VTTL, VEE, TC Range mA VIN = +5.5V IIL Input LOW Current −700 µA VIN = +0.5V VFCD Input Clamp Diode Voltage −1.2 V IEE VEE Supply Current Breakdown Test IIN = −18 mA LE LOW, OE and DIR HIGH Inputs OPEN −159 −75 −169 −75 mA VEE = −4.2V to −4.8V VEE = −4.2V to −5.7V Note 8: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. 3 www.fairchildsemi.com 100328 Commercial Version (Continued) ECL-to-TTL DC Electrical Characteristics (Note 9) VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = 0°C to +85°C, CL = 50 pF, VTTL = +4.5V to +5.5V Symbol VOH Parameter Output HIGH Voltage VOL Output LOW Voltage VIH Input HIGH Voltage Min Typ 2.7 3.1 2.4 2.9 0.3 Max Units V Conditions IOH = −3 mA, VTTL = 4.75V IOH = −3 mA, VTTL = 4.50V IOL = 24 mA, VTTL = 4.50V 0.5 V −1165 −870 mV Guaranteed HIGH Signal for All Inputs −1830 −1475 mV Guaranteed LOW Signal for All Inputs 350 µA VIN = VIH (Max) µA VIN = VIL (Min) µA VOUT = +2.7V µA VOUT = +0.5V VIL Input LOW Voltage IIH Input HIGH Current IIL Input LOW Current IOZHT 3-STATE Current Output HIGH IOZLT 3-STATE Current Output LOW −700 IOS Output Short-Circuit Current −150 ITTL VTTL Supply Current 0.50 70 −60 mA VOUT = 0.0V, VTTL = +5.5V 74 mA TTL Outputs LOW 49 mA TTL Outputs HIGH 67 mA TTL Outputs in 3-STATE DIP TTL-to-ECL AC Electrical Characteristics (Note 9) VEE = −4.2V to −5.7V, VTTL = +4.5V to +5.5V, VCC = VCCA = GND TC = 0°C TC = 25°C Symbol Parameter Min Max Min Max tPLH TN to En tPHL (Transparent) tPLH LE to En tPHL tPZH OE to En (Cutoff to HIGH) tPHZ OE to En (HIGH to Cutoff) tPHZ DIR to En (HIGH to Cutoff) TC = 85°C Min Max Units Conditions 1.1 3.5 1.1 3.6 1.1 3.8 ns Figures 1, 2 1.7 3.6 1.7 3.7 1.9 3.9 ns Figures 1, 2 1.3 4.2 1.5 4.4 1.7 4.8 ns Figures 1, 2 1.5 4.5 1.6 4.5 1.6 4.6 ns Figures 1, 2 1.6 4.3 1.6 4.3 1.7 4.5 ns Figures 1, 2 tSET Tn to LE 1.1 1.1 1.1 ns Figures 1, 2 tHOLD Tn to LE 1.1 1.1 1.1 ns Figures 1, 2 tPW(H) Pulse Width LE 2.1 2.1 2.1 ns Figures 1, 2 tTLH Transition Time tTHL 20% to 80%, 80% to 20% ns Figures 1, 2 0.6 1.6 0.6 1.6 0.6 1.6 Note 9: The specified limits represent the “worst” case value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. www.fairchildsemi.com 4 100328 Commercial Version (Continued) DIP ECL-to-TTL AC Electrical Characteristics VEE = −4.2V to −5.7V, VTTL = +4.5V to +5.5V, VCC = VCCA = GND, CL = 50 pF TC = 0°C TC = 25°C Symbol Parameter Min Max Min Max tPLH En to Tn tPHL (Transparent) tPLH LE to Tn TC = 85°C Min Max Units Conditions 2.3 5.6 2.4 5.6 2.6 5.9 ns Figures 3, 4 3.1 7.2 3.1 7.2 3.3 7.7 ns Figures 3, 4 ns Figures 3, 5 ns Figures 3, 5 ns Figures 3, 6 tPHL tPZH OE to Tn 3.4 8.45 3.7 8.95 4.0 9.7 tPZL (Enable Time) 3.8 9.2 4.0 9.2 4.3 9.95 tPHZ OE to Tn 3.2 8.95 3.3 8.95 3.5 9.2 tPLZ (Disable Time) 3.0 7.7 3.4 8.7 4.1 9.95 tPHZ DIR to Tn 2.7 8.2 2.8 8.7 3.1 8.95 tPLZ (Disable Time) 2.8 7.45 3.1 7.95 4.0 9.2 tSET En to LE 1.1 1.1 1.1 ns Figures 3, 6 tHOLD En to LE 2.1 2.1 2.6 ns Figures 3, 4 tPW(H) Pulse Width LE 4.1 4.1 4.1 ns Figures 3, 7 SOIC and PLCC TTL-to-ECL AC Electrical Characteristics VEE = −4.2V to −5.7V, VTTL = +4.5V to +5.5V Symbol Parameter TC = 0°C TC = 25°C TC = 85°C Units Conditions Min Max Min Max Min Max 1.1 3.3 1.1 3.4 1.1 3.6 ns Figures 1, 2 tPLH Tn to En tPHL (Transparent) tPLH LE to En 1.7 3.4 1.7 3.5 1.9 3.7 ns Figures 1, 2 OE to En 1.3 4.0 1.5 4.2 1.7 4.6 ns Figures 1, 2 1.5 4.3 1.6 4.3 1.6 4.4 ns Figures 1, 2 1.6 4.1 1.6 4.1 1.7 4.3 ns Figures 1, 2 tPHL tPZH (Cutoff to HIGH) tPHZ OE to En (HIGH to Cutoff) tPHZ DIR to En (HIGH to Cutoff) tSET Tn to LE 1.0 1.0 1.0 ns Figures 1, 2 tHOLD Tn to LE 1.0 1.0 1.0 ns Figures 1, 2 tPW(H) Pulse Width LE 2.0 2.0 2.0 ns Figures 1, 2 tTLH Transition Time 0.6 1.6 ns Figures 1, 2 tTHL 20% to 80%, 80% to 20% tOSHL Maximum Skew Common Edge Output-to-Output Variation 1.6 0.6 1.6 0.6 PLCC Only 200 200 200 ps 200 200 200 ps 650 650 650 ps 650 650 650 ps (Note 10) Data to Output Path tOSLH Maximum Skew Common Edge Output-to-Output Variation PLCC Only (Note 10) Data to Output Path tOST Maximum Skew Opposite Edge Output-to-Output Variation PLCC Only (Note 10) Data to Output Path tPS Maximum Skew Pin (Signal) Transition Variation PLCC Only (Note 10) Data to Output Path Note 10: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL), or LOW-to-HIGH (tOSLH), or in opposite directions both HL and LH (tOST). Parameters tOST and tps guaranteed by design. 5 www.fairchildsemi.com 100328 Commercial Version (Continued) SOIC and PLCC ECL-to-TTL AC Electrical Characteristics VEE = −4.2V to −5.7V, VTTL = +4.5V to +5.5V, CL = 50 pF TC = 0°C Symbol Parameter Min Max tPLH En to Tn tPHL (Transparent) tPLH LE to Tn TC = 25°C TC = 85°C Min Max Min Max Units Conditions 2.3 5.4 2.4 5.4 2.6 5.7 ns Figures 3, 4 3.1 7.0 3.1 7.0 3.3 7.5 ns Figures 3, 4 ns Figures 3, 5 ns Figures 3, 5 ns Figures 3, 6 Figures 3, 4 tPHL tPZH OE to Tn 3.4 8.25 3.7 8.75 4.0 9.5 tPZL (Enable Time) 3.8 9.0 4.0 9.0 4.3 9.75 tPHZ OE to Tn 3.2 8.75 3.3 8.75 3.5 9.0 tPLZ (Disable Time) 3.0 7.5 3.4 8.5 4.1 9.75 tPHZ DIR to Tn 2.7 8.0 2.8 8.5 3.1 8.75 tPLZ (Disable Time) 2.8 7.25 3.1 7.75 4.0 9.0 tSET En to LE 1.0 1.0 1.0 ns tHOLD En to LE 2.0 2.0 2.5 ns Figures 3, 4 tPW(H) Pulse Width LE 4.0 4.0 4.0 ns Figures 3, 4 tOSHL Maximum Skew Common Edge Output-to-Output Variation PLCC Only 600 600 600 ps 850 850 850 ps 1350 1350 1350 ps 950 950 950 ps (Note 11) Data to Output Path tOSLH Maximum Skew Common Edge Output-to-Output Variation PLCC Only (Note 11) Data to Output Path tOST Maximum Skew Opposite Edge Output-to-Output Variation PLCC Only (Note 11) Data to Output Path tPS Maximum Skew Pin (Signal) Transition Variation PLCC Only (Note 11) Data to Output Path Note 11: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL), or LOW-to-HIGH (tOSLH), or in opposite directions both HL and LH (tOST). Parameters tOST and tPS guaranteed by design. www.fairchildsemi.com 6 100328 Industrial Version PLCC TTL-to-ECL DC Electrical Characteristics (Note 12) VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = −40°C to +85°C, VTTL = +4.5V to +5.5V TC = −40°C TC = 0°C to +85°C Symbol Parameter Units Min Max Min Max Conditions VOH Output HIGH Voltage −1085 −870 −1025 −870 mV VIN = VIH(Max) or VIL(Min) VOL Output LOW Voltage −1830 −1575 −1830 −1620 mV Loading with 50Ω to −2V −1950 mV Cutoff Voltage OE or DIR LOW, −1900 VIN= VIH(Max) or VIL(Min), Loading with 50Ω to −2V VOHC Output HIGH Voltage Corner Point HIGH VOLC −1095 Output LOW Voltage −1035 −1565 Corner Point LOW mV −1610 mV VIN = VIH(Min) or VIL(Max) Loading with 50Ω to −2V VIH Input HIGH Voltage 2.0 5.0 2.0 5.0 V VIL Input LOW Voltage 0 0.8 0 0.8 V Over VTTL, VEE, TC Range IIH Input HIGH Current 70 µA VIN = +2.7V 1.0 mA VIN = +5.5V IIL Input LOW Current −700 −700 µA VIN = +0.5V VFCD Input Clamp Diode Voltage −1.2 −1.2 V IIN = −18 mA IEE VEE Supply Current 70 Breakdown Test 1.0 Over VTTL, VEE, TC Range LE LOW, OE and DIR HIGH Inputs OPEN −159 −70 −159 −75 −169 −70 −169 −75 mA VEE = −4.2V to −4.8V VEE = −4.2V to −5.7V PLCC ECL-to-TTL DC Electrical Characteristics (Note 12) VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = −40°C to +85°C, CL = 50 pF, VTTL = +4.5V to +5.5V TC = −40°C TC = 0°C to +85°C Symbol Parameter Units Min Max Min Max VOH Output HIGH Voltage 2.7 2.7 2.4 2.4 0.5 V Conditions IOH = −3 mA, VTTL = 4.75V IOH = −3 mA, VTTL = 4.50V IOL = 24 mA, VTTL = 4.50V VOL Output LOW Voltage 0.5 V VIH Input HIGH Voltage −1170 −870 −1165 −870 mV Guaranteed HIGH Signal for All Inputs VIL Input LOW Voltage −1830 −1480 −1830 −1475 mV Guaranteed LOW Signal for All Inputs 350 µA VIN = VIH (Max) µA VIN = VIH (Min) µA VOUT = +2.7V µA VOUT = +0.5V IIH Input HIGH Current IIH Input LOW Current 425 IOZHT 3-STATE Current Output HIGH IOZLT 3-STATE Current Output LOW −700 IOS Output Short-Circuit Current −150 ITTL VTTL Supply Current 0.50 0.50 70 70 −700 −60 −150 −60 74 74 49 49 67 67 mA VOUT = 0.0V, VTTL = +5.5V TTL Outputs LOW mA TTL Outputs HIGH TTL Outputs in 3-STATE Note 12: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. 7 www.fairchildsemi.com 100328 Industrial Version (Continued) PLCC TTL-to-ECL AC Electrical Characteristics VEE = −4.2V to −5.7V, VTTL = +4.5V to +5.5V Symbol Parameter tPLH Tn to En tPHL (Transparent) tPLH LE to En tPHL tPZH OE to En (Cutoff to HIGH) tPHZ OE to En (HIGH to Cutoff) tPHZ DIR to En (HIGH to Cutoff) TC = −40°C TC = 25°C TC = 85°C Units Conditions Min Max Min Max Min Max 1.0 3.3 1.1 3.4 1.1 3.6 1.7 3.4 1.7 3.5 1.9 3.7 ns Figures 1, 2 1.2 4.0 1.5 4.2 1.7 4.6 ns Figures 1, 2 1.5 4.5 1.6 4.3 1.6 4.4 ns Figures 1, 2 1.6 4.1 1.6 4.1 1.7 4.3 ns Figures 1, 2 ns Figures 1, 2 tSET Tn to LE 2.5 1.0 1.0 ns Figures 1, 2 tHOLD Tn to LE 1.0 1.0 1.0 ns Figures 1, 2 tPW(H) Pulse Width LE 2.5 2.0 2.0 ns Figures 1, 2 tTLH Transition Time tTHL 20% to 80%, 80% to 20% ns Figures 1, 2 0.4 2.3 0.6 1.6 0.6 1.6 PLCC ECL-to-TTL AC Electrical Characteristics VEE = −4.2V to −5.7V, VTTL = +4.5V to +5.5V, CL = 50 pF Symbol Parameter tPLH En to Tn tPHL (Transparent) tPLH LE to Tn TC = 0°C TC = 25°C TC = 85°C Units Conditions Min Max Min Max Min Max 2.3 5.4 2.4 5.4 2.6 5.7 ns Figures 3, 4 ns Figures 3, 4 ns Figures 3, 5 ns Figures 3, 5 3.1 7.4 3.1 7.0 3.3 7.5 tPZH OE to Tn 3.4 8.3 3.7 8.75 4.0 9.5 tPZL (Enable Time) 3.7 9.0 4.0 9.0 4.3 9.75 tPHZ OE to Tn 3.2 9.0 3.3 8.75 3.5 9.0 tPLZ (Disable Time) 3.0 7.5 3.4 8.5 4.1 9.75 tPHZ DIR to Tn 2.7 8.0 2.8 8.5 3.1 8.75 tPLZ (Disable Time) 2.8 7.3 3.1 7.75 4.0 9.0 ns Figures 3, 5 tSET En to LE 2.5 1.0 1.0 ns Figures 3, 4 tHOLD En to LE 2.3 2.0 2.5 ns Figures 3, 4 tPW(H) Pulse Width LE 4.0 4.0 4.0 ns Figures 3, 4 tPHL www.fairchildsemi.com 8 100328 Test Circuitry (TTL-to-ECL) Note: • Rt = 50Ω termination. When an input or output is being monitored by a scope, Rt is supplied by the scope's 50Ω resistance. When an input or output is not being monitored, an external 50Ω resistance must be applied to serve as Rt. • TTL and ECL force signals are brought to the DUT via 50Ω coax lines. • VTTL is decoupled to ground with 0.1 µF to ground, VEE is decoupled to ground with 0.01 µF and VCC is connected to ground. • For ECL input pins, the equivalent force/sense circuitry is optional. FIGURE 1. TTL-to-ECL AC Test Circuit Switching Waveforms (TTL-to-ECL) FIGURE 2. TTL to ECL Transition—Propagation Delay and Transition Times 9 www.fairchildsemi.com 100328 Test Circuitry (ECL-to-TTL) Note: • Rt = 50Ω termination. When an input or output is being monitored by a scope, Rt is supplied by the scope's 50Ω resistance. When an input or output is not being monitored, an external 50Ω resistance must be applied to serve as Rt. • The TTL 3-State pull up switch is connected to +7V only for ZL and LZ tests. • TTL and ECL force signals are brought to the DUT via 50Ω coax lines. • VTTL is decoupled to ground with 0.1 µF, VEE is decoupled to ground with 0.01 µF and VCC is connected to ground. FIGURE 3. ECL-to-TTL AC Test Circuit Switching Waveforms (ECL-to-TTL) Note: DIR is LOW, and OE is HIGH FIGURE 4. ECL-to-TTL Transition—Propagation Delay and Transition Times www.fairchildsemi.com 10 100328 Switching Waveforms (ECL-to-TTL) (Continued) Note: DIR is LOW, LE is HIGH FIGURE 5. ECL-to-TTL Transition, OE to TTL Output, Enable and Disable Times Note: OE is HIGH, LE is HIGH FIGURE 6. ECL-to-TTL Transition, DIR to TTL Output, Disable Time 11 www.fairchildsemi.com 100328 Applications FIGURE 7. Applications Diagram—MOS/TTL SRAM Interface Using 100328 ECL–TTL Latched Translator www.fairchildsemi.com 12 100328 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide Package Number N24E 13 www.fairchildsemi.com 100328 Low Power Octal ECL/TTL Bi-Directional Translator with Latch Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Package Number V28A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 14