Revised August 2000 100350 Low Power Hex D-Type Latch General Description Features The 100350 contains six D-type latches with true and complement outputs, a pair of common Enables (Ea and Eb), and a common Master Reset (MR). A Q output follows its D input when both Ea and Eb are LOW. When either Ea or Eb (or both) are HIGH, a latch stores the last valid data present on its D input before Ea or Eb went HIGH. The MR input overrides all other inputs and makes the Q outputs LOW. All inputs have 50 kΩ pull-down resistors. ■ 20% power reduction of the 100150 ■ 2000V ESD protection ■ Pin/function compatible with 100150 ■ Voltage compensated operating range = −4.2V to −5.7V Ordering Code: Order Number Package Number Package Description 100350PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 100350QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Devises also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagrams 24-Pin DIP Pin Descriptions 28-Pin PLCC Pin Names Description D0–D5 Data Inputs Ea , Eb Common Enable Inputs (Active LOW) MR Asynchronous Master Reset Input Q0–Q5 Data Outputs Q0–Q5 Complementary Data Outputs © 2000 Fairchild Semiconductor Corporation DS009884 www.fairchildsemi.com 100350 Low Power Hex D-Type Latch July 1988 100350 Truth Tables (Each Latch) Asynchronous Operation Latch Operation Inputs Outputs Dn Ea Eb MR Inputs Qn Dn Ea Eb MR Qn X X X H L L L L L L H L L L H X H X L Latched (Note 1) X X H L Latched (Note 1) H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Note 1: Retains data present before E positive transition Logic Diagram www.fairchildsemi.com Outputs 2 Recommended Operating Conditions Above which the useful life may be impaired. Storage Temperature (TSTG) −65°C to +150°C VEE to +0.5V Output Current (DC Output HIGH) −50 mA ESD (Note 3) ≥2000V −5.7V to −4.2V Supply Voltage (VEE) −7.0V to +0.5V VEE Pin Potential to Ground Pin Input Voltage (DC) 0°C to +85°C Case Temperature (TC) +150°C Maximum Junction Temperature (TJ) Note 2: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 3: ESD testing conforms to MIL-STD-883, Method 3015. DC Electrical Characteristics (Note 4) VEE = −4.5V to −5.7V, VCC = VCCA = GND, TC = 0°C to +85°C Min Typ Max VOH Symbol Output HIGH Voltage −1025 −955 −870 VOL Output LOW Voltage −1830 −1705 −1620 VOHC Output HIGH Voltage −1035 VOLC Output LOW Voltage VIH Input HIGH Voltage −1165 −870 mV Guaranteed HIGH Signal for All Inputs VIL Input LOW Voltage −1830 −1475 mV Guaranteed LOW Signal for All Inputs IIL Input LOW Current 0.50 µA VIN = VIL (Min) IIH Input HIGH Current µA VIN = VIH (Max) mA VEE = −4.2V to −4.8V IEE Parameter Units mV mV −1610 MR 240 Dn 240 Ea, Eb 240 Power Supply Conditions VIN =VIH (Max) Loading with or VIL (Min) 50Ω to −2.0V VIN = VIH (Min) Loading with or VIL (Max) 50Ω to −2.0V Inputs Open Current −89 −44 −93 −44 VEE = −4.2V to −5.7V Note 4: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. DIP AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol Parameter tPLH Propagation Delay tPHL Dn to Output TC = 0°C TC = +25°C TC = +85°C Min Max Min Max Min Max 0.50 1.40 0.50 1.40 0.50 1.50 Units ns (Transparent Mode) tPLH Propagation Delay tPHL Ea, Eb to Output tPLH Propagation Delay tPHL MR to Output tTLH Transition Time tTHL 20% to 80%, 80% to 20% tS Setup Time Conditions Figures 1, 2 0.75 1.85 0.75 1.85 0.75 2.05 ns 0.90 2.10 0.90 2.10 0.90 2.10 ns Figures 1, 3 0.35 1.30 0.35 1.30 0.35 1.30 ns Figures 1, 2 ns Figures 3, 4 D0–D5 1.00 1.00 1.00 MR (Release Time) 1.60 1.60 1.60 tH Hold Time, D0–D5 0.40 0.40 0.40 ns Figure 4 tPW(L) Pulse Width LOW 2.00 2.00 2.00 ns Figure 2 tPW(H) Pulse Width HIGH, MR 2.00 2.00 2.00 ns Figure 3 Ea, Eb 3 www.fairchildsemi.com 100350 Absolute Maximum Ratings(Note 2) 100350 PLCC AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol tPLH tPHL Parameter TC = 0°C TC = +25°C TC = +85°C Min Max Min Max Min Max 0.50 1.20 0.50 1.20 0.50 1.30 Units Conditions Propagation Delay Dn to Output ns (Transparent Mode) tPLH Propagation Delay tPHL Ea, Eb to Output tPLH Propagation Delay tPHL MR to Output tTLH Transition Time tTHL 20% to 80%, 80% to 20% tS Setup Time Figures 1, 2 0.75 1.65 0.75 1.65 0.75 1.85 ns 0.90 1.90 0.90 1.90 0.90 1.90 ns Figures 1, 3 0.35 1.10 0.35 1.10 0.35 1.10 ns Figures 1, 2 ns Figures 3, 4 D0–D5 0.90 0.90 0.90 MR (Release Time) 1.50 1.50 1.50 tH Hold Time, D0–D5 0.30 0.30 0.30 ns Figure 4 tPW(L) Pulse Width LOW 2.00 2.00 2.00 ns Figure 2 2.00 2.00 2.00 ns Figure 3 Ea, Eb tPW(H) Pulse Width HIGH, MR Test Circuit Note: • VCC, VCCA = +2V, VEE = −2.5V • L1 and L2 = equal length 50Ω impedance lines • RT = 50Ω terminator internal to scope • Decoupling 0.1 µF from GND to VCC and VEE • All unused outputs are loaded with 50Ω to GND • CL = Fixture and stray capacitance ≤ 3 pF FIGURE 1. AC Test Circuit www.fairchildsemi.com 4 100350 Switching Waveforms FIGURE 2. Enable Timing FIGURE 3. Reset Timing Notes: tS is the minimum time before the transition of the enable that information must be present at the data input. tH is the minimum time after the transition of the enable that information must remain unchanged at the data input. FIGURE 4. Data Setup and Hold Time 5 www.fairchildsemi.com 100350 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide Package Number N24E www.fairchildsemi.com 6 100350 Low Power Hex D-Type Latch Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Package Number V28A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 7 www.fairchildsemi.com