Revised August 2000 100301 Low Power Triple 5-Input OR/NOR Gate General Description Features The 100301 is a monolithic triple 5-input OR/NOR gate. All inputs have 50 kΩ pull-down resistors and all outputs are buffered. ■ 23% power reduction of the 100101 ■ 2000V ESD protection ■ Pin/function compatible with 100101 ■ Voltage compensated operating range = −4.2V to −5.7V ■ Available to industrial grade temperature range (PLCC package only) Ordering Code: Order Number Package Number Package Description 100301SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 100301PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 100301QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 100301QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Industrial Temperature Range (−40°C to +85°C) Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagrams 24-Pin DIP/SOIC 28-Pin PLCC Pin Descriptions Pin Names Description Dna, Dnb, Dnc Data Inputs Oa, Ob, Oc Data Outputs Oa, Ob, Oc Complementary Data Outputs © 2000 Fairchild Semiconductor Corporation DS010579 www.fairchildsemi.com 100301 Low Power Triple 5-Input OR/NOR Gate August 1989 100301 Truth Table Inputs Outputs D1a, D1b, D1c D2a, D2b, D2c D3a, D3b, D3c D4a, D4b, D4c D5a, D5b, D5c Oa, Ob, Oc Oa, Ob, Oc L L L L L L H L L L L H H L L L L H L H L L L L H H H L L L H L L H L L L H L H H L L L H H L H L L L H H H H L L H L L L H L L H L L H H L L H L H L H L L H L H H H L L H H L L H L L H H L H H L L H H H L H L L H H H H H L H L L L L H L H L L L H H L H L L H L H L H L L H H H L H L H L L H L H L H L H H L H L H H L H L H L H H H H L H H L L L H L H H L L H H L H H L H L H L H H L H H H L H H H L L H L H H H L H H L H H H H L H L H H H H H H L H = HIGH Voltage Level L = LOW Voltage Level www.fairchildsemi.com 2 Storage Temperature (TSTG) VEE Pin Potential to Ground Pin Recommended Operating Conditions −65°C to +150°C +150°C Maximum Junction Temperature (TJ) Case Temperature (TC) −7.0V to +0.5V Output Current (DC Output HIGH) −50 mA ESD (Note 2) ≥2000V 0°C to +85°C Commercial VEE to +0.5V Input Voltage (DC) 100301 Absolute Maximum Ratings(Note 1) −40°C to +85°C Industrial −5.7V to −4.2V Supply Voltage (VEE) Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “recommended Operating Conditions” table will define the conditions for actual device operation. Note 2: ESD testing conforms to MIL-STD-883, Method 3015. Commercial Version DC Electrical Characteristics (Note 3) VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = 0°C to +85°C Min Typ Max Units VOH Symbol Output HIGH Voltage Parameter −1025 −955 −870 mV VOL Output LOW Voltage −1830 −1705 −1620 mV VOHC Output HIGH Voltage −1035 VOLC Output LOW Voltage VIH Input HIGH Voltage VIL IIL IIH Input HIGH Current IEE Power Supply Current mV Conditions Loading with VIN = VIH(Max) or VIL(Min) 50Ω to −2.0V Loading with VIN = VIH(Min) or VIL(Max) −1610 mV −1165 −870 mV Guaranteed HIGH Signal for All Inputs Input LOW Voltage −1830 −1475 mV Guaranteed LOW Signal for All Inputs Input LOW Current 0.50 µA VIN = VIL(Min) −29 −17 240 µA VIN = VIH(Max) −15 mA Inputs OPEN 50Ω to −2.0V Note 3: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. DIP AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol Parameter tPLH Propagation Delay tPHL Data to Output tTLH Transition Time tTHL 20% to 80%, 80% to 20% TC = 0°C TC = +25°C TC = +85°C Units Min Max Min Max Min Max 0.50 1.10 0.50 1.15 0.50 1.20 ns 0.40 1.20 0.40 1.20 0.40 1.20 ns Conditions Figures 1, 2 (Note 4) Figures 1, 2 Note 4: The propagation delay specified is for single output switching. Delays may vary up to 100 ps with multiple outputs switching. 3 www.fairchildsemi.com 100301 Commercial Version (Continued) SOIC and PLCC AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol Parameter tPLH Propagation Delay tPHL Data to Output tTLH Transition Time tTHL 20% to 80%, 80% to 20% tOSHL Maximum Skew Common Edge TC = 0°C TC = +25°C TC = +85°C Units Min Max Min Max Min Max 0.50 1.00 0.50 1.05 0.50 1.10 ns 0.40 1.10 0.40 1.10 0.40 1.10 ns Conditions Figures 1, 2 (Note 5) Figures 1, 2 PLCC Only Output-to-Output Variation 240 240 240 ps 330 330 330 ps 330 330 330 ps 230 230 230 ps (Note 6) Data to Output Path tOSLH Maximum Skew Common Edge PLCC Only Output-to-Output Variation (Note 6) Data to Output Path tOST Maximum Skew Opposite Edge PLCC Only Output-to-Output Variation (Note 6) Data to Output Path tPS Maximum Skew PLCC Only Pin (Signal) Transition Variation (Note 6) Data to Output Path Note 5: The propagation delay specified is for single output switching. Delays may vary up to 100 ps with multiple outputs switching. Note 6: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL), or LOW-to-HIGH (tOSLH), or in opposite directions both HL and LH (tOST). Parameters tOST and tPS guaranteed by design. Industrial Version PLCC DC Electrical Characteristics (Note 7) VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = −40°C to +85°C Symbol Parameter TC = −40°C Min TC = 0°C to +85°C Max Min Units Conditions Max VOH Output HIGH Voltage −1085 −870 −1025 −870 mV VIN = VIH(Max) Loading with VOL Output LOW Voltage −1830 −1575 −1830 −1620 mV or VIL(Min) 50Ω to −2.0V VOHC Output HIGH Voltage −1095 mV VIN = VIH(Min) Loading with VOLC Output LOW Voltage −1610 mV or VIL(Max) 50Ω to −2.0V VIH Input HIGH Voltage −1170 −870 −1165 −870 mV Guaranteed HIGH Signal for All Inputs VIL Input LOW Voltage −1830 −1480 −1830 −1475 mV Guaranteed LOW Signal for All Inputs IIL Input LOW Current 0.50 µA VIN = VIL(Min) IIH Input HIGH Current IEE Power Supply Current −1035 −1565 0.50 240 −29 −15 −29 240 µA VIN = VIH(Max) −15 mA Inputs Open Note 7: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. PLCC AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol Parameter TC = −40°C Min tPLH Propagation Delay tPHL Data to Output tTLH Transition Time tTHL 20% to 80%, 80% to 20% TC = +25°C Max Min Max TC = +85°C Min Units 0.40 1.00 0.50 1.05 0.50 1.10 ns 0.30 1.10 0.40 1.10 0.40 1.10 ns Note 8: The propagation delay specified is for single output switching. Delays may vary up to 100 ps with multiple outputs switching. www.fairchildsemi.com 4 Conditions Max Figures 1, 2 (Note 8) Figures 1, 2 100301 Test Circuitry Notes: VCC, VCCA = +2V, VEE = −2.5V L1 and L2 = equal length 50Ω impedance lines RT = 50Ω terminator internal to scope Decoupling 0.1 µF from GND to VCC and VEE All unused outputs are loaded with 50Ω to GND CL = Fixture and stray capacitance ≤ 3 pF FIGURE 1. AC Test Circuit Switching Waveforms FIGURE 2. Propagation Delay and Transition Times 5 www.fairchildsemi.com 100301 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide Package Number N24E www.fairchildsemi.com 6 100301 Low Power Triple 5-Input OR/NOR Gate Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Package Number V28A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 7 www.fairchildsemi.com