FUJITSU SEMICONDUCTOR DATA SHEET DS04-21371-1E ASSP Fractional-N PLL Frequency Synthesizer MB15F83UL ■ DESCRIPTION The Fujitsu MB15F83UL is Fractional-N Phase Locked Loop (PLL) frequency synthesizer with fast lock up function. The Fractional-N PLL operating up to 2000 MHz and the integer PLL operating up to 600 MHz are integrated on one chip. The MB15F83UL is used, as charge pump which is well-balanced output current with 1.5 mA and 6 mA selectable by serial data, direct power save control and digital lock detector. In addition, the MB15F83UL adopts a new architecture to achieve fast lock. The new package (Thin Bump Chip Carrier20) decreases a mount area of MB15F83UL more than 30% comparing with the former B.C.C.16 (for dual PLL, MB15F03SL) . The MB15F83UL is ideally suited for wireless mobile communications, such as GSM. ■ FEATURES • High frequency operation : RF synthesizer : 2000 MHz Max. : IF synthesizer : 600 MHz Max. • Low power supply voltage : VCC = 2.7 V to 3.6 V • Ultra Low power supply current : ICC = 5.8 mA Typ. (VCC = Vp = 3.0 V, Ta = +25 °C, SW = 0 in IF and RF locking state) (Continued) ■ PACKAGES 20-pin, Plastic TSSOP 20-pad, Plastic BCC (FPT-20P-M06) (LCC-20P-M05) MB15F83UL (Continued) • Direct power saving function : Power supply current in power saving mode Typ. 0.1 µA (VCC = Vp = 3.0 V, Ta = +25 °C) , Max. 10 µA (VCC = Vp = 3.0 V) • Fractional function : modulo 13 fixed (implemented in RF-PLL) • Dual modulus prescaler : 2000 MHz prescaler (16/17 fixed) /600 MHz prescaler (8/9 or 16/17) • Serial input programmable reference divider : RF : 7 bit (3 to 127) /IF : 14 bit (3 to 16383) • Serial input programmable divider consisting of : RF section - Binary 4-bit swallow counter : 0 to 15 - Binary 10-bit programmable counter : 18 to 1,023 - Binary 4-bit fractional counter numerator : 0 to 15 IF section - Binary 4-bit swallow counter : 0 to 15 - Binary 11-bit programmable counter : 3 to 2,047 • On-chip phase comparator for fast lock and low noise • Operating temperature : Ta = −40 °C to +85 °C • Small package Bump Chip Carrier.0 (3.4 mm × 3.6 mm × 0.6 mm) ■ PIN ASSIGNMENTS (BCC-20) TOP VIEW (TSSOP-20) TOP VIEW OSCIN 1 20 Clock GND 2 19 Data finIF 3 18 LE XfinIF 4 17 finRF GNDIF 5 16 XfinRF VCCIF 6 15 GNDRF PSIF 7 14 VpIF 8 13 DOIF 9 12 VpRF LD/fout 10 11 DORF finIF 1 20 19 18 17 16 XfinIF 2 finRF GNDIF VCCIF 3 4 15 14 GNDRF VCCRF PSIF 5 13 12 PSRF VpIF 6 (FPT-20P-M06) 2 OSCIN Data GND Clock 7 8 9 10 11 DOIF DORF LD/fout VpRF (LCC-20P-M05) LE XfinRF VCCRF PSRF MB15F83UL ■ PIN DESCRIPTION Pin no. TSSOP BCC Pin name I/O Descriptions I The programmable reference divider input pin. TCXO should be connected with an AC coupling capacitor. 1 19 OSCIN 2 20 GND 3 1 finIF I Prescaler input pin for the IF-PLL. Connection to an external VCO should be AC coupling. 4 2 XfinIF I Prescaler complimentary input pin for the IF-PLL section. This pin should be grounded via a capacitor. 5 3 GNDIF 6 4 VCCIF 7 5 PSIF 8 6 VpIF Power supply voltage input pin for the IF-PLL charge pump. 9 7 DoIF O Charge pump output pin for the IF-PLL section. Phase characteristics of the phase detector can be reversed by FC-bit. 10 8 LD/fout O Look detect signal output (LD) /phase comparator monitoring output (fout) pins. The output signal is selected by an LDS bit in a serial data. LDS bit = “H”; outputs fout signal / LDS bit = “L”; outputs LD signal 11 9 DoRF O Charge pump output pin for the RF-PLL section. Phase characteristics of the phase detector can be reversed by FC-bit. 12 10 VpRF Power supply voltage input pin for the RF-PLL charge pump. 13 11 PSRF I 14 12 VCCRF 15 13 GNDRF 16 14 XfinRF I Prescaler complimentary input pin for the RF-PLL section. This pin should be grounded via a capacitor. 17 15 finRF I Prescaler input pin for the RF-PLL. Connection to an external VCO should be AC coupling. 18 16 LE I Load enable signal input pin (with the schmitt trigger circuit.) On a rising edge of load enable, data in the shift register is transferred to the corresponding latch according to the control bit in a serial data. 19 17 Data I Serial data input pin (with the schmitt trigger circuit.) A data is transferred to the corresponding latch (IF-ref counter, IF-prog. counter, RF-ref. counter, RF-prog. counter) according to the control bit in a serial data. 20 18 Clock I Clock input pin for the 23-bit shift register (with the schmitt trigger circuit.) One bit data is shifted into the shift register on a rising edge of the clock. Ground pin for OSC input buffer and the shift register circuit. Ground pin for the IF-PLL section. Power supply voltage input pin for the IF-PLL section (except for the charge pump circuit) , the shift register and the oscillator input buffer. When power is OFF, latched data of IF-PLL is lost. I Power saving mode control signal pin for the IF-PLL section. This pin must be set at “L” when the power supply is started up. (Open is prohibited.) PSIF = “H”; Normal mode / PSIF = “L”; Power saving mode Power saving mode control pin for the RF-PLL section. This pin must be set at “L” when the power supply is started up. (Open is prohibited. ) PSRF = “H”; Normal mode / PSRF = “L”; Power saving mode Power supply voltage input pin for the RF-PLL section (except for the charge pump circuit) . Ground pin for the RF-PLL section. 3 MB15F83UL ■ BLOCK DIAGRAM VCCIF GNDIF (4) 6 5 (3) 11-bit latch fpIF Binary 11-bit Binary 4-bit swallow counter programmable (IF-PLL) counter (IF-PLL) IF-PLL Phase comp. Charge pump (IF-PLL) (IF-PLL) 9 DoIF (7) Prescaler (IF-PLL) CSC FCC Binary 14-bit programmable ref. counter (IF-PLL) SWC 14-bit latch T2 8/9, 16/17 T1 (1) finIF 3 XfinIF 4 (2) 4-bit latch Power saving LDS PSIF 7 (5) VpIF (6) 8 Lock Det. (IF-PLL) 6-bit latch LDIF Slector LDIF LDRF frIF 7-bit latch 10 LD/fout (8) frRF fpIF fpRF CSF FCF SC2 OR SFW Binary 7-bit programmable ref. counter (RF-PLL) SC1 OSCIN 1 (19) Lock Det. 5-bit latch (RF-PLL) frRF MD2 (15) finRF 17 XfinRF 16 (14) PSRF 13 (11) LE 18 (16) frRF Fractional Counter 13 Prescaler Selector fpRF MD1 (RF-PLL) fpRF 16/17 Power saving RF-PLL Schmitt circuit Binary 10-bit Binary 4-bit swallow counter programmable (RF-PLL) counter (RF-PLL) 4-bit latch 10-bit latch F F F F 1 2 3 4 Phase comp. (RF-PLL) Charge pump (RF-PLL) 4-bit latch Latch selector SC SC1 SC2 Data 19 (17) Clock 20 (18) Schmitt circuit C C C N N N Schmitt circuit 1 2 3 4 (RF-PLL) 23-bit shift register 2 (20) GND O : TSSOP 20 ( ) : BCC 20 OR (12) 14 15 (13) 12 (10) VccRF GNDRF VpRF 11 (9) DoRF MB15F83UL ■ ABSOLUTE MAXIMUM RATINGS Parameter Symbol Unit Min. Max. VCC −0.5 +4.0 V Vp VCC +4.0 V VI −0.5 VCC + 0.5 V LD / fout VO GND VCC V Do VDO GND Vp V Tstg −55 +125 °C Power supply voltage Input voltage Output voltage Rating Storage temperature WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. ■ RECOMMENDED OPERATING CONDITIONS Parameter Symbol Value Unit Remark 3.6 V VCCRF = VCCIF 3.0 3.6 V GND VCC V −40 +85 °C Min. Typ. Max. VCC 2.7 3.0 Vp VCC Input voltage VI Operating temperature Ta Power supply voltage WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 5 MB15F83UL ■ ELECTRICAL CHARACTERISTICS * (VCC = 2.7 V to 3.6 V, Ta = −40 °C to +85 °C) Parameter Symbol Input sensitivity “H” level input voltage “L” level input voltage “H” level input voltage “L” level input voltage “H” level input current “L” level input current “H” level input current “L” level input current Min. Typ. Max. finIF = 480 MHz, SWC = 0 VCCIF = VpIF = 3.0 V 1.0 1.6 2.3 mA ICCRF *1 finRF = 2000 MHz VCCRF = VpRF = 3.0 V 2.8 4.2 5.8 mA IPSIF PS = “L” 0.1 *2 10 µA IPSRF PS = “L” 0.1 *2 10 µA finIF IF PLL 100 600 MHz finRF RF PLL 400 2000 MHz OSCIN fOSC 3 40 MHz finRF finIF PfinIF IF PLL, 50 Ω system −15 +2 dBm finRF PfinRF RF PLL, 50 Ω system −15 +2 dBm OSCIN VOSC 0.5 VCC Vp-p Data, Clock, LE VIH 0.7 VCC + 0.4 0.3 VCC − 0.4 PSIF PSRF VIH 0.7 VCC VIL 0.3 VCC Data, Clock, LE, PSIF, PSRF IIH *4 −1.0 +1.0 IIL *4 −1.0 +1.0 IIH 0 +100 IIL *4 −100 0 VCC − 0.4 0.4 OSCIN VIL Schmitt triger input Schmitt triger input “H” level output voltage LD/ “L” level output voltage fout VOH VCC = Vp = 3.0 V, IOH = −1 mA VOL VCC = Vp = 3.0 V, IOL = 1 mA “H” level output voltage DoIF “L” level output voltage DoRF VDOH VCC = Vp = 3.0 V, IDOH = −0.5 mA Vp − 0.4 VDOL VCC = Vp = 3.0 V, IDOL = 0.5 mA 0.4 IOFF VCC = Vp = 3.0 V VOFF = 0.5 V to Vp − 0.5 V 2.5 IOH *4 VCC = Vp = 3.0 V −1.0 IOL VCC = Vp = 3.0 V 1.0 High impedance cutoff current Unit *3 finIF *3 Operating frequency Value ICCIF *1 Power supply current Power saving current Condition DoIF DoRF “H” level output current LD/ “L” level output current fout V V µA µA V V nA mA (Continued) 6 MB15F83UL (Continued) (VCC = 2.7 V to 3.6 V, Ta = −40 °C to +85 °C) Parameter Symbol “H” level output current IDOH *4 DoIF DoRF “L” level output current IDOL IDOL/IDOH IDOMT *5 Charge pump current rate DOVD *6 vs VDO I vs Ta IDOTA *7 Value Condition Unit Min. Typ. Max. CS bit = “H” −8.2 −6.0 −4.1 mA CS bit = “L” −2.2 −1.5 −0.8 mA CS bit = “H” 4.1 6.0 8.2 mA CS bit = “L” 0.8 1.5 2.2 mA VDO = Vp / 2 3 % 0.5 V ≤ VDO ≤ Vp − 0.5 V 10 % −40 °C ≤ Ta ≤ +85 °C, VDO = Vp / 2 5 % VCC = Vp = 3.0 V VDOH = Vp / 2 Ta = +25 °C VCC = Vp = 3.0 V VDOL = Vp / 2 Ta = +25 °C *1 : Conditions ; fosc = 13 MHz, Ta = +25 °C in locking state. *2 : VCCIF = VpIF = VCCRF = VpRF = 3.0 V, fosc = 13 MHz, Ta = +25 °C, in power saving mode. *3 : AC coupling. 1000 pF capacitor is connected. *4 : The symbol “–” (minus) means direction of current flow. *5 : VCC = Vp = 3.0 V, Ta = +25 °C (||I3| − |I4||) / [ (|I3| + |I4|) / 2] × 100 (%) *6 : VCC = Vp = 3.0 V, Ta = +25 °C [ (||I2| − |I1||) / 2] / [ (|I1| + |I2|) / 2] × 100 (%) (Applied to each lDOL and lDOH) *7 : VCC = Vp = 3.0 V, Ta = +25 °C[ (||IDO (85 °C) | − |IDO (–40 °C) ||) / 2] / [ (|IDO (85 °C) | + |IDO (–40 °C) |) / 2] × 100 (%) (Applied to each IDOL and IDOH) I2 I3 I1 IDOL IDOH 0.5 I1 I4 I2 Vp/2 Vp − 0.5 Vp output voltage (V) 7 MB15F83UL ■ FUNCTIONAL DESCRIPTION 1. Serial Data Input Serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of IF/RF-PLL sections and programmable reference dividers of IF/RF-PLL sections are controlled individually. Serial data of binary code is entered through Data pin. On a rising edge of clock, one bit of serial data is transferred into the shift register. On a rising edge of load enable signal, the data stored in the shift register is transferred to one of latches depending upon the control bit data setting. The programmable The programmable counter and the reference counter for swallow counter for the the IF-PLL IF-PLL The programmable reference counter for the RF-PLL The prgrammable counter and the swallow counter for the RF-PLL CN1 0 1 0 1 CN2 0 0 1 1 CN3 0 0 0 0 Note : (CN3 = 1 is pohibited) (1) Serial data format LSB 1 2 3 4 5 6 Direction of data shift 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 0 0 0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 RC8 RC9 RC10 RC11 RC12 RC13 RC14 LDS T1 T2 SWC FCC CSC 1 0 0 AC1 AC2 AC3 AC4 0 1 0 RF1 RF2 RF3 RF4 RF5 RF6 RF7 1 1 0 AF1 AF2 AF3 AF4 0 0 0 0 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 X 0 0 0 0 0 0 0 0 SC1 SC2 NF1 NF2 NF3 NF4 NF5 NF6 NF7 NF8 NF9 NF10 F1 F2 1 F3 Control bit (CN3) Control bit (CN2) Control bit (CN1) RC1 to RC14 AC1 to AC4 NC1 to NC11 LDS, T1, T2 SWC FCC CSC RF1 to RF7 AF1 to AF4 NF1 to NF10 F1 to F4 SC1, SC2 FCF CSF X : Divide ratio setting bits for the reference counter of the IF (3 to 16383) : Divide ratio setting bits for the swallow counter of the IF (0 to 15, A < N) : Divide ratio setting bits for the programmable counter of the IF (3 to 2047) : Select bits for the lock detect output or a monitoring phase comparison frequency : Divide ratio setting for the prescaler of the IF : Phase control bit for the phase detector of the IF : Charge pump current select bit of the IF : Divide ratio setting bits for the reference counter of the RF (3 to 127) : Divide ratio setting bits for the swallow counter of the RF (0 to 15, A < N − 2) : Divide ratio setting bits for the programmable counter of the RF (18 to 1023) : Fractional-N increment setting bit for the fractional accumulator (0 to 15, F < Q) : Spurious cancel set bit of the RF. : Phase control bit for the phase detector of the RF. : Charge pump current select bit of the RF : Dummy bit (Set “0” or “1”) Note: Data input with MSB first. 8 MSB 22 23 X FCF CSF F4 0 MB15F83UL (2) Data Setting • RF synthesizer Data Setting (Fractional-N) The divide ratio can be calculated using the following equation : fVCORF = NTOTAL × fosc÷R NTOTAL = P × N + A + F / Q fVCORF NTOTAL fosc R P N A F Q ← (A < N − 2, F < Q) : Output frequency of external voltage controlled oscillator (VCO) : Total division ratio from prescaler input to the phase detector input : Output frequency of the reference frequency oscillator : Preset divide ratio of binary 7 bit reference counter (3 to 127) : Preset divide ratio of modulus prescaler (16 fixed) : Preset divide ratio of binary 10 bit programmable counter (18 to 1023) : Preset divide ratio of binary 4 bit swallow counter (0 to 15) : A numerator of fractional-N (0 to 15) : A denominator of fractional-N, modulo 13 • Binary 7-bit Programmable Reference Counter Data Setting (RF1 to RF7) Divide ratio (R) RF7 RF6 RF5 RF4 RF3 RF2 RF1 3 0 0 0 0 0 1 1 4 0 0 0 0 1 0 0 52 0 1 1 0 1 0 0 127 1 1 1 1 1 1 1 Note : Divide ratio less than 3 is prohibited. • Fractional-N incremant of the fractional accumulator Data Setting (F1 to F4) Setting value(F) F4 F3 F2 F1 0 0 0 0 0 1 0 0 0 1 2 0 0 1 0 15 1 1 1 1 Note : F < Q 9 MB15F83UL • Binary 10-bit Programable Counter Data Setting (NF1 to NF10) Divide ratio (N) 18 19 32 1023 NF10 0 0 0 1 NF9 0 0 0 1 NF8 0 0 0 1 NF7 0 0 0 1 NF6 0 0 1 1 NF5 1 1 0 1 NF4 0 0 0 1 NF3 0 0 0 1 Note : Divide ratio less than 18 is prohibited. • Binary 4-bit Swallow Counter Data Setting (AF1 to AF4) Divide ratio (A) AF4 AF3 AF2 AF1 0 0 0 0 0 1 0 0 0 1 2 0 0 1 0 15 1 1 1 1 Note : A < N − 2 • Spurious cancel Bit Setting Spurious cancel amount SC1 Large SC2 0 0 Midium 0 1 Small 1 0 Note : The bits set how much the amount of spurious cancel. If the Large is selected, a spurious is tended to become small. • Phase Comparator Phase Switching Data Setting FCF = Low FCF = High DO DO fr > fp H L fr = fp Z Z fr < fp L H VCO polarity 1 2 Notes : • Z = High-Z • Depending upon the VCO and LPF polarity, FC bit should be set. • Charge pump current select Bit Setting Current value CSF 10 1 ± 6.0 mA 0 ± 1.5 mA NF2 1 1 0 1 NF1 0 1 0 1 MB15F83UL • IF synthesizer Data Setting (Integer) The divide ratio can be calculated using the following equation : fVCOIF = [ (P × N) + A] × fosc÷R fVCOIF P N A fosc R (A < N) : Output frequency of external voltage controlled oscillator (VCO) : Preset divide ratio of modulus prescaler (8 or 16) : Preset divide ratio of binary 11 bit programmable counter (3 to 2047) : Preset divide ratio of binary 4 bit swallow counter (0 to 15) : Output frequency of the reference frequency oscillator : Preset divide ratio of binary 14 bit reference counter (3 to 16383) • Binary 14-bit Programmable Reference Counter Data Setting (RC1 to RC14) Divide ratio (R) RC14 RC13 RC12 RC11 RC10 RC9 RC8 RC7 RC6 RC5 RC4 RC3 RC2 RC1 3 0 0 0 0 0 0 0 0 0 0 0 0 1 1 4 0 0 0 0 0 0 0 0 0 0 0 1 0 0 16383 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Note : Divide ratio less than 3 is prohibited. • Binary 11-bit Programmable Counter Data Setting (NC1 to NC11) Divide ratio (N) NC11 NC10 NC9 NC8 NC7 NC6 NC5 NC4 NC3 NC2 NC1 3 0 0 0 0 0 0 0 0 0 1 1 4 0 0 0 0 0 0 0 0 1 0 0 2047 1 1 1 1 1 1 1 1 1 1 1 Note : Divide ratio less than 3 is prohibited. • Binary 4-bit Swallow Counter Data Setting (AC1 to AC4) Divide ratio (A) AC4 AC3 AC2 AC1 0 0 0 0 0 1 0 0 0 1 2 0 0 1 0 15 1 1 1 1 Note : A < N • Prescaler Data Setting (SWC) Prescaler divide ratio SWC 1 8/9 0 16/17 11 MB15F83UL • Phase Comparator Phase Switching Data Setting FCC = Low FCC = High DO DO fr > fp H L fr = fp Z Z fr < fp L H Notes : • Z = High-Z • Depending upon the VCO and LPF polarity, FC bit should be set. •Charge pump current select Data Setting (CSC) Do current CSC 1 ± 6.0 mA 0 ± 1.5 mA • Common setting • LD/fout Output Select Data Setting LD/fout LDS T1 T2 0 frIF 1 0 0 frRF 1 1 0 fpIF 1 0 1 fpRF 1 1 1 LD output fout output • FC bit Setting When designing a synthesizer, the FC bit setting depends on the VCO and LPF characteristics. When the LPF and VCO characteristics are similar to (1) , set FC bit “H”. When the VCO characteristics are similar to (2) , set FC bit “L”. High (1) VCO output frequency (2) LPF output voltage 12 Max. MB15F83UL 2. Power Saving Mode (Intermittent Mode Control) • PS Pin Setting PS pin Status H Normal mode L Power saving mode The intermittent mode control circuit reduces the PLL power consumption. By setting the PS pin low, the device enters the power saving mode, reducing the current consumption. See “■ ELECTRICAL CHARACTERISTICS” for the specific value. The phase detector output, Do, becomes high impedance. For the single PLL, the lock detector, LD, remains high, indicating a locked condition. For the dual PLL, the lock detector, LD, is shown in “■PHASE DETECTOR OUTPUT WAVEFORM the LD Output Logic table. Setting the PS pin high releases the power saving mode, and the device works normally. The intermittent mode control circuit also ensures a smooth start-up when the device returns to normal operation. When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is because of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr) which can cause a major change in the comparator output, resulting in a VCO frequency jump and an increase in lockup time. To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error signal from the phase detector when it returns to normal operation. Notes: •When power (VCC) is first applied, the device must be in standby mode and PS = Low, for at least 1 µs. •PS pin must be set “L” for Power ON. OFF VCC ON tV ≥ 1 µs Clock Data LE tPS ≥ 100 ns PS (1) (2) (3) (1) PS = L (power saving mode) at Power ON (2) Set serial data 1 µs after power supply remains stable (VCC ≥ 2.2 V) . (3) Release power saving mode (PS : L → H) 100 ns after setting serial data. 13 MB15F83UL 3. Serial Data Input Timing 1st data 2nd data Control bit Data MSB Invalid data LSB Clock LE t1 t4 t3 t2 t5 t6 t7 On the rising edge of the clock, one bit of data is transferred into shift register. Parameter Min. Typ. Max. Unit Parameter Min. Typ. Max. t1 20 ns t5 100 ns t2 20 ns t6 20 ns t3 30 ns t7 100 ns t4 30 ns Note : LE should be “L” when the data is transferred into the shift register. 14 Unit MB15F83UL ■ PHASE DETECTOR OUTPUT WAVEFORM frIF/RF fpIF/RF tWU tWL LD (FC bit = High) DOIF/RF Z H L (FC bit = Low) H DOIF/RF Z L LD Output Logic Table IF-PLL section RF-PLL section LD output Locking state/Power saving state Locking state/Power saving state H Locking state/Power saving state Unlocking state L Unlocking state Locking state/Power saving state L Unlocking state Unlocking state L Notes: • Phase error detection range = −2 π to +2 π • Pulses on DoIF/RF signals are output to prevent dead zone. • LD output becomes low when phase error is tWU or more. • LD output becomes high when phase error is tWL or less and continues to be so for three cycles or more. • tWU and tWL depend on OSCIN input frequency as follows. tWU ≥ 2/fosc [s] : i.e. tWU ≥ 153.8 ns when fosc = 13.0 MHz tWU ≤ 4/fosc [s] : i.e. tWL ≤ 307.7 ns when fosc = 13.0 MHz 15 MB15F83UL ■ TEST CIRCUIT (for Measuring Input Sensitivity fin/OSCIN) fout Oscilloscope VpIF 0.1 µF VCCIF 0.1 µF 1000 pF 1000 pF P.G 1000 pF S.G 50 Ω LD/fout DOIF VpIF 50 Ω 10 9 8 PSIF VCCIF GNDIF XfinIF finIF GND OSCIN 7 6 5 4 3 2 1 17 18 19 20 MB15F83UL 11 1000 pF 12 13 14 15 16 DORF VpRF PSRF VCCRFGNDRF XfinRF finRF LE Data Clock S.G 50 Ω 1000 pF VpRF VCCRF 0.1 µF Note : TSSOP-20 16 0.1 µF Controller (divide ratio setting) MB15F83UL ■ TYPICAL CHARACTERISTICS 1. fin input sensitivity RF-PLL input sensitivity vs. Input frequency Ta = + 25 °C 10 0 2.7 V PfinRF (dBm) SPEC 3.0 V −10 3.6 V −20 SPEC 3.3 V −30 −40 −50 0 500 1000 1500 2000 2500 finRF (MHz) IF-PLL input sensitivity vs. Input frequency Ta = + 25 °C 10 0 2.7 V PfinIF (dBm) SPEC 3.0 V −10 3.3 V −20 3.6 V −30 −40 −50 0 500 1000 1500 2000 finIF (MHz) 17 MB15F83UL 2. OSCIN input sensitivity Input sensitivity vs. Input frequency Ta = + 25 °C 10 SPEC Input sensitivity VOSC (dBm) 0 VCC = 2.7 V −10 VCC = 3.0 V VCC = 3.6 V −20 SPEC −30 −40 −50 −60 0 50 100 150 200 Input frequency fOSC (MHz) 18 250 300 MB15F83UL 3. RF-PLL Do output current • 1.5 mA mode IDO − VDO Charge pump output current IDO (mA) 20 0 −20 0 1 2 3 Charge pump output voltage VDO (V) • 6.0 mA mode Charge pump output current IDO (mA) IDO − VDO 20 0 −20 0 1 2 3 Charge pump output voltage VDO (V) 19 MB15F83UL 4. IF-PLL Do output current • 1.5 mA mode IDO − VDO Charge pump output current IDO (mA) 10.0 VCC = Vp = 2.7 V 0 −10.0 0.0 1.0 2.0 3.0 Charge pump output voltage VDO (V) • 6.0 mA mode IDO − VDO Charge pump output current IDO (mA) 10.0 VCC = Vp = 2.7 V 0 −10.0 0.0 1.0 2.0 3.0 Charge pump output voltage VDO (V) 20 MB15F83UL 5. fin input impedance finR input impedance 1.1765 pF 1 : 45.859 Ω −188.77 Ω 1 GHz 2 : 25.48 Ω −103.67 Ω 1.7 GHz 3 : 22.152 Ω −83.391 Ω 2 GHz 1 3 START 1 000.000 000 MHz 2 STOP 2 600.000 000 MHz finIF input impedance 4 : 9.3437 Ω −75.625 Ω 2.1045 pF 1 000.000 000 MHz 1 : 325.78 Ω −732.22 Ω 100 MHz 2 : 21.516 Ω −170.72 Ω 500 MHz 3 : 12.422 Ω −108.38 Ω 750 MHz 1 2 4 3 START .030 000 MHz STOP 1 000.000 000 MHz 21 MB15F83UL 6. OSCIN input impedance OSCIN input impedance 4 : 092.56 Ω -1.3177 kΩ 2.4157 pF 50.000 000 MHz 1 : 28.625 Ω −667.75 Ω 100 MHz 2 : 2.1273 kΩ −5.9445 kΩ 10 MHz 3 : 2.1273 kΩ −5.9445 kΩ 4 10 MHz 3 2 3 1 START .030 000 MHz 22 STOP 100.000 000 MHz MB15F83UL ■ REFERENCE INFORMATION (for Lock-up Time, Phase Noise and Reference Leakage) Test Circuit S.G. OSC IN LPF DO fin fVCO = 1733 MHz KV = 44 MHz/V fr = 200 kHz fOSC = 13 MHz LPF VCC = 3.0 V VVCO = 3.5 V Ta = +25 °C CP : 6 mA mode QM = 13 10 kΩ Spectrum Analyzer VCO 390 pF 3.0 kΩ 82 pF 3900 pF • PLL Reference Leakage ATTEN 10 dB RL 0 dBm D VAVG 100 10 dB/ ∆MKR −69.00 dB 200 kHz ∆MKR 200 kHz −69.00 dB CENTER 1.733000 GHz RBW 10 kHz VBW 10 kHz SPAN 1.000 MHz SWP 50.0 ms • PLL Phase Noise ATTEN 10 dB RL 0 dBm D VAVG 24 10 dB/ ∆MKR −63.17 dB 1.00 kHz ∆MKR 1.00 kHz −63.17 dB CENTER 1.73299933 GHz RBW 100 Hz VBW 100 Hz SPAN 10.00 kHz SWP 802 ms 23 MB15F83UL • PLL Lock Up time • PLL Lock Up time 1733 MHz→1803 MHz within ± 1 kHz Lch→Hch 189 µs 1.803004500 GHz 1.733004500 GHz 1.803000500 GHz 1.733000500 GHz 1.802996500 GHz −956 µs 24 1803 MHz→1733 MHz within ± 1 kHz Hch→Lch 167 µs 1.732996500 GHz 1.544 ms 500.0 µs/div 4.044 ms −956 µs 1.544 ms 500.0 µs/div 4.044 ms MB15F83UL ■ APPLICATION EXAMPLE VCO OUTPUT from controller LPF 3.0 V 1000 pF 3.0 V 0.1 µF 0.1 µF 1000 pF Clock DATA LE finRF XfinRF GNDRF VCCRF PSRF VpRF DORF 20 19 18 17 16 15 14 13 12 11 MB15F83UL 1 2 3 4 5 6 7 8 9 10 OSCIN GND finIF XfinIF GNDIF VCCIF PSIF VpIF DOIF LD/fout 1000 pF 1000 pF 3.0 V 1000 pF 0.1 µF 3.0 V Lock Det. 0.1 µF TCXO OUTPUT VCO LPF Notes:• Schmit trigger circuit is provided (insert a pull-up or pull-down resistor to prevent oscillation when open-circuited in the input) . • TSSOP-20 25 MB15F83UL ■ USAGE PRECAUTIONS (1) VCCRF, VpRF, VCCIF and VpIF must be equal voltage. Even if either RF-PLL or IF-PLL is not used, power must be supplied to VCCRF, VpRF, VCCIF and VpIF to keep them equal. It is recommended that the non-use PLL is controlled by power saving function. (2) To protect against damage by electrostatic discharge, note the following handling precautions : -Store and transport devices in conductive containers. -Use properly grounded workstations, tools, and equipment. -Turn off power before inserting or removing this device into or from a socket. -Protect leads with conductive sheet, when transporting a board mounted device. ■ ORDERING INFORMATION Part number 26 Package MB15F83ULPFT 20-pin plastic TSSOP (FPT-20P-M06) MB15F83ULPVA 20-pad plastic BCC (LCC-20P-M05) Remarks MB15F83UL ■ PACKAGE DIMENSIONS 20-pin Plastic TSSOP (FPT-20P-M06) * : These dimensions do not include resin protrusion. * 6.50±0.10(.256±.004) 0.17±0.05 (.007±.002) 11 20 * 4.40±0.10 6.40±0.20 (.173±.004) (.252±.008) INDEX Details of "A" part 1.05±0.05 (Mounting height) (.041±.002) LEAD No. 1 10 0.65(.026) "A" 0.24±0.08 (.009±.003) 0.13(.005) M 0~8° +0.03 (0.50(.020)) 0.10(.004) C 0.45/0.75 (.018/.030) +.001 0.07 –0.07 .003 –.003 (Stand off) 0.25(.010) 1999 FUJITSU LIMITED F20026S-2C-2 Dimensions in mm (inches) (Continued) 27 MB15F83UL (Continued) 20-pad plastic BCC (LCC-20P-M05) 3.00(.118)TYP 3.60±0.10(.142±.004) 16 0.55±0.05 (.022±.002) (Mounting height) 11 11 0.25±0.10 (.010±.004) 16 0.50(.020) TYP 0.25±0.10 (.010±.004) INDEX AREA 3.40±0.10 (.134±.004) 2.70(.106) TYP "D" "A" 1 6 "C" 6 Details of "A" part 0.50±0.10 (.020±.004) 1 0.50(.020) TYP 2.80(.110)REF 0.075±0.025 (.003±.001) (Stand off) 0.05(.002) "B" Details of "B" part 0.50±0.10 (.020±.004) Details of "C" part Details of "D" part 0.50±0.10 (.020±.004) 0.30±0.10 (.012±.004) C0.20(.008) 0.60±0.10 (.024±.004) C 0.30±0.10 (.012±.004) 0.60±0.10 (.024±.004) 0.40±0.10 (.016±.004) 2001 FUJITSU LIMITED C20056S-c-2-1 Dimensions in mm (inches) 28 MB15F83UL FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F0107 FUJITSU LIMITED Printed in Japan