FUJITSU SEMICONDUCTOR DATA SHEET DS07-13706-1E 16-bit Proprietary Microcontroller CMOS F2MC-16LX MB90550A Series MB90552A/553A/T552A/T553A/F553A/P553A ■ DESCRIPTION The MB90550A series is a line of general-purpose, high-performance, 16-bit microcontrollers designed for applications which require high-speed real-time processing, such as industrial machines, OA equipment, and process control systems. While inheriting the AT architecture of the F2MC*-8 family, the instruction set for the MB90550A series incorporates additional instructions for high-level languages, supports extended addressing modes, and contains enhanced multiplication and division instructions as well as a substantial collection of improved bit manipulation instructions. In addition, the MB90550A has an on-chip 32-bit accumulator which enables processing of long-word data. *: F2MC stands for FUJITSU Flexible Microcontroller. ■ FEATURES • Minimum instruction execution time : 62.5 ns (at oscillation of 4 MHz,×four times the PLL clock) • Maximum memory space 16 Mbytes • Instruction set optimized for controller applications Supported data types : Bit, byte, word, and long word Typical addressing mode : 23 types Enhanced precision calculation realized by the 32-bit accumulator Enhanced signed multiplication/division instruction and RETI instruction functions (Continued) ■ PACKAGES 100-pin plastic QFP 100-pin plastic LQFP (FPT-100P-M06) (FPT-100P-M05) MB90550A Series (Continued) • Instruction set designed for high level language (C) and multi-task operations Adoption of system stack pointer Symmetrical instruction set and barrel shift instructions • Address match detection function integrated (for two address pointers) • Faster execution speed : 4-byte queue • Powerful interrupt functions (Eight priority levels programmable) External interrupt inputs : 8 channels • Data transfer functions (Intelligent I/O service) : Up to 16 channels DTP request inputs : 8 channels • Embedded ROM size (EPROM, Flash : 128 Kbytes) Mask ROM : 64 Kbytes/128 Kbytes • Embedded RAM size (EPROM, Flash : 4 Kbytes) Mask ROM : 2 Kbytes/4 Kbytes • General-purpose ports :Up to 83 channels (Input pull-up resistor settable for : 16 channels Open drain settable for : 8 channels I/O open drains : 6 channels) • A/D converter (RC successive approximation type): 8 channels (Resolution: 8 or 10 bits selectable; Conversion time of 26.3 µs minimum) • UART : 1 channel • Extended I/O serial interface : 2 channels • I2C interface : 2 channels (Two channels, including one switchable between terminal input and output) • 16-bit reload timer : 2 channels • 8/16-bit PPG timer : 3 channels (8 bits × 2 channels; 16 bits x 1 channel: Mode switching function provided) • 16-bit I/O timer (Input capture × 4 channels, output compare × 4 channels, free run timer ×1 channel • Clock monitor function integrated (Delivering the oscillation clock divided by 21 to 28) • Timebase timer/watchdog timer : 18 bit • Low power consumption modes (sleep, stop, hardware standby, and CPU intermittent operation modes) • Package : QFP-100, LQFP-100 • CMOS technology 2 MB90550A Series ■ PRODUCT LINEUP Part number MB90552A MB90553A MB90F553A MB90P553A MB90V550A Flash ROM products OTP Evaluation product Item Mask ROM products Classification Mass Product ROM size 64 Kbytes 128 Kbytes None RAM size 2 Kbytes 4 Kbytes 6 Kbytes The number of instructions: 340 Instruction bit length: 8 bits, 16 bits Instruction length: 1 byte to 7 bytes Data bit length: 1 bit, 8 bits, 16 bits Minimum execution time: 62.5 ns (at machine clock of 16 MHz) Interrupt processing time: 1.5 ms (at machine clock of 16 MHz, minimum value) CPU functions Ports General-purpose I/O ports (CMOS output): 53 General-purpose I/O ports (with pull-up resistor): 16 General-purpose I/O ports (N-channel open-drain output): 6 General-purpose I/O ports (N-channel open-drain function selectable): 8 Total: 83 UART0 (SCI) Clock synchronized transmission (62.5 kbps to 2 Mbps) Clock asynchronized transmission (62500 bps to 9615 bps) Transmission can be performed by bi-directional serial transmission or by master/slave connection. 8/10-bit A/D converter Resolution: 8/10-bit Number of inputs: 8 One-shot conversion mode (converts selected channel only once) Scan conversion mode (converts two or more successive channels and can program up to 8 channels.) Continuous conversion mode (converts selected channel continuously) Stop conversion mode (converts selected channel and stop operation repeatedly) 8/16-bit PPG timer Number of channels: 1 (or 8-bit × 2 channels) PPG operation of 8-bit or 16-bit A pulse wave of given intervals and given duty ratios can be output. Pulse interval: 62.5 ns to 1 ms (at oscillation of 4 MHz, machine clock of 16 MHz) 16-bit I/O timer 16-bit free run timer Number of channel: 1 Overflow interrupts Output compare (OCU) Number of channels: 4 Pin input factor: A match signal of compare register Input capture (ICU) Number of channels: 4 Rewriting a register value upon a pin input (rising, falling, or both edges) (Continued) 3 MB90550A Series (Continued) Part number MB90552A MB90553A MB90F553A MB90P553A MB90V550A Item DTP/external interrupt circuit Number of inputs: 8 Started by a rising edge, a falling edge, an “H” level input, or an “L” level input. External interrupt circuit or extended intelligent I/O service (EI2OS) can be used. Extended I/O serial interface Clock synchronized transmission (3125 bps to 1 Mbps) LSB first/MSB first I2C interface Serial I/O port for supporting Inter IC BUS Timebase timer 18-bit counter Interrupt interval: 1.024 ms, 4.096 ms, 16.384 ms, 131.072 ms (at oscillation of 4 MHz) Watchdog timer Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms (at oscillation of 4 MHz, minimum value) Process CMOS Power supply voltage for operation* 4.5 V to 5.5 V *:Varies with conditions such as the operating frequency. (See section “■ ELECTRICAL CHARACTERISTICS”) Assurance for the MB90V550A is given only for operation with a tool at a power voltage of 4.5 V to 5.5 V, an operating temperature of 0 to +25°C, and an operating frequency of 1 MHz to 16 MHz. ■ PACKAGE AND CORRESPONDING PRODUCTS Package MB90552A MB90553A MB90F553A FPT-100P-M05 MB90P553A × FPT-100P-M06 : Available × : Not available Note:For more information about each package, see section “■ PACKAGE DIMENSIONS” ■ DIFFERENCES AMONG PRODUCTS Memory Size In evaluation with an evaluation product, note the difference between the evaluation product and the product actually used. The following items must be taken into consideration. • The MB90V550A does not have an internal ROM, however, operations equivalent to chips with an internal ROM can be evaluated by using a dedicated development tool, enabling selection of ROM size by settings of the development tool. • In the MB90V550, images from FF4000H to FFFFFFH are mapped to bank 00, and FE0000H to FF3FFFH to mapped to bank FE and FF only. (This setting can be changed by configuring the deveolpment tool.) • In the MB90F553A/553A/552A, images from FF4000H to FFFFFFH are mapped to bank 00, and FF0000H to FF3FFFH to bank FF only. 4 MB90550A Series ■ PIN ASSIGNMENT • FPT-100P-M06 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 P17/AD15 P16/AD14 P15/AD13 P14/AD12 P13/AD11 P12/AD10 P11/AD09 P10/AD08 P07/AD07 P06/AD06 P05/AD05 P04/AD04 P03/AD03 P02/AD02 P01/AD01 P00/AD00 VCC X1 X0 VSS (Top view) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PA4/CKOT PA3 PA2 RST PA1/OUT3 PA0/OUT2 P97/PPG5 P96/PPG4 P95/PPG3 P94/PPG2 P93/PPG1 P92/PPG0 P91/OUT1 P92/OUT0 P87/IN3 P86/IN2 P85/IN1 P84/IN0 P83/TOT1 P82/TOT0 P81/TIN1 P80/TIN0 P77/IRQ7 P76/IRQ6 P75/IRQ5 P74/IRQ4 P73/IRQ3 P72/IRQ2 HST MD2 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 P53/SCL1 P54/SDA2 P55/SCL2 AVCC AVRH AVRL AVSS P60/AN0 P61/AN1 P62/AN2 P63/AN3 VSS P64/AN4 P65/AN5 P66/AN6 P67/AN7 P70/IRQ0 P71/IRQ1 MD0 MD1 P20/A16 P21/A17 P22/A18 P23/A19 P24/A20 P25/A21 P26/A22 P27/A23 P30/ALE P31/RD VSS P32/WRL P33/WRH P34/HRQ P35/HAK P36/RDY P37/CLK P40/SCK P41/SOT P42/SIN P43/SCK1 P44/SOT1 VCC P45/SIN1 P46/ADTG P47/SCK0 C P50/SDA0/SOT0 P51/SCL0/SIN0 P52/SDA1 (FPT-100P-M06) 5 MB90550A Series • FPT-100P-M05 100 P21/A17 99 P20/A16 98 P17/AD15 97 P16/AD14 96 P15/AD13 95 P14/AD12 94 P13/AD11 93 P12/AD10 92 P11/AD09 91 P10/AD08 90 P07/AD07 89 P06/AD06 88 P05/AD05 87 P04/AD04 86 P03/AD03 85 P02/AD02 84 P01/AD01 83 P00/AD00 82 VCC 81 X1 80 X0 79 VSS 78 PA4/CKOT 77 PA3 76 PA2 (Top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P50/SDA0/SOT0 P51/SCL0/SIN0 P52/SDA1 P53/SCL1 P54/SDA2 P55/SCL2 AVCC AVRH AVRL AVSS P60/AN0 P61/AN1 P62/AN2 P63/AN3 VSS P64/AN4 P65/AN5 P66/AN6 P67/AN7 P70/IRQ0 P71/IRQ1 MD0 MD1 MD2 HST 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P22/A18 P23/A19 P24/A20 P25/A21 P26/A22 P27/A23 P30/ALE P31/RD VSS P32/WRL P33/WRH P34/HRQ P35/HAK P36/RDY P37/CLK P40/SCK P41/SOT P42/SIN P43/SCK1 P44/SOT1 VCC P45/SIN1 P46/ADTG P47/SCK0 C (FPT-100P-M05) 6 RST PA1/OUT3 PA0/OUT2 P97/PPG5 P96/PPG4 P95/PPG3 P94/PPG2 P93/PPG1 P92/PPG0 P91/OUT1 P90/OUT0 P87/IN3 P86/IN2 P85/IN1 P84/IN0 P83/TOT1 P82/TOT0 P81/TIN1 P80/TIN0 P77/IRQ7 P76/IRQ6 P75/IRQ5 P74/IRQ4 P73/IRQ3 P72/IRQ2 MB90550A Series ■ PIN DESCRIPTION Pin no. Pin name Circuit type 80 X0 A Oscillation pin 83 81 X1 A Oscillation pin 77 75 RST B Reset input pin 52 50 HST C Hardware standby input pin QFP LQFP 82 P00 to P07 85 to 92 83 to 90 93 to 100 D (CMOS) Serve as lower data I/O/lower address output (AD00 to AD07) pins in the external bus mode. P10 to P17 General-purpose I/O port. A pull-up resistor can be added (RD17 to RD10 = 1) by using the pull-up resistor setting register (RDR1). D17 to D10 = 1: Disabled when the port is set for output. 91 to 98 D (CMOS) Serve as upper data I/O/middle address output (AD08 to AD15) pins in the 16-bit bus-width, external bus mode. P20 to P27 99,100, 1 to 6 E (CMOS) A16 to A23 P30 9 7 ALE P31 10 8 RD P32 12 10 WRL P33 13 General-purpose I/O port. A pull-up resistor can be added (RD07 to RD00 = 1) by using the pull-up resistor setting register (RDR0). D07 to D00 = 1: Disabled when the port is set for output. AD00 to AD07 AD08 to AD15 1 to 8 Function 11 WRH E (CMOS) E (CMOS) E (CMOS) E (CMOS) General-purpose I/O port. This function is enabled either in single-chip mode or with the xternal address output control register set to "Port". External address bus A16 to A23 output pins. This function is enabled in an external-bus enabled mode with the external address output register set to "Address". General-purpose I/O port. This function is enabled in single-chip mode. Address latch enable output pin. This function is enabled in an external-bus enabled mode. General-purpose I/O port. This function is enabled in single-chip mode. Read strobe output pin for the data bus. This function is enabled in an external-bus enabled mode. General-purpose I/O port. This function is enabled in single-chip mode. Write strobe output pin for the lower eight bits of the data bus. This function is enabled in an external-bus enabled mode. General-purpose I/O port. This function is enabled in single-chip mode. Write strobe output pin for the upper eight bits of the data bus. This function is enabled in an external-bus enabled mode. (Continued) 7 MB90550A Series Pin no. QFP LQFP Pin name P34 14 12 HRQ P35 15 13 HAK P36 16 14 RDY P37 17 15 CLK P40 18 19 20 21 16 Circuit type E (CMOS) E (CMOS) E (CMOS) E (CMOS) F (CMOS/H) Function General-purpose I/O port. This function is enabled in single-chip mode Hold request input pin. This function is enabled in an external-bus enabled mode. General-purpose I/O port. This function is enabled in single-chip mode. Hold acknowledge output pin. This function is enabled in an external-bus enabled mode. General-purpose I/O port. This function is enabled in single-chip mode. Ready signal input pin. This function is enabled in an external-bus enabled mode. General-purpose I/O port. This function is enabled in single-chip mode. CLK output pin. This function is enabled in an external-bus enabled mode. General-purpose I/O port. Serves as an open-drain output port (OD40 = 1) depending on the setting of the open-drain control setting register (ODR4). (D40 = 0: Disabled when the port is set for input.) SCK UART serial clock I/O pin. This function is enabled with the UART clock output enabled. P41 General-purpose I/O port. Serves as an open-drain output port (OD41 = 1) depending on the setting of the open-drain control setting register (ODR4). (D41 = 0: Disabled when the port is set for input.) 17 F (CMOS/H) SOT UART serial data output pin. This function is enabled with the UART serial data output enabled. P42 General-purpose I/O port. Serves as an open-drain output port (OD42 = 1) depending on the setting of the open-drain control setting register (ODR4). (D42 = 0: Disabled when the port is set for input.) F (CMOS/H) 18 SIN UART serial data input pin. Since this input is used as required while the UART is operating for input, the output by any other function must be off unless used intentionally. P43 General-purpose I/O port. Serves as an open-drain output port (OD43 = 1) depending on the setting of the open-drain control setting register (ODR4). (D43 = 0: Disabled when the port is set for input.) 19 SCK1 F (CMOS/H) Extended I/O serial clock I/O pin. This function is enabled with the extended I/O serial clock output enabled. (Continued) 8 MB90550A Series Pin no. QFP LQFP Pin name Circuit type P44 22 24 25 F (CMOS/H) 20 Extended I/O serial data output pin. This function is enabled with the extended I/O serial data output enabled. P45 General-purpose I/O port. Serves as an open-drain output port (OD45 = 1) depending on the setting of the open-drain control setting register (ODR4). (D45 = 0: Disabled when the port is set for input.) F (CMOS/H) 22 SIN1 Extended I/O serial data input pin. Since this input is used as required while the extended I/O serial interface is operating for input, the output by any other function must be off unless used intentionally. P46 General-purpose I/O port. Serves as an open-drain output port (OD46 = 1) depending on the setting of the open-drain control setting register (ODR4). (D46 = 0: Disabled when the port is set for input.) F (CMOS/H) 23 P47 24 F (CMOS/H) 25 C — P50 SDA0 28 26 SOT0 A/D converter external trigger input pin. Since this input is used as required while the A/D converter is operating for input, the output by any other function must be off unless used intentionally. General-purpose I/O port. Serves as an open-drain output port (OD47 = 1) depending on the setting of the open-drain control setting register (ODR4). D47 = 0: Disabled when the port is set for input. Extended I/O serial clock I/O pin. This function is enabled with the extended I/O serial clock output enabled. SCK0 27 General-purpose I/O port. Serves as an open-drain output port (OD44 = 1) depending on the setting of the open-drain control setting register (ODR4). (D44 = 0: Disabled when the port is set for input.) SOT1 ADTG 26 Function Capacitance pin for regulating the power supply. Connect an external ceramic capacitor of about 0.1 µF. N-channel open-drain I/O port. G (NchOD/H) I2C interface data I/O pin. This function is enabled with the I2C interface enabled for operation. While the I2C interface is operating, place the port output in the Hi-Z state (PDR = 1). Extended I/O serial data output pin. This function is enabled with the extended I/O serial data output enabled. (Continued) 9 MB90550A Series Pin no. QFP LQFP Pin name Circuit type P51 N-channel open-drain I/O port. SCL0 29 G (NchOD/H) 27 P52,P54 28,30 SDA1,SDA2 N-channel open-drain I/O port. G (NchOD/H) P53,P55 31,33 29,31 38 to 41, 36 to 39, 43 to 46 41 to 44 SCL1,SCL2 P60 to P67 AN0 to AN7 G (NchOD/H) H (CMOS/H) 57,58 61,62 59,60 TIN0,TIN1 P82,P83 TOT0,TOT1 I (CMOS/H) 67,68 65,66 IN0 to IN3 P90,P91 OUT0,OUT1 General-purpose I/O port. A/D converter analog input pin. This function is enabled with the analog input enabled. External interrupt request input pins. Since this input is used as required while external interrupts remain enabled, the output by any other function must be off unless used intentionally. General-purpose I/O port. J (CMOS/H) Reload timer event input pins. Since this input is used as required while the reload timer is operating for input, the output by any other function must be off unless used intentionally. J (CMOS/H) General-purpose I/O port. P84 to P87 63 to 66 61 to 64 I2C interface clock I/O pins. This function is enabled with the I2C interface enabled for operation. While the I2C interface is operating, place the port output in the Hi-Z state (PDR = 1). General-purpose I/O port. P80,P81 59,60 I2C interface data I/O pins. This function is enabled with the I2C interface enabled for operation. While the I2C interface is operating, place the port output in the Hi-Z state (PDR = 1). N-channel open-drain I/O port. P70 to P77 47,48, 45,46, 53 to 58 51 to 56 IRQ0 to IRQ7 I2C interface clock I/O pin. This function is enabled with the I2C interface enabled for operation. While the I2C interface is operating, place the port output in the Hi-Z state (PDR = 1). Extended I/O serial data input pin. Since this input is used as required while the extended I/O serial interface is operating for input, the output by any other function must be off unless used intentionally. SIN0 30,32 Function Reload timer output pins. General-purpose I/O port. J (CMOS/H) Input capture trigger input pin. Since this input is used as required while the input capture unit is operating for input, the output by any other function must be off unless used intentionally. J (CMOS/H) General-purpose I/O port. Output compare event output pins. (Continued) 10 MB90550A Series (Continued) Pin no. QFP LQFP Pin name P92 to P97 69 to 74 67 to 72 75,76 73,74 78,79 76,77 80 78 34 PPG0 to PPG5 PA0,PA1 OUT2,OUT3 PA2,PA3 PA4 Circuit type J (CMOS/H) J (CMOS/H) J (CMOS/H) Function General-purpose I/O port. PPG output pins. This function is enabled with the PPG output enabled. General-purpose I/O port. Output compare event output pins. General-purpose I/O port. General-purpose I/O port. CKOT J (CMOS/H) 32 AVCC A/D converter power-supply pin. 35 33 AVRH This is a general purpose I/O port. 36 34 AVRL A/D converter external reference voltage source pin. 37 35 AVSS A/D converter power-supply pin. MD0,MD1 C Operation mode setting input pins. Connect these pins directly to Vcc or Vss. K Operation mode setting input pin. Connect this pin directly to Vcc or Vss. (MB90552A/553A/ V550A) C Operation mode setting input pin. Connect this pin directly to Vcc or Vss. (MB90P553A/F553A) 49 to 50 47 to 48 51 49 MD2 Serves as the CKOT output while the CKOT is operating. 23,84 21,82 VCC Power (5 V) input pin. 11,42, 81 9,40, 79 VSS Power (0 V) input pin. 11 MB90550A Series ■ I/O CIRCUIT TYPE Type Circuit Remarks Clock input X1 A • 3 MHz to 32 MHz • Oscillator recovery resistor approx. 1MΩ X0 HARD,SOFT STANDBY CONTROL • CMOS level hysteresis input • Pull-up resistor provided Resistor : About 50 kΩ B • CMOS level hysteresis input C Pull-up resistor control Digital output • • • • CMOS level output CMOS level input Standby control provided Input pull-up resistor control provided Resistor: About 50 kΩ Digital output D Digital input HARD,SOFT STANDBY CONTROL (Continued) 12 MB90550A Series Type Circuit Remarks Digital output • CMOS level output • CMOS level input • Standby control provided Digital output E Digital input HARD,SOFT STANDBY CONTROL Open- drain control signal • CMOS level output • CMOS level hysteresis input • Open-drain control provided Digital input F Digital input HARD,SOFT STANDBY CONTROL Digital output G Digital input HARD,SOFT STANDBY CONTROL Digital output • N-channel open-drain output • CMOS level hysteresis input • Standby control provided Note: Unlike normal CMOS I/O pins, this pin is not provided with any P-channel transistor. Therefore the pin does not allow a current to flow to the Vcc side even when applied with a voltage from an external device with the IC’s power supply left off. • • • • CMOS level output CMOS level hysteresis input Standby control provided Analog input Digital output H Analog input Digital input HARD,SOFT STANDBY CONTROL A/D DISABLE (Continued) 13 MB90550A Series (Continued) Type Circuit Remarks Digital output • CMOS level output • CMOS level hysteresis input • Standby control provided Digital output I Digital input HARD STANDBY CONTROL Digital output • CMOS level output • CMOS level hysteresis input • Standby control provided Digital output J Digital input HARD,SOFT STANDBY CONTROL • CMOS level hysteresis input • Pull-up resistor provided Resistor : About 50kΩ K 14 MB90550A Series ■ HANDLING DEVICES 1. Preventing Latchup CMOS ICs may cause latchup in the following situations: • When a voltage higher than Vcc or lower than Vss is applied to input or output pins. • When a voltage exceeding the rating is applied between Vcc and Vss. • When AVcc power is supplied prior to the Vcc voltage. If latchup occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the device. Use meticulous care not to let it occur. For the same reason, also be careful not to let the analog power-supply voltage exceed the digital power-supply voltage. 2. Connection of Unused Pins Leaving unused pins open may result in abnormal operations. Clamp the pin level by connecting it to a pull-up or a pull-down 1kΩ or more resistor. 3. Notes on Using External Clock In using the external clock, drive X0 pin only and leave X1 pin unconnected. • Using external clock MB90550A series X0 Open X1 4. Power Supply Pins (VCC/VSS) In products with multiple VCC or VSS pins, the pins of a same potential are internally connected in the device to avoid abnormal operations including latch-up. However, connect the pins external power and ground lines to lower the electro-magnetic emission level and abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total current rating. Make sure to connect VCC and VSS pins via lowest impedance to power lines. It is recommended to provide a bypass capacitor of around 0.1 µF between VCC and VSS pin near the device. • Using power supply pins VCC VSS VCC VSS VSS VCC MB90550A series VCC VSS VSS VCC 15 MB90550A Series 5. Crystal Oscillator Circuit Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other circuits. It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with an grand area for stabilizing the operation. 6. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs Make sure to turn on the A/D converter power supply, D/A converter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to AN7) after turning-on the digital power supply (VCC). Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure that the voltage not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simultaneously is acceptable). 7. Connection of Unused Pins of A/D Converter Connect unused pin of A/D converter to AVCC = VCC, AVSS = AVRH = AVRL = VSS. 8. N.C. Pin The N.C. (internally connected) pin must be opened for use. 9. Notes on Energization To prevent the internal regulator circuit rom malfunctioning,set the voltage rise time during energization at 50 or more µs. 10. Initialization In the device, there are internal registers which is initialized only by a power-on reset. To initialize these registers turning on the power again. 11. Return from standby state If the power-supply voltage goes below the standby RAM holding voltage in the standby state, the device may fail to return from the standby state. In this case, reset the device via the external reset pin to return to the normal state. 12. Precautions for Use of ’DIV A, Ri,’ and ’DIVW A, Ri’ Instructions The signed multiplication-division instructions ’DIV A, Ri,’ and ’DIVW A, RWi’ should be used when the corresponding bank registers (DTB, ADB, USB, SSB) are set to value ’00h.’ If the corresponding bank registers (DTB, ADB, USB, SSB) are set to a value other than ’00h,’ then the remainder obtained after the execution of the instruction will not be placed in the instruction operand register. 16 MB90550A Series ■ BLOCK DIAGRAM X0, X1 RST 4 CPU Clock control circuit* Core of F2MC-16LX family HST Interrupt controller RAM Port A ROM P00 to P07/ AD00 to AD07 Port 0 P10 to P17/ AD08 to AD15 Port 1 P20 to P27/ A16 to A23 Port 2 P30/ALE Port 3 F F M C 16 L X B U S P31/RD Clock monitor function CKOT/PA4 PA2, A3 OUT2, OUT3/ PA0, A1 Port 9 PPG5/P97 PPG4/P96 8/16 PPG × 3c h P32/WRL PPG3/P95 PPG2/P94 P33/WRH PPG1/P93 P34/HRQ I/O timer P35/HAK P36/RDY 16-bit output compare unit x 4 channels P37/CLK 16-bit input capture unit x 4 channels 16-bit free-run timer PPG0/P92 OUT0, OUT1/ P90, P91 IN0 to IN3/ P84 to P87 Port 4 Communication prescaler 16-bit reload timer x 2 channels TOT0, TOT1/ P82, P83 TIN0, TIN1/ P80, P81 P40/SCK P41/SOT UART Port 8 P42/SIN P43/SCK1 P44/SOT1 Port 7 Extended I/O serial interface 1 External interrupt P45/SIN1 IRQ0 to IRQ7/ P70 to P77 P46/ADTG AVCC P47/SCK0 P50/SDA0/SOT0 Extended I/O serial interface 0 A/D converter (8/10 bits) I2C interface 0 P53/SCL1 P54/SDA2 AVSS AN0 to AN7/ P60 to P67 P51/SCL0/SIN0 P52/SDA1 AVRH, AVRL Port 6 *: Specifications of evaluation model I2C interface 1 P55/SCL2 Port 5 (MB90V550A) Contains no internal ROM. Contains 6 KB of internal RAM. Contains the same internal resources as the other products in the MB90550A series. 17 MB90550A Series Note: The clock control circuit contains a watchdog timer, time-base timer, and a low power consumption control circuit. P00 to P07 (8 pins): Input pull-up resistor setting register provided P10 to P17 (8 pins): Input pull-up resistor setting register provided P40 to P47 (8 pins): Open-drain control setting register provided P50 to P55 (6 pins): N-channel open drain Ports 0, 1, 2, 3, 4, 6, 7, 8, 9, and A are CMOS level input/output ports. 18 MB90550A Series ■ MEMORY MAP The ROM data of bank FF is reflected in the upper address of bank 00, realizing effective use of the C compiler small model. The lower 16-bit of bank FF and the lower 16-bit of bank 00 is assigned to the same address, enabling reference of the table on the ROM without stating “far”. For example, if an attempt has been made to access 00C000H, the contents of the ROM at FFC000H are accessed actually. Since the ROM area of the FF bank exceeds 48 Kbytes, the whole area cannot be reflected in the image for the 00 bank. The ROM data at FF4000H to FFFFFFH looks, therefore, as if it were the image for 004000H to 00FFFFH. Thus, it is recommended that the ROM data table be stored in the area of FF4000H to FFFFFFH. Internal ROM Single chip mode A mirror function is supported external bus mode A mirror function is supported External ROM external bus mode FFFFFFH ROM area ROM area ROM area (image of bank FF) ROM area (image of bank FF) Address#1 FF0000H 010000H Address#2 : Internal access memory 004000H 002000H : External access memory Address#3 RAM Registor RAM Registor RAM Registor Peripheral Peripheral Peripheral 000100H 0000C0H 0000D0H : Inhibited area Parts No. Address#1 Address#2 Address#3 MB90552A FF0000H 004000H 000900H MB90553A FE0000H 004000H 001100H MB90F553A FE0000H 004000H 001100H MB90P553A FE0000H 004000H 001100H MB90V550A (FE0000H) 004000H 001900H 19 MB90550A Series ■ F2MC-16LX CPU PROGRAMMING MODEL • Dedicated registers AH : Accumlator (A) Dual 16-bit register used for storing results of calculation etc. The two 16-bit registers can be combined to be used as a 32-bit register. AL USP : User stack pointer (USP) The 16-bit pointer indicating a user stack address. SSP : System stack pointer (SSP) The 16-bit pointer indicating the status of the system stack address. PS : Processor status (PS) The 16-bit register indicating the system status. PC : Program counter (PC) The 16-bit register indicating storing location of the current instruction code. DPR PCB : Program bank register (PCB) The 8-bit register indicating the program space. DTB : Data bank register (DTB) The 8-bit register indicating the data space. USB : User stack bank register (USB) The 8-bit register indicating the user stack space. SSB : System stack bank register (SSB) The 8-bit register indicating the system stack space. ADB : Additional data bank register (ADB) The 8-bit register indicating the additional data space. 8 bit 16 bit 32 bit 20 : Direct page register (DPR) The 8-bit register indicating bit 8 through 15 of the operand address in the short direct addressing mode. MB90550A Series ■ I/O MAP Address Register name Abbreviated register name Read/write Resource name Initial value 00H Port 0 data register PDR0 R/W Port 0 XXXXXXXX 01H Port 1 data register PDR1 R/W Port 1 XXXXXXXX 02H Port 2 data register PDR2 R/W Port 2 XXXXXXXX 03H Port 3 data register PDR3 R/W Port 3 XXXXXXXX 04H Port 4 data register PDR4 R/W Port 4 XXXXXXXX 05H Port 5 data register PDR5 R/W Port 5 __111111 06H Port 6 data register PDR6 R/W Port 6 XXXXXXXX 07H Port 7 data register PDR7 R/W Port 7 XXXXXXXX 08H Port 8 data register PDR8 R/W Port 8 XXXXXXXX 09H Port 9 data register PDR9 R/W Port 9 XXXXXXXX 0AH Port A data register PDRA R/W Port A _ _ _XXXXX 0BH to 0FH (Disabled) 10H Port 0 direction register DDR0 R/W Port 0 00000000 11H Port 1 direction register DDR1 R/W Port 1 00000000 12H Port 2 direction register DDR2 R/W Port 2 00000000 13H Port 3 direction register DDR3 R/W Port 3 00000000 14H Port 4 direction register DDR4 R/W Port 4 00000000 (Disabled) 15H 16H Port 6 direction register DDR6 R/W Port 6 00000000 17H Port 7 direction register DDR7 R/W Port 7 00000000 18H Port 8 direction register DDR8 R/W Port 8 00000000 19H Port 9 direction register DDR9 R/W Port 9 00000000 1AH Port A direction register DDRA R/W Port A ___00000 1BH Port 4 output pin register ODR4 R/W Port 4 00000000 1CH Port 0 resistor setting register RDR0 R/W Port 0 00000000 1DH Port 1 resistor setting register RDR1 R/W Port 1 00000000 Port 6, A/D converter 11111111 (Disabled) 1EH 1FH Analog input enable register ADER R/W 20H Serial mode register SMR R/W 00000000 21H Serial control register SCR R/W 0 0 0 0 0 10 0 22H Serial input data register / serial output data register SIDR/SODR R/W 23H Serial status register SSR R/W UART XXXXXXXX 00001_00 (Continued) 21 MB90550A Series Address Register name Abbreviated register name Read/write 24H Serial mode control status register 0 25H Serial mode control status register 0 26H Serial data register 0 SDR0 R/W 27H Clock frequency-divider control register CDCR R/W 28H Serial mode control status register 1 29H Serial mode control status register 1 2AH Serial data register 1 R/W SMCS0 R/W! SMCS1 R/W! SDR1 Initial value ____0000 Extended I/O serial interface 0 00000010 XXXXXXXX Communication prescaler R/W 0___1111 ____0000 Extended I/O serial interface 1 R/W 00000010 XXXXXXXX (Disabled) 2BH 2CH Resource name 2 IBSR0 R 00000000 2 00000000 I C bus status register 0 2DH I C bus control register 0 IBCR0 R/W 2EH I2C bus clock select register 0 ICCR0 R/W 2FH I2C bus address register 0 IADR0 R/W _ XXXXXXX IDAR0 R/W XXXXXXXX 30H 2 I C bus data register 0 I2C interface 0 _ _ 0XXXXX (Disabled) 31H 32H I2C bus status register 1 IBSR1 R 00000000 33H I2C bus control register 1 IBCR1 R/W 00000000 34H I C bus clock select register 1 ICCR1 R/W 2 2 I2C interface 1 _ _ 0XXXXX 35H I C bus address register 1 IADR1 R/W 36H I2C bus data register 1 IDAR1 R/W XXXXXXXX 37H I2C bus port select register ISEL R/W _______0 38H Interrupt/DTP enable register ENIR R/W 00000000 39H Interrupt/DTP factor register EIRR R/W Request level setting register ELVR R/W ADCS0 R/W ADCS1 R/W ADCR0 R/W! ADCR1 R/W 3AH 3BH 3CH 3DH 3EH 3FH Control status register Data register DTP/externalint interrupt _ XXXXXXX XXXXXXXX 00000000 00000000 00000000 A/D convertor 00000000 XXXXXXXX XXXXXXXX (Continued) 22 MB90550A Series Address Register name Abbreviated register name Read/write Resource name Initial value 40H Reload register L (ch.0) PRLL0 R/W XXXXXXXX 41H Reload register H (ch.0) PRLH0 R/W XXXXXXXX 42H Reload register L (ch.1) PRLL1 R/W XXXXXXXX 43H Reload register H (ch.1) PRLH1 R/W XXXXXXXX 44H PPG0 operating mode control register PPGC0 R/W 45H PPG1 operating mode control register PPGC1 R/W 0_000001 46H PPG0 and 1 output control register PPGE1 R/W 00000000 8/16 bit PPG0/1 0_000__1 (Disabled) 47H 48H Reload register L (ch.2) PRLL2 R/W XXXXXXXX 49H Reload register H (ch.2) PRLH2 R/W XXXXXXXX 4AH Reload register L (ch.3) PRLL3 R/W XXXXXXXX 4BH Reload register H (ch.3) PRLH3 R/W XXXXXXXX 4CH PPG2 operating mode control register PPGC2 R/W 4DH PPG3 operating mode control register PPGC3 R/W 0_000001 4EH PPG2 and 3 output control register PPGE2 R/W 00000000 8/16 bit PPG2/3 0_000__1 (Disabled) 4FH 50H Reload register L (ch.4) PRLL4 R/W XXXXXXXX 51H Reload register H (ch.4) PRLH4 R/W XXXXXXXX 52H Reload register L (ch.5) PRLL5 R/W XXXXXXXX 53H Reload register H (ch.5) PRLH5 R/W XXXXXXXX 54H PPG4 operating mode control register PPGC4 R/W 55H PPG5 operating mode control register PPGC5 R/W 0_000001 56H PPG4 and 5 output control register PPGE3 R/W 00000000 59H 0_000__1 (Disabled) 57H 58H 8/16 bit PPG4/5 Clock output enable register CLKR R/W Clock monitor function ____0000 (Disabled) (Continued) 23 MB90550A Series Address 5AH 5BH 5CH 5DH 5EH 5FH 60H 61H 62H Register name Control status register 0 Abbreviated register name Read/write TMCSR0 R/W TMR0/ TMRLR0 R/W Control status register 1 TMCSR1 R/W Input capture register, channel-0 lower bits 63H Input capture register, channel-0 upper bits 64H Input capture register, channel-1 lower bits 65H Input capture register, channel-1 upper bits 66H Input capture register, channel-2 lower bits R/W IPCP0 R ____0000 XXXXXXXX XXXXXXXX 00000000 16 bit reload timer 1 TMR1/ TMRLR1 Initial value 00000000 16 bit reload timer 0 16 bit timer register 0/ 16 bit reload register 0 16 bit timer register 1/ 16 bit reload register 1 Resource name ____0000 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX IPCP1 R XXXXXXXX IPCP2 R 16 bit I/O timer Input capture (ch.0 to ch.3) XXXXXXXX 67H Input capture register, channel-2 upper bits 68H Input capture register, channel-3 lower bits 69H Input capture register, channel-3 upper bits 6AH Input capture control status register ICS01 R/W 00000000 6BH Input capture control status register ICS23 R/W 00000000 6CH Timer data register, lower bits 6DH Timer data register, upper bits 6EH Timer control status register TCCS R/W 6FH ROM mirroring function selection register ROMM W XXXXXXXX XXXXXXXX IPCP3 R XXXXXXXX TCDT R/W R/W 16 bit I/O timer free run timer ROM mirroring function 00000000 00000000 00000000 _______1 (Continued) 24 MB90550A Series Address Register name Abbreviated register name Read/write Resource name Initial value 70H Compare register, channel-0 lower bits 71H Compare register, channel-0 upper bits 72H Compare register, channel-1 lower bits 73H Compare register, channel-1 upper bits 74H Compare register, channel-2 lower bits 75H Compare register, channel-2 upper bits 76H Compare register, channel-3 lower bits 77H Compare register, channel-3 upper bits 78H Compare control status register, channel-0 OCS0 R/W 0000__00 79H Compare control status register, channel-1 OCS1 R/W ___00000 7AH Compare control status register, channel-2 OCS2 R/W 0000__00 7BH Compare control status register, channel-3 OCS3 R/W ___00000 XXXXXXXX OCCP0 R/W XXXXXXXX XXXXXXXX OCCP1 R/W XXXXXXXX XXXXXXXX OCCP2 OCCP3 R/W 16 bit I/O timer output compare (ch.0 to ch.3) XXXXXXXX XXXXXXXX R/W XXXXXXXX 7CH to 9DH (Disabled) PACSR R/W Address match detection function 00000000 Delayed interrupt factor generation/cancellation register DIRR R/W Delayed interrupt _______0 A0H Low-power consumption mode control register LPMCR R/W! A1H Clock select register CKSCR R/W! 9EH Program address detection control register 9FH A2H to A4H Low power 00011000 consumption control 11111100 circuit (Disabled) A5H Automatic ready function select register ARSR W A6H External address output control register HACR W A7H Bus control signal select register ECSR W 0011__00 External bus pin control circuit 00000000 0000000_ (Continued) 25 MB90550A Series Address Register name Abbreviated register name Read/write Resource name Initial value A8H Watchdog timer control register WDTC R/W! Watchdog timer XXXXX 1 1 1 A9H Timebase timer control register TBTC R/W! Timebase timer 1__00100 Flash interface circuit 00000__0 AAH to ADH AEH (Disabled) Flash control status register FMCS R/W (Disabled) AFH B0H Interrupt control register 00 ICR00 R/W! 00000111 B1H Interrupt control register 01 ICR01 R/W! 00000111 B2H Interrupt control register 02 ICR02 R/W! 00000111 B3H Interrupt control register 03 ICR03 R/W! 00000111 B4H Interrupt control register 04 ICR04 R/W! 00000111 B5H Interrupt control register 05 ICR05 R/W! 00000111 B6H Interrupt control register 06 ICR06 R/W! 00000111 B7H Interrupt control register 07 ICR07 R/W! B8H Interrupt control register 08 ICR08 R/W! B9H Interrupt control register 09 ICR09 R/W! 00000111 BAH Interrupt control register 10 ICR10 R/W! 00000111 BBH Interrupt control register 11 ICR11 R/W! 00000111 BCH Interrupt control register 12 ICR12 R/W! 00000111 BDH Interrupt control register 13 ICR13 R/W! 00000111 BEH Interrupt control register 14 ICR14 R/W! 00000111 BFH Interrupt control register 15 ICR15 R/W! 00000111 C0H to FFH (External area) 100H to #H (RAM area) #H to 1FEFH (Reserved area) Interrupt controller 00000111 00000111 (Continued) 26 MB90550A Series (Continued) Address Register name Abbreviated register name Read/write 1FF0H Program address detection register 0 1FF1H Program address detection register 1 1FF2H Program address detection register 2 R/W 1FF3H Program address detection register 3 R/W 1FF4H Program address detection register 4 1FF5H Program address detection register 5 1FF6H to 1FFFH PADR0 PADR1 Resource name Initial value R/W XXXXXXXX R/W XXXXXXXX Address match detection function XXXXXXXX XXXXXXXX R/W XXXXXXXX R/W XXXXXXXX (Reserved area) • Initial value representations 0: Initial value of 0 1: Initial value of 1 X: Initial value undefined –: Initial value undefined (none) • Addresses that follow 00FFH are a reserved area. • The boundary #H between the RAM and reserved areas is different depending on each product. Note : For writable bits, the initial value column contains the initial value to which the bit is initialized at a reset. Notice that it is not the value read from the bit. The LPMCR, CKSCR, and WDTC registers may be initialized or not at a reset, depending on the type of the reset. Their initial values in the above list are those to which the registers are initialized, of course. “R/W!” in the access column indicates that the register contains read-only or write-only bits. If a read-modify-write instruction (such as a bit setting instruction) is used to access a register marked “R/ W!” “R/W*”, or “W” in the access column, the bit focused on by the instruction is set to the desired value but a malfunction occurs if the other bits contains a write-only bit. Do not use such instructions to access those registers. 27 MB90550A Series ■ INTERRUPT FACTORS INTERRUPT VECTORS, INTERRUPT CONTROL REGISTERS Interrupt vectors EI2OS Interrupt source support Number Address Interrupt control registers ICR Address Reset × # 08 FFFFDCH — — INT9 instruction × # 09 FFFFD8H — — Exception × # 10 FFFFD4H — — # 11 FFFFD0H # 12 FFFFCCH ICR00 0000B0H DTP0 (external interrupt 0) # 13 FFFFC8H DTP4/5 (external interrupt 4/5) # 14 FFFFC4H ICR01 0000B1H DTP1 (external interrupt 1) # 15 FFFFC0H # 16 FFFFBCH ICR02 0000B2H # 17 FFFFB8H # 18 FFFFB4H ICR03 0000B3H # 19 FFFFB0H # 20 FFFFACH ICR04 0000B4H # 21 FFFFA8H # 22 FFFFA4H ICR05 0000B5H Extended I/O serial interface 1 # 23 FFFFA0H 16-bit free-run timer (I/O timer) overflow # 24 FFFF9CH ICR06 0000B6H 16-bit re-load timer 0 # 25 FFFF98H DTP6/7 (external interrupt 6/7) # 26 FFFF94H ICR07 0000B7H 16-bit re-load timer 1 # 27 FFFF90H # 28 FFFF8CH ICR08 0000B8H Input capture (ch.0) include (I/O timer) # 29 FFFF88H Input capture (ch.1) include (I/O timer) # 30 FFFF84H ICR09 0000B9H Input capture (ch.2) include (I/O timer) # 31 FFFF80H Input capture (ch.3) include (I/O timer) # 32 FFFF7CH ICR10 0000BAH Output compare (ch.0) match (Output timer) #33 FFFF78H Output compare (ch.1) match (Output timer) # 34 FFFF74H ICR11 0000BBH Output compare (ch.2) match (Output timer) # 35 FFFF70H Output compare (ch.3) match (Output timer) # 36 FFFF6CH ICR12 0000BCH UART0 transmission complete # 37 FFFF68H # 38 FFFF64H ICR13 0000BDH # 39 FFFF60H ICR14 0000BEH ICR15 0000BFH A/D converter Timebase timer 8/16-bit PPG timer0 counter borrow × × DTP2 (external interrupt 2) 8/16-bit PPG timer 1 counter borrow × DTP3 (external interrupt 3) 8/16-bit PPG timer 2 counter borrow × Extended I/O serial interface 0 8/16-bit PPG timer 3 counter borrow 8/16-bit PPG timer 4/5 counter borrow 2 I C interface 0 × × × UART0 reception complete I C interface 1 × # 40 FFFF5CH Flash memory status × # 41 FFFF58H Delayed interrupt generation module × # 42 FFFF54H 2 : The interrupt request flag is cleared by the EI2OS interrupt clear signal. × : The interrupt request flag is not cleared by the EI2OS interrupt clear signal. : The interrupt request flag is cleared by the EI2OS interrupt clear signal. The stop request is available. 28 MB90550A Series Note: On using the EI2OS Function with Extended I/O Serial Interface 2 If a resource has two interrupt sources for the same interrupt number, both of the interrupt request flags are cleared by the EI2OS interrupt clear signal. When the EI2OS function is used for one of the two interrupt sources, therefore, the other interrupt function cannot be used. Set the interrupt request enable bit for the relevant resource to 0 for software polling processing. Interrupt source Interrupt No. Extended I/O serial interface 1 # 23 16-bit free-run timer (I/O timer) overflow # 24 Interrupt control register Resource interrupt request Enabled ICR06 Disabled 29 MB90550A Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings (VSS = AVSS = 0.0 V) Parameter Symbol Value Unit Remarks Min. Max. VCC VSS − 0.3 VSS + 6.0 V AVCC VSS − 0.3 VSS + 6.0 V AVRH VSS − 0.3 VSS + 6.0 V AVRL VSS − 0.3 VSS + 6.0 V Input voltage VI VSS − 0.3 VCC + 0.3 V Output voltage VO VSS − 0.3 VCC + 0.3 V IOL1 10 mA Other than P20 to P27 IOL2 20 mA P20 to P27 IOLAV1 4 mA Other than P20 to P27 IOLAV2 12 mA P20 to P27 ∑IOL 150 mA “L” level total average output current ∑IOLAV 80 mA “H” level maximum output current IOH*2 −15 mA IOHAV*3 −4 mA ∑IOH −100 mA ∑IOHAV*4 −50 mA Power consumption PD 500 mW Operating temperature TA −40 +85 °C TSTG −55 +150 °C Power supply voltage “L” level maximum output current*2 “L” level average output current “L” level total maximum output current “H” level average output current “H” level total maximum output current “H” level total average output current Storage temperature VCC ≥ AVCC *1 AVCC ≥ AVRH ≥ AVRL *5 *5 *5 *1 : Be careful not to let AVcc exceed Vcc, for example, when the power supply is turned on. *2 : The maximum output current is a peak value for a corresponding pin. *3 : Average output current is an average current value observed for a 100 ms period for a corresponding pin. *4 : Total average current is an average current value observed for a 100 ms period for all corresponding pins. *5 : Average output current = operating current × operating efficiency WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 30 MB90550A Series 2. Recommended Operating Conditions (VSS = AVSS = 0.0 V) Parameter Value Symbol Unit Remarks Min. Max. 4.5 5.5 V Normal operation (MB90F553A, MB90P553A, MB90V550A) 3.5 5.5 V Normal operation (MB90553A, MB90552A) 3.5 5.5 V Retains status at the time of operation stop VIH 0.7VCC VCC+0.3 V CMOS input pin*1 VIHS 0.8VCC VCC+0.3 V CMOS hysteresys input pin*2 VIHM VCC − 0.3 VCC+0.3 V MD pin input*3 VIL VSS − 0.3 0.3VCC V CMOS input pin*1 VILS VSS − 0.3 0.2VCC V CMOS hysteresys input pin*2 VILM VSS − 0.3 VSS +0.3 V MD pin input*3 Smoothing capacitor*4 CS 0.1 1.0 µF *5 Operating temperature TA –40 +85 °C Power supply voltage “H” level input voltage “L” level input voltage VCC AVCC *1 : P00 to P07, P10 to P17, P20 to P27, P30 to P37 *2 : X0, HST, RST, P40 to P47, P50 to P55, P60 to P67, P70 to P77, P80 to P87, P90 to P97, PA0 to PA4 *3 : MD0, MD1, MD2 *4 : For connecting smoothing capacitor CS, see the diagram below: *5 : Use a ceramic capacitor or a capacitor with equivqlent frequency characteristics. The smoothing capacitor to be connected to the VCC pin must have a capacitance value higher than CS. • C pin connection circuit C CS VSS AVSS WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 31 MB90550A Series 3. DC Characteristics Parameter Symbol Pin name (VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = –40 °C to +85 °C) Value Condition Unit Remarks Min. Typ. Max. Open-drain output pin voltage VD P50 to P55 “H” level output voltage VOH Other than P50 to P55 VCC = 4.5V, IOH = −4.0mA “L” level output voltage 1 VOL1 Other than P20 to P27 “L” level output voltage 2 VOL2 Input leakage current IIL — VSS – 0.3 — VSS + 6.0 V VCC – 0.5 — — V VCC = 4.5V, IOL = 4.0mA — — 0.4 V P20 to P27 VCC = 4.5V, IOL = 12.0mA — — 0.4 V All output pins VCC = 5.5V, VSS < VI < VCC –5 — 5 µA — 30 40 mA MB90V550A — 80 110 mA MB90P553A — 60 90 mA MB90F553A — 30 40 mA MB90553A — 25 35 mA MB90552A — 100 150 mA MB90F553A — 7 10 mA MB90V550A — 25 30 mA MB90P553A — 10 20 mA MB90F553A — 7 10 mA MB90553A — 7 10 mA MB90552A — 5 20 µA MB90V550A — 0.1 10 µA MB90P553A — 5 20 µA MB90F553A — 5 20 µA MB90553A — 5 20 µA MB90552A Internal operation at 16 MHz VCC = 5.5 V Normal operation ICC When data written in flash mode Power supply current* VCC ICCS Internal operation at 16 MHz VCC = 5.5 V In sleep mode VCC = 5.5V, TA = +25°C In stop mode ICCH Input capacitance CIN Other than AVCC, AVSS, C, VCC and VSS — — 10 — pF Open-drain output leakage current Ileak P50 to P55 — — 0.1 5 µA 25 50 100 kΩ RUP P00 to P07 and P10 to P17 (In pull-up setting),RST Other than MB90V550A 20 40 100 kΩ MB90V550A Pull-up resistance — * : The current value is preliminary value and may be subject to change for enhanced characteristics without previous notice. The power supply current is measured with an external clock. 32 MB90550A Series 4. AC Characteristics (1) Clock Timing Symbol Parameter (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Value Pin name Unit Unit Min. Typ. Max. Oscillation clock frequency FC X0, X1 3 — 16 MHz Oscillation clock cycle time tC X0, X1 62.5 — 333 ns Frequency fluctuation rate locked* ∆f — — — 5 % Input clock pulse width PWH PWL X0 10 — — ns Recommended duty ratio of 40% to 60% Input clock rising/falling time tCR, tCF X0 — — 5 ns External clock operation Internal operating clock frequency FCP — 8.0 — 16 MHz PLL operation 1.5 — 16 MHz When PLL is not used Internal operating clock cycle time tCP — 62.5 — 125 ns PLL operation 62.5 — 666 ns When PLL is not used * :The frequency fluctuation rate is the maximum deviation rate of the preset center frequency when the multiplied PLL signal is locked. + ∆f = α fo +α × 100 (%) Center frequency fo −α − • X0, X1 clock timing tHCYL 0.8 VCC 0.8 VCC 0.8 VCC 0.2 VCC X0 PWH tCF 0.2 VCC PWL tCR 33 MB90550A Series • PLL operation guarantee range Relationship between internal operating clock frequency and power supply voltage Operation guarantee range MB90F553A, MB90P553A, MB90V550A Power supply voltage VCC 5.5 4.5 3.5 PLL Operation guarantee range Operation guarantee range MB90553A, MB90552A 3 1.5 8 12 16 Internal operating clock frequency FCP (MHz) Internal operating clock frequency FCP (MHz) Relationship between oscillation clock frequency and internal operating clock frequency 16 Multiplied- Multipliedby-4 Multiplied-by-2 by-3 Multiplied-by-1 12 9 8 Not multiplied 4 1.5 3 4 8 16 Oscillation clock frequency FC (MHz) The AC ratings are measured for the following measurement reference voltages • Input signal waveform Hystheresis input pin Output pin 0.8 VCC 2.4 V 0.2 VCC 0.8 V Pins other than hystheresis input/MD input 0.7 VCC 0.3 VCC 34 • Output signal waveform MB90550A Series (2) Clock Output Timing Parameter Symbol Cycle time tCYC CLK ↑ → CLK ↓ time tCHCL (VCC = 5.0 V ±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Value Pin name Unit Remarks Min. Max. CLK tCP — ns tCP/2 − 20 tCP/2+20 ns tCYC tCHCL 2.4 V 2.4 V 0.8 V CLK (3) Reset, Hardware Standby Input Timing Parameter Symbol (VCC = 5.0 V ±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Value Pin name Unit Remarks Min. Max. Reset input time tRSTL RST 16 tCP — ns Hardware standby input time tHSTL HST 16 tCP — ns tRSTL, tHSTL RST HST 0.2 VCC 0.2 VCC 35 MB90550A Series (4) Specification for Power-on Reset Parameter Symbol Power supply rising time (VCC = 5.0 V ± 10 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Value Pin name Unit Remarks Min. Max. tR 0.066 30 ms — 0.2 V Power-supply start voltage VOFF Power-supply end voltage VON 3.5 — V Power supply cut-off time tOFF 4 — ms VCC Due to repeated operations tR 3.5 V 0.2 V VCC 0.2 V 0.2 V tOFF Sudden changes in the power supply voltage may cause a power-on reset. To change the power supply voltage while the device is in operation, it is recommended to raise the voltage smoothly to suppress fluctuations as shown below. In this case, change the supply voltage with the PLL clock not used. If the voltage drop is 1 mV or fewer per second, however, you can use the PLL clock. VCC 5.0 V 3.5 V It is recommended to keep the rising speed of the supply voltage at 50 mV/ms or slower. VSS 0V 36 RAM data being held MB90550A Series (5) Bus Read Timing (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Value Pin name Min. Unit Max. ALE pulse width tLHLL ALE tCP/2 − 20 Effective address → ALE ↓ time tAVLL ALE, A23 to A16, AD15 to AD00 tCP/2 − 20 — ns ALE ↓ → address effective time tLLAX ALE, AD15 to AD00 tCP/2 − 15 — ns Effective address → RD ↓ time tAVRL A23 to A16, AD15 to AD00, RD tCP − 15 — ns Effective address → valid data input tAVDV A23 to A16, AD15 to AD00 — 5 tCP/2 − 60 ns RD pulse width tRLRH RD 3 tCP/2 − 20 — ns RD ↓ → valid data input tRLDV RD, AD1 to AD00 — 3 tCP/2 − 60 ns RD ↑ → data hold time tRHDX RD, AD15 to AD00 0 — ns RD ↑ → ALE ↑ time tRHLH RD, ALE tCP/2 − 15 — ns RD ↑ → address effective time tRHAX ALE, A23 to A16 tCP/2 − 10 — ns Effective address → CLK ↑ time tAVCH A23 to A16, AD15 to AD00, CLK tCP/2 − 20 — ns RD ↓ → CLK ↑ time tRLCH RD, CLK tCP/2 − 20 — ns ALE ↓ → RD ↓ time tLLRL ALE, RD tCP/2 − 15 — ns Remarks ns • Bus read timing tAVCH tRLCH 2.4 V 2.4 V CLK tRHLH 2.4 V ALE tLHLL 2.4 V 0.8 V tAVLL tLLAX 2.4 V tRLRH RD tLLRL • Multiplex mode tAVRL A23 to A16 2.4 V 0.8 V tRHAX tRLDV 2.4 V 0.8 V 2.4 V 0.8 V tAVDV AD15 to AD00 2.4 V 0.8 V Address 2.4 V 0.8 V 0.7 VCC 0.3 VCC Read data tRHDX 0.7 VCC 0.3 VCC 37 MB90550A Series (6) Bus Write Timing (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Value Symbol Pin name Effective address → WR ↓ time tAVWL A23 to A16, AD15 to AD00, WRH, WRL WR pulse width tWLWH valid data output→ WR ↑ time Parameter Unit Min. Max. tCP – 15 — ns WRH, WRL 3 tCP/2 – 20 — ns tDVWH AD15 to AD00, WRH, WRL 3 tCP/2 – 20 — ns WR ↑ → data hold time tWHDX AD15 to AD00, WRH, WRL 20 — ns WR ↑ → address effective time tWHAX A23 to A16, WRH, WRL tCP/2 – 10 — ns WR ↑ → ALE ↑ time tWHLH WRH, WRL, ALE tCP/2 – 15 — ns WR ↓ → CLK ↑ time tWLCH WRH, WRL, CLK tCP/2 – 20 — ns Remarks Multiplex mode • Bus write timing tWLCH 2.4 V CLK tWHLH 2.4 V ALE tAVWL WR (WRL, WRH) tWLWH 2.4 V 0.8 V • Multiplex mode A23 to A16 tWHAX 2.4 V 2.4 V 0.8 V 0.8 V tDVWH AD15 to AD00 38 2.4 V 0.8 V Address 2.4 V 0.8 V Write data tWHDX 2.4 V 0.8 V MB90550A Series (7) Ready Input Timing Parameter (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Symbol RDY setup time tRYHS RDY hold time tRYHH Pin name Value Unit Min. Max. 45 — ns 0 — ns RDY CLK Remarks Note : Use the automatic ready function when the setup time for the rising edge of the RDY signal is not sufficient. • Ready input timing 2.4 V CLK ALE WR (WRL, WRH) 0.8 V tRYHS RDY wait not inserted RDY wait inserted (1 cycle) 0.8 VCC tRYHH 0.8 VCC 0.2 VCC 39 MB90550A Series (8) Hold Timing (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Pins in floating status → HAK ↓ time tXHAL HAK ↑ → pin valid time tHAHV Pin name HAK Value Unit Min. Max. 30 tCP ns tCP 2 tCP ns Remarks Note : More than 1 machine cycle is needed before HAK changes after HRQ pin is fetched. • Hold timing HAK tXHAL tHAHV Pins High impedance (9) UART, Extended I/O Sirial 0, 1 Timing (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Symbol Pin name Serial clock cycle time tSCYC SCK0 to SCK2 SCK ↓ → SOT delay time tSLOV Valid SIN → SCK ↑ tIVSH SCK ↑ → valid SIN hold time tSHIX Serial clock “H” pulse width tSHSL Serial clock “L” pulse width tSLSH SCK ↓ → SOT delay time tSLOV Valid SIN → SCK ↑ tIVSH SCK ↑ → valid SIN hold time tSHIX Parameter Condition Unit Min. Max. 8 tCP — ns –80 80 ns 100 — ns tCP — ns SCK0 to SCK2 4 tCP — ns SCK0 to SCK2 4 tCP — ns — 150 ns 60 — ns 60 — ns SCK0 to SCK2, Internal shift clock SOT0 to SOT2 mode SCK0 to SCK2, CL = 80 pF + 1 TTL for an outSIN0 to SIN2 put pin SCK0 to SCK2, SIN0 to SIN2 External shift clock SCK0 to SCK2, mode SOT0 to SOT2 CL = 80 pF + 1 TTL for an SCK0 to SCK2, output pin SIN0 to SIN2 SCK0 to SCK2, SIN0 to SIN2 Notes: • These are AC ratings in the CLK synchronous mode. • CL is the load capacitance value connected to pins while testing. 40 Value Remarks MB90550A Series • Internal shift clock mode tSCYC SCK 2.4 V 0.8 V 0.8 V tSLOV 2.4 V SOT 0.8 V tIVSH SIN tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC • External shift clock mode tSLSH SCK tSHSL 0.8 VCC 0.2 VCC 0.8 VCC 0.2 VCC tSLOV 2.4 V SOT 0.8 V tIVSH SIN tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC (10) Timer Input Timing (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Input pulse width Symbol tTIWH tTIWL Pin name TIN0, TIN1 IN0 to IN3 Value Min. Max. 4 tCP — Unit Remarks ns • Timer input timing 0.8 VCC 0.8 VCC TIN0 to TIN1 IN0 to IN3 0.2 VCC tTIWH 0.2 VCC tTIWL 41 MB90550A Series (11) Timer Output Timing (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Value Symbol Pin name tTO TOT0,TOT1,OUT0, OUT1,PPG0 to PPG5 CLK ↑ → TOUT transition time Min. Max. 30 — Unit Remarks ns • Timer output timing 2.4 V CLK tTO TOT0,TOT1 OUT0,OUT1 PPG0 to PPG5 2.4 V 0.8 V (12) Trigger Input Timing Parameter Input pulse width (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Symbol Pin name tTRGL IRQ0 to IRQ7 Value Min. Max. 5 tCP — Unit ns • Trigger input timing 0.8 VCC 0.8 VCC 0.2 VCC IRQ0 to IRQ7 tTRGH 42 0.2 VCC tTRGL Remarks MB90550A Series (13) I2C Interface Parameter Internal clock cycle time (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Symbol tCP Start condition output tSTAO Stop condition output tSTOO Start condition detection tSTAI Stop condition detection tSTOI SCL output “L” width tLOWO SCL output “H” width tHIGHO SDA output delay time tDOO Setup after SDA output interrupt period tDOSUO SCL input “L” width tLOWI SCL input “H” width tHIGHI SDA input setup time tSUI SDA input hold time tHOI Pin name — SDA0 to SDA2 SCL0 toSCL2 SCL0 to SCL2 SDA0 to SDA2 SCL0 to SCL2 SCL0 to SCL2 SDA0 to SDA2 SCL0 to SCL2 Value Min. Max. 62.5 666 Unit ns tCP × m × n/2 – 20 tCP × m × n/2 + 20 ns tCP (m × n/2 + 4) – 20 tCP (m × n/2 + 4) + 20 ns 3 tCP + 40 — ns 3 tCP + 40 — ns tCP × m × n/2 – 20 tCP × m × n/2 + 20 ns tCP (m × n/2 + 4) – 20 tCP (m × n/2 + 4) + 20 ns 2 tCP – 20 2 tCP + 20 ns 4 tCP – 20 — ns 3 tCP + 40 — ns tCP + 40 — ns 40 — ns 0 — ns Remarks All products Only as master Only as slave Only as master Notes: • “m” and“n” in the above table represent the values of shift clock frequency setting bits (CS4 to CS0) in the clock control register “ICCR”. For details, refer to the register description in the hardware manual. • tDOSUO represents the minimum value when the interrupt period is equal to or greater than the SCL “L” width. • The SDA and SCL output values indicate that that rise time is 0 ns. 43 MB90550A Series • I2C interface [data transmitter (master/slave)] tLOWO tHIGHO 0.8 VCC 0.8 VCC 0.8 VCC 0.8 VCC 0.8 VCC SCL 0.2 VCC 0.2 VCC 8 1 tSTAO tDOO 9 tSUI tDOO SDA tHOI tDOSUO ACK • I2C interface [data receiver (master/slave)] tHIGHI 0.8 VCC tLOWI 0.8 VCC 0.8 VCC SCL 0.2 VCC 6 7 tSUI SDA 44 tHOI 0.2 VCC 8 0.2 VCC 0.2 VCC 9 tDOO tDOO ACK tDOSUO tSTOI MB90550A Series 5. A/D Converter (1)Electrical Characteristics (4.5 V ≤ AVRH − AVRL, VCC = AVCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Pin name Value Min. Typ. Max. Unit Remarks Resolution — — — 10 — bit Total error — — — — ±5.0 LSB Non-linear error — — — — ±2.5 LSB Differential linearity error — — — — ±1.9 LSB Zero transition voltage VOT AN0 to AN7 AVRL− 3.5LSB AVRL+ 0.5LSB AVRL+ 4.5LSB V Full-scale transition voltage VFST AN0 to AN7 AVRH− 6.5LSB AVRH− 1.5LSB AVRH+ 1.5LSB V Sampling period tSMP — 64 — 4096 tCP Compare time tCMP — 22 — — µs *1 A/D Conversion time tCNV — 26.3 — — µs *2 Analog port input current IAIN AN0 to AN7 — — 10 µA Analog input voltage VAIN AN0 to AN7 AVRL — AVRH V — AVRH AVRL — AVCC V — AVRL 0 — AVRH V — 3.5 7.0 mA — — 5 µA — 300 500 µA — — 5 µA — — 4 LSB Reference voltage Power supply current IA IAH IR Reference voltage supply current IRH Offset between channels — AVCC AVRH AN0 to AN7 1LSB= (AVRH−AVRL) /1024 *3 *3 *1: When FCP = 8 MHz, tCMP = 176 × tCP. When FCP = 16 MHz, tCMP = 352 × tCP. *2:Equivalent to the time for conversion per channel if “tSMP = 64 × tCP” or “tCMP = 352 × tCP” is selected when FCP = 16 MHz. *3:Specifies the power-supply current (Vcc = AVcc = AVRH = 5.0 V) when the A/D converter is inactive and the CPU has been stopped. Notes: • The error becomes larger relatively as |AVRH-AVRL| becomes smaller. • Use the output impedance rS of the external circuit for analog input under the following condition: External circuit output impedance rS = 10 kΩ max. • If the output impedance of the external circuit is too high, the analog voltage sampling time may be insufficient. • If you insert a DC-blocking capacitor between the external circuit and the input pin, select the capacitance about several thousands times the sampling capacitance CSH in the chip to suppress the effect of capacity potential division with CSH. 45 MB90550A Series • Analog input circuit model Microcontroller internal circuit Input pin AN0 rS RSH CSH Input pin AN7 VS External circuit to Comparator S/H circuit Analog channel selector <Recommended/reference values for device parameters> rS = 10 kΩ or less RSH = About 3 kΩ CSH = About 25 pF Note: Device parameter values are provided as reference values for design purposes; they are not guaranteed. 46 MB90550A Series (2) Definitions of Terms • Resolution: Analog transition identifiable by the A/D converter. Analog voltage can be divided into 1024 (210) components at 10-bit resolution. • Total error: Difference between actual and logical values. This error is the sum of an offset error, gain error, non-linearity error, and an error caused by noise. • Linearity error: Deviation of the straight line drawn between the zero transition point (00 0000 0000 <-> 00 0000 0001) and the full-scale transition point (11 1111 1110 <-> 11 1111 1111) of the device from actual conversion characteristics • Differential linearity error: Deviation from the ideal input voltage required to shift output code by one LSB • 10-bit A/D converter conversion characteristics 11 11 11 11 1111 1111 1111 1111 1111 1110 1101 1100 • • 1LSB × N + VOT • Digital output • • • • • • Linearity error • • • • 00 0000 0011 00 0000 0010 00 0000 0001 00 0000 0000 VOT VNT V(N + 1)T VFST Analog input VFST − VOT 1022 VNT − (1LSB × N + VOT) Linearity error = [ LSB ] 1LSB V (N + 1) T − VNT − 1 [ LSB ] Differential linearity error = 1LSB 1LSB = 47 MB90550A Series ■ EXAMPLE CHARACTERISTICS 1. “L” level output voltage VOL − IOL Other than P20 to P27 700 600 VOL (mV) 500 400 300 200 100 0 0 2 4 6 8 10 IOL (mA) VOL − IOL P20 to P27 700 TA = 25 °C VCC = 3.5 V 600 VCC = 4.0 V VOL (mV) 500 VCC = 5.0 V VCC = 6.0 V 400 300 200 100 0 0 5 10 15 IOL (mA) 48 20 25 30 MB90550A Series 2. “H” level output voltage (VCC − VOH) − IOH Other than P50 to P55 700 TA = 25 °C 600 VCC = 3.5 V VCC − VOH (mV) 500 VCC = 4.0 V VCC = 5.0 V 400 VCC = 6.0 V 300 200 100 0 −2 0 −4 −6 −8 −10 IOH (mA) 3. “H” level input voltage / “L” level input voltage (CMOS input) VIH / VIL − VCC 5 4.5 TA = 25 °C 4 VIH/VIL (V) 3.5 3 2.5 2 1.5 1 1.5 0 3.5 4 4.5 5 5.5 VCC (V) 49 MB90550A Series 4. “H” level input voltage / “L” level input voltage (CMOS hysteresis input) VIHS / VILS − VCC 5 4.5 TA = 25 °C 4 VIHS/VILS (V) 3.5 VIHS 3 2.5 2 VIHL 1.5 1 1.5 0 3.5 4 4.5 VCC (V) 50 5 5.5 MB90550A Series 5. Power supply current (FCP = internal operating clock frequency) • MB90552A • Measurement conditions : External clock mode, ROM read loop operation, without resource operation, Typ. sample, internal operating frequency = 4MHz (external rectangular wave clock at 8MHz), TA = 25 °C ICC − VCC 30 TA = 25 °C FCP = 16 MHz 25 ICC (mA) 20 FCP = 10.6 MHz 15 FCP = 8 MHz 10 FCP = 4 MHz 5 0 3.5 4 4.5 5 5.5 VCC (V) ICCS − VCC 10 9 TA = 25 °C FCP = 16 MHz 8 ICCS (mA) 7 FCP = 10.6 MHz 6 5 FCP = 8 MHz 4 3 FCP = 4 MHz 2 1 0 3.5 4 4.5 5 5.5 VCC (V) 51 MB90550A Series • MB90F553A • Measurement conditions : External clock mode, ROM read loop operation, without resource operation, Typ. sample, internal operating frequency = 4MHz (external rectangular wave clock at 8MHz), TA = 25 °C ICC − VCC 70 TA = 25 °C 60 FCP = 16 MHz ICC (mA) 50 40 FCP = 10 MHz 30 FCP = 4 MHz 20 10 4.5 5 5.5 VCC (V) ICCS − VCC 12 TA = 25 °C 10 FCP = 16 MHz ICCS (mA) 8 FCP = 10 MHz 6 4 FCP = 4MHz 2 0 4.5 5 VCC (V) 52 5.5 MB90550A Series 6. Pull-up resistance Pull-up resistance − VCC 90 Pull-up resistance (kΩ) 80 TA = 85 °C 70 TA = 25 °C 60 TA = −40 °C 50 40 30 20 10 4 4.5 5 5.5 VCC (V) 53 MB90550A Series ■ INSTRUCTIONS (340 INSTRUCTIONS) Table 1 Item Mnemonic # ~ RG B Operation LH AH I S T N Z V C RMW Explanation of Items in Tables of Instructions Meaning Upper-case letters and symbols: Represented as they appear in assembler. Lower-case letters: Replaced when described in assembler. Numbers after lower-case letters: Indicate the bit width within the instruction code. Indicates the number of bytes. Indicates the number of cycles. m : When branching n : When not branching See Table 4 for details about meanings of other letters in items. Indicates the number of accesses to the register during execution of the instruction. It is used calculate a correction value for intermittent operation of CPU. Indicates the correction value for calculating the number of actual cycles during execution of the instruction. (Table 5) The number of actual cycles during execution of the instruction is the correction value summed with the value in the “~” column. Indicates the operation of instruction. Indicates special operations involving the upper 8 bits of the lower 16 bits of the accumulator. Z : Transfers “0”. X : Extends with a sign before transferring. – : Transfers nothing. Indicates special operations involving the upper 16 bits in the accumulator. * : Transfers from AL to AH. – : No transfer. Z : Transfers 00H to AH. X : Transfers 00H or FFH to AH by signing and extending AL. Indicates the status of each of the following flags: I (interrupt enable), S (stack), T (sticky bit), N (negative), Z (zero), V (overflow), and C (carry). * : Changes due to execution of instruction. – : No change. S : Set by execution of instruction. R : Reset by execution of instruction. Indicates whether the instruction is a read-modify-write instruction. (a single instruction that reads data from memory, etc., processes the data, and then writes the result to memory.) * : Instruction is a read-modify-write instruction. – : Instruction is not a read-modify-write instruction. Note: A read-modify-write instruction cannot be used on addresses that have different meanings depending on whether they are read or written. • Number of execution cycles The number of cycles required for instruction execution is acquired by adding the number of cycles for each instruction, a corrective value depending on the condition, and the number of cycles required for program fetch. Whenever the instruction being executed exceeds the two-byte (word) boundary, a program on an internal ROM connected to a 16-bit bus is fetched. If data access is interfered with, therefore, the number of execution cycles is increased. For each byte of the instruction being executed, a program on a memory connected to an 8-bit external data bus is fetched. If data access in interfered with, therefore, the number of execution cycles is increased. When a general-purpose register, an internal ROM, an internal RAM, an internal I/O device, or an external bus is accessed during intermittent CPU operation, the CPU clock is suspended by the number of cycles specified by the CG1/0 bit of the low-power consumption mode control register. When determining the number of cycles required for instruction execution during intermittent CPU operation, therefore, add the value of the number of times access is done × the number of cycles suspended as the corrective value to the number of ordinary execution cycles. 54 MB90550A Series Table 2 Explanation of Symbols in Tables of Instructions Symbol A Meaning 32-bit accumulator The bit length varies according to the instruction. Byte : Lower 8 bits of AL Word : 16 bits of AL Long : 32 bits of AL and AH AH AL Upper 16 bits of A Lower 16 bits of A SP Stack pointer (USP or SSP) PC Program counter PCB Program bank register DTB Data bank register ADB Additional data bank register SSB System stack bank register USB User stack bank register SPB Current stack bank register (SSB or USB) DPR Direct page register brg1 DTB, ADB, SSB, USB, DPR, PCB, SPB brg2 DTB, ADB, SSB, USB, DPR, SPB Ri R0, R1, R2, R3, R4, R5, R6, R7 RWi RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7 RWj RW0, RW1, RW2, RW3 RLi RL0, RL1, RL2, RL3 dir Compact direct addressing addr16 addr24 ad24 0 to 15 ad24 16 to 23 Direct addressing Physical direct addressing Bit 0 to bit 15 of addr24 Bit 16 to bit 23 of addr24 io imm4 imm8 imm16 imm32 ext (imm8) disp8 disp16 bp I/O area (000000H to 0000FFH) 4-bit immediate data 8-bit immediate data 16-bit immediate data 32-bit immediate data 16-bit data signed and extended from 8-bit immediate data 8-bit displacement 16-bit displacement Bit offset vct4 vct8 Vector number (0 to 15) Vector number (0 to 255) ( )b Bit address rel ear eam rlst PC relative addressing Effective addressing (codes 00 to 07) Effective addressing (codes 08 to 1F) Register list 55 MB90550A Series Table 3 Code 00 01 02 03 04 05 06 07 Notation R0 R1 R2 R3 R4 R5 R6 R7 RW0 RW1 RW2 RW3 RW4 RW5 RW6 RW7 Effective Address Fields Address format RL0 (RL0) RL1 (RL1) RL2 (RL2) RL3 (RL3) Number of bytes in address extension * Register direct “ea” corresponds to byte, word, and long-word types, starting from the left 08 09 0A 0B @RW0 @RW1 @RW2 @RW3 Register indirect 0C 0D 0E 0F @RW0 + @RW1 + @RW2 + @RW3 + Register indirect with post-increment 10 11 12 13 14 15 16 17 @RW0 + disp8 @RW1 + disp8 @RW2 + disp8 @RW3 + disp8 @RW4 + disp8 @RW5 + disp8 @RW6 + disp8 @RW7 + disp8 Register indirect with 8-bit displacement 18 19 1A 1B @RW0 + disp16 @RW1 + disp16 @RW2 + disp16 @RW3 + disp16 Register indirect with 16-bit displacement 1C 1D 1E 1F @RW0 + RW7 @RW1 + RW7 @PC + disp16 addr16 Register indirect with index Register indirect with index PC indirect with 16-bit displacement Direct address — 0 0 1 2 0 0 2 2 Note : The number of bytes in the address extension is indicated by the “+” symbol in the “#” (number of bytes) column in the tables of instructions. 56 MB90550A Series Table 4 Number of Execution Cycles for Each Type of Addressing (a) Code Operand Number of execution cycles for each type of addressing Number of register accesses for each type of addressing 00 to 07 Ri RWi RLi 08 to 0B @RWj 2 1 0C to 0F @RWj + 4 2 10 to 17 @RWi + disp8 2 1 18 to 1B @RWj + disp16 2 1 1C 1D 1E 1F @RW0 + RW7 @RW1 + RW7 @PC + disp16 addr16 4 4 2 1 2 2 0 0 Listed in tables of instructions Listed in tables of instructions Note : “(a)” is used in the “~” (number of states) column and column B (correction value) in the tables of instructions. Table 5 Compensation Values for Number of Cycles Used to Calculate Number of Actual Cycles Operand (b) byte (c) word (d) long Cycles Access Cycles Access Cycles Access Internal register +0 1 +0 1 +0 2 Internal memory even address Internal memory odd address +0 +0 1 1 +0 +2 1 2 +0 +4 2 4 Even address on external data bus (16 bits) Odd address on external data bus (16 bits) +1 +1 1 1 +1 +4 1 2 +2 +8 2 4 External data bus (8 bits) +1 1 +4 2 +8 4 Notes: • “(b)”, “(c)”, and “(d)” are used in the “~” (number of states) column and column B (correction value) in the tables of instructions. • When the external data bus is used, it is necessary to add in the number of wait cycles used for ready input and automatic ready. Table 6 Correction Values for Number of Cycles Used to Calculate Number of Program Fetch Cycles Instruction Byte boundary Word boundary Internal memory — +2 External data bus (16 bits) — +3 External data bus (8 bits) +3 — Notes: • When the external data bus is used, it is necessary to add in the number of wait cycles used for ready input and automatic ready. • Because instruction execution is not slowed down by all program fetches in actuality, these correction values should be used for “worst case” calculations. 57 MB90550A Series Table 7 Mnemonic # Transfer Instructions (Byte) [41 Instructions] ~ RG B Operation LH AH I S T N Z V C RMW MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVN A, dir A, addr16 A, Ri A, ear A, eam A, io A, #imm8 A, @A A, @RLi+disp8 A, #imm4 3 2 4 3 2 1 2 2 2+ 3+ (a) 3 2 2 2 3 2 10 3 1 1 0 0 1 1 0 0 0 0 2 0 (b) (b) 0 0 (b) (b) 0 (b) (b) 0 byte (A) ← (dir) byte (A) ← (addr16) byte (A) ← (Ri) byte (A) ← (ear) byte (A) ← (eam) byte (A) ← (io) byte (A) ← imm8 byte (A) ← ((A)) byte (A) ← ((RLi)+disp8) byte (A) ← imm4 Z Z Z Z Z Z Z Z Z Z * * * * * * * – * * – – – – – – – – – – – – – – – – – – – – – * – * – * – * – * – * – * – * – * – R * * * * * * * * * * – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX A, dir A, addr16 A, Ri A, ear A, eam A, io A, #imm8 A, @A A,@RWi+disp8 A, @RLi+disp8 3 2 4 3 2 2 2 2 2+ 3+ (a) 3 2 2 2 3 2 5 2 10 3 0 0 1 1 0 0 0 0 1 2 (b) (b) 0 0 (b) (b) 0 (b) (b) (b) byte (A) ← (dir) byte (A) ← (addr16) byte (A) ← (Ri) byte (A) ← (ear) byte (A) ← (eam) byte (A) ← (io) byte (A) ← imm8 byte (A) ← ((A)) byte (A) ← ((RWi)+disp8) byte (A) ← ((RLi)+disp8) X * X * X * X * X * X * X * X – X * X * – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * * * * * * * * * – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV /MOV dir, A addr16, A Ri, A ear, A eam, A io, A @RLi+disp8, A Ri, ear Ri, eam ear, Ri eam, Ri Ri, #imm8 io, #imm8 dir, #imm8 ear, #imm8 eam, #imm8 @AL, AH @A, T 2 3 1 2 2+ 2 3 2 2+ 2 2+ 2 3 3 3 3+ 3 4 2 2 3+ (a) 3 10 3 4+ (a) 4 5+ (a) 2 5 5 2 4+ (a) 0 0 1 1 0 0 2 2 1 2 1 1 0 0 1 0 (b) (b) 0 0 (b) (b) (b) 0 (b) 0 (b) 0 (b) (b) 0 (b) byte (dir) ← (A) byte (addr16) ← (A) byte (Ri) ← (A) byte (ear) ← (A) byte (eam) ← (A) byte (io) ← (A) byte ((RLi) +disp8) ← (A) byte (Ri) ← (ear) byte (Ri) ← (eam) byte (ear) ← (Ri) byte (eam) ← (Ri) byte (Ri) ← imm8 byte (io) ← imm8 byte (dir) ← imm8 byte (ear) ← imm8 byte (eam) ← imm8 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * – – * – * * * * * * * * * * * * – – * – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – 2 3 0 (b) byte ((A)) ← (AH) – – – – – * * – – – XCH XCH XCH XCH A, ear A, eam Ri, ear Ri, eam 4 2 2+ 5+ (a) 7 2 2+ 9+ (a) 2 0 4 2 0 2× (b) 0 2× (b) byte (A) ↔ (ear) byte (A) ↔ (eam) byte (Ri) ↔ (ear) byte (Ri) ↔ (eam) Z Z – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 58 MB90550A Series Table 8 Transfer Instructions (Word/Long Word) [38 Instructions] RG B 2 3 3 4 1 1 1 2 2 2 2+ 3+ (a) 2 3 2 3 3 2 2 5 3 10 0 0 0 1 1 0 0 0 0 1 2 (c) (c) 0 0 0 (c) (c) (c) 0 (c) (c) word (A) ← (dir) word (A) ← (addr16) word (A) ← (SP) word (A) ← (RWi) word (A) ← (ear) word (A) ← (eam) word (A) ← (io) word (A) ← ((A)) word (A) ← imm16 – – – – – – – – – word (A) ← ((RWi) +disp8) – word (A) ← ((RLi) +disp8) – MOVW dir, A MOVW addr16, A MOVW SP, A MOVW RWi, A MOVW ear, A MOVW eam, A MOVW io, A MOVW @RWi+disp8, A MOVW @RLi+disp8, A MOVW RWi, ear MOVW RWi, eam MOVW ear, RWi MOVW eam, RWi MOVW RWi, #imm16 MOVW io, #imm16 MOVW ear, #imm16 MOVW eam, #imm16 MOVW @AL, AH /MOVW@A, T 2 3 1 1 2 2+ 2 2 3 2 2+ 2 2+ 3 4 4 4+ 3 4 1 2 2 3+ (a) 3 5 10 3 4+ (a) 4 5+ (a) 2 5 2 4+ (a) 0 0 0 1 1 0 0 1 2 2 1 2 1 1 0 1 0 (c) (c) 0 0 0 (c) (c) (c) (c) (0) (c) 0 (c) 0 (c) 0 (c) word (dir) ← (A) word (addr16) ← (A) word (SP) ← (A) word (RWi) ← (A) word (ear) ← (A) word (eam) ← (A) word (io) ← (A) 2 3 0 (c) XCHW XCHW XCHW XCHW 2 4 2+ 5+ (a) 2 7 2+ 9+ (a) MOVL A, ear MOVL A, eam MOVL A, #imm32 MOVL ear, A MOVL eam, A Mnemonic MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW A, dir A, addr16 A, SP A, RWi A, ear A, eam A, io A, @A A, #imm16 A, @RWi+disp8 A, @RLi+disp8 A, ear A, eam RWi, ear RWi, eam # ~ Operation LH AH I S T N Z V C RMW * * * * * * * – * * * – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * * * * * * * * * * * – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – word ((RWi) +disp8) ← (A) – word ((RLi) +disp8) ← (A) – word (RWi) ← (ear) – word (RWi) ← (eam) – word (ear) ← (RWi) – word (eam) ← (RWi) – word (RWi) ← imm16 – word (io) ← imm16 – word (ear) ← imm16 – word (eam) ← imm16 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * * * – * – * * * * * * * * * * * * * * – * – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – word ((A)) ← (AH) – – – – – * * – – – 2 0 0 2× (c) 4 0 2 2× (c) word (A) ↔ (ear) word (A) ↔ (eam) word (RWi) ↔ (ear) word (RWi) ↔ (eam) – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – 2 4 2+ 5+ (a) 5 3 2 0 0 0 (d) 0 long (A) ← (ear) long (A) ← (eam) long (A) ← imm32 – – – – – – – – – – – – – – – * * * * * * – – – – – – – – – 2 4 2+ 5+ (a) 2 0 0 (d) long (ear) ← (A) long (eam) ← (A) – – – – – – – – – – * * * * – – – – – – Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 59 MB90550A Series Table 9 Addition and Subtraction Instructions (Byte/Word/Long Word) [42 Instructions] # ~ RG B Operation 2 2 2 2+ 2 2+ 1 2 2+ 1 2 2 2 2+ 2 2+ 1 2 2+ 1 2 5 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 2 5 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 0 0 1 0 2 0 0 1 0 0 0 0 1 0 2 0 0 1 0 0 0 (b) 0 (b) 0 2× (b) 0 0 (b) 0 0 (b) 0 (b) 0 2× (b) 0 0 (b) 0 byte (A) ← (A) +imm8 byte (A) ← (A) +(dir) byte (A) ← (A) +(ear) byte (A) ← (A) +(eam) byte (ear) ← (ear) + (A) byte (eam) ← (eam) + (A) byte (A) ← (AH) + (AL) + (C) byte (A) ← (A) + (ear) + (C) byte (A) ← (A) + (eam) + (C) Z Z Z Z – Z Z Z Z byte (A) ← (AH) + (AL) + (C) (decimal) Z Z byte (A) ← (A) –imm8 Z byte (A) ← (A) – (dir) Z byte (A) ← (A) – (ear) Z byte (A) ← (A) – (eam) – byte (ear) ← (ear) – (A) – byte (eam) ← (eam) – (A) byte (A) ← (AH) – (AL) – (C) Z byte (A) ← (A) – (ear) – (C) Z byte (A) ← (A) – (eam) – (C) Z byte (A) ← (AH) – (AL) – (C) (decimal) Z 1 2 2+ 3 2 2+ 2 2+ 1 2 2+ 3 2 2+ 2 2+ 2 3 4+ (a) 2 3 5+ (a) 3 4+ (a) 2 3 4+ (a) 2 3 5+ (a) 3 4+ (a) 0 1 0 0 2 0 1 0 0 1 0 0 2 0 1 0 0 0 (c) 0 0 2× (c) 0 (c) 0 0 (c) 0 0 2× (c) 0 (c) word (A) ← (AH) + (AL) word (A) ← (A) +(ear) word (A) ← (A) +(eam) word (A) ← (A) +imm16 word (ear) ← (ear) + (A) word (eam) ← (eam) + (A) word (A) ← (A) + (ear) + (C) word (A) ← (A) + (eam) + (C) word (A) ← (AH) – (AL) word (A) ← (A) – (ear) word (A) ← (A) – (eam) word (A) ← (A) –imm16 word (ear) ← (ear) – (A) word (eam) ← (eam) – (A) word (A) ← (A) – (ear) – (C) word (A) ← (A) – (eam) – (C) A, ear 2 6 A, eam 2+ 7+ (a) A, #imm32 5 4 A, ear 2 6 A, eam 2+ 7+ (a) A, #imm32 5 4 2 0 0 2 0 0 0 (d) 0 0 (d) 0 long (A) ← (A) + (ear) long (A) ← (A) + (eam) long (A) ← (A) +imm32 long (A) ← (A) – (ear) long (A) ← (A) – (eam) long (A) ← (A) –imm32 Mnemonic ADD ADD ADD ADD ADD ADD ADDC ADDC ADDC ADDDC SUB SUB SUB SUB SUB SUB SUBC SUBC SUBC SUBDC A,#imm8 A, dir A, ear A, eam ear, A eam, A A A, ear A, eam A A, #imm8 A, dir A, ear A, eam ear, A eam, A A A, ear A, eam A ADDW A ADDW A, ear ADDW A, eam ADDW A, #imm16 ADDW ear, A ADDW eam, A ADDCW A, ear ADDCW A, eam SUBW A SUBW A, ear SUBW A, eam SUBW A, #imm16 SUBW ear, A SUBW eam, A SUBCW A, ear SUBCW A, eam ADDL ADDL ADDL SUBL SUBL SUBL LH AH I S T N Z V C RMW – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * – – – – – * – – – – – – – – – * – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * – – – – – * – – – – – – – * – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * * * * * * * * * * * * * – – – – – – Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 60 MB90550A Series Table 10 Mnemonic Increment and Decrement Instructions (Byte/Word/Long Word) [12 Instructions] # ~ RG B Operation LH AH I S T N Z V C RMW INC INC ear eam 2 2 2+ 5+ (a) 2 0 0 byte (ear) ← (ear) +1 2× (b) byte (eam) ← (eam) +1 – – – – – – – – – – * * * * * * – – – * DEC DEC ear eam 2 3 2+ 5+ (a) 2 0 0 byte (ear) ← (ear) –1 2× (b) byte (eam) ← (eam) –1 – – – – – – – – – – * * * * * * – – – * INCW INCW ear eam 2 3 2+ 5+ (a) 2 0 0 word (ear) ← (ear) +1 2× (c) word (eam) ← (eam) +1 – – – – – – – – – – * * * * * * – – – * DECW ear DECW eam 2 3 2+ 5+ (a) 2 0 0 word (ear) ← (ear) –1 2× (c) word (eam) ← (eam) –1 – – – – – – – – – – * * * * * * – – – * INCL INCL ear eam 2 7 2+ 9+ (a) 4 0 0 long (ear) ← (ear) +1 2× (d) long (eam) ← (eam) +1 – – – – – – – – – – * * * * * * – – – * DECL DECL ear eam 2 7 2+ 9+ (a) 4 0 0 long (ear) ← (ear) –1 2× (d) long (eam) ← (eam) –1 – – – – – – – – – – * * * * * * – – – * Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” Table 11 Mnemonic Compare Instructions (Byte/Word/Long Word) [11 Instructions] # ~ RG B Operation LH AH I S T N Z V C RMW CMP CMP CMP CMP A A, ear A, eam A, #imm8 1 2 2+ 2 1 2 3+ (a) 2 0 1 0 0 0 0 (b) 0 byte (AH) – (AL) byte (A) ← (ear) byte (A) ← (eam) byte (A) ← imm8 – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * * * * * – – – – CMPW CMPW CMPW CMPW A 1 A, ear 2 A, eam 2+ A, #imm16 3 1 2 3+ (a) 2 0 1 0 0 0 0 (c) 0 word (AH) – (AL) word (A) ← (ear) word (A) ← (eam) word (A) ← imm16 – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * * * * * – – – – CMPL CMPL CMPL A, ear 2 A, eam 2+ A, #imm32 5 6 7+ (a) 3 2 0 0 0 (d) 0 word (A) ← (ear) word (A) ← (eam) word (A) ← imm32 – – – – – – – – – – – – – – – * * * * * * * * * * * * – – – Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 61 MB90550A Series Table 12 Mnemonic Multiplication and Division Instructions (Byte/Word/Long Word) [11 Instructions] # ~ 1 RG B Operation LH AH I S T N Z V C RMW DIVU A 1 * 0 0 word (AH) /byte (AL) – – – – – – – * * – DIVU A, ear 2 *2 1 0 word (A)/byte (ear) – – – – – – – * * – DIVU A, eam 2+ *3 0 *6 word (A)/byte (eam) – – – – – – – * * – *4 1 0 long (A)/word (ear) – – – – – – – * * – DIVUW A, eam 2+ *5 0 *7 long (A)/word (eam) – – – – – – – * * – MULU MULU MULU 0 0 byte (AH) *byte (AL) → word (A) 1 0 byte (A) *byte (ear) → word (A) 0 (b) byte (A) *byte (eam) → word (A) – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – 0 0 word (AH) *word (AL) → long (A) 1 0 word (A) *word (ear) → long (A) 0 (c) word (A) *word (eam) → long (A) – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – DIVUW A, ear 2 A 1 *8 A, ear 2 *9 A, eam 2+ *10 MULUW A 1 *11 MULUW A, ear 2 *12 MULUW A, eam 2+ *13 *1: *2: *3: *4: *5: *6: *7: *8: *9: *10: *11: *12: *13: Quotient → byte (AL) Remainder → byte (AH) Quotient → byte (A) Remainder → byte (ear) Quotient → byte (A) Remainder → byte (eam) Quotient → word (A) Remainder → word (ear) Quotient → word (A) Remainder → word (ear) 3 when the result is zero, 7 when an overflow occurs, and 15 normally. 4 when the result is zero, 8 when an overflow occurs, and 16 normally. 6 + (a) when the result is zero, 9 + (a) when an overflow occurs, and 19 + (a) normally. 4 when the result is zero, 7 when an overflow occurs, and 22 normally. 6 + (a) when the result is zero, 8 + (a) when an overflow occurs, and 26 + (a) normally. (b) when the result is zero or when an overflow occurs, and 2 × (b) normally. (c) when the result is zero or when an overflow occurs, and 2 × (c) normally. 3 when byte (AH) is zero, and 7 when byte (AH) is not zero. 4 when byte (ear) is zero, and 8 when byte (ear) is not zero. 5 + (a) when byte (eam) is zero, and 9 + (a) when byte (eam) is not 0. 3 when word (AH) is zero, and 11 when word (AH) is not zero. 4 when word (ear) is zero, and 12 when word (ear) is not zero. 5 + (a) when word (eam) is zero, and 13 + (a) when word (eam) is not zero. Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 62 MB90550A Series Table 13 Signed Multiplication and Division Instructions (Byte/Word/Long Word) [11 Instructions] Mnemonic # ~ RG B 0 DIV A 2 *1 0 DIV A, ear 2 *2 1 DIV A, eam 2 + *3 0 DIVW A, ear 2 *4 1 DIVW A, eam 2+ *5 0 MULU MULU MULU MULUW MULUW MULUW A 2 A, ear 2 A, eam 2 + A 2 A, ear 2 A, eam 2 + *8 *9 *10 *11 *12 *13 0 1 0 0 1 0 Operation word (AH) /byte (AL) Quotient → byte (AL) Remainder → byte (AH) 0 word (A)/byte (ear) Quotient → byte (A) Remainder → byte (ear) *6 word (A)/byte (eam) Quotient → byte (A) Remainder → byte (eam) 0 long (A)/word (ear) Quotient → word (A) Remainder → word (ear) *7 long (A)/word (eam) Quotient → word (A) Remainder → word (eam) 0 0 (b) 0 0 (c) byte (AH) *byte (AL) → word (A) byte (A) *byte (ear) → word (A) byte (A) *byte (eam) → word (A) word (AH) *word (AL) → long (A) word (A) *word (ear) → long (A) word (A) *word (eam) → long (A) LH AH I S T N Z V C RMW Z – – – – – – * * – Z – – – – – – * * – Z – – – – – – * * – – – – – – – – * * – – – – – – – – * * – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – *1: *2: *3: *4: Set to 3 when the division-by-0, 8 or 18 for an overflow, and 18 for normal operation. Set to 3 when the division-by-0, 10 or 21 for an overflow, and 22 for normal operation. Set to 4 + (a) when the division-by-0, 11 + (a) or 22 + (a) for an overflow, and 23 + (a) for normal operation. Positive dividend: Set to 4 when the division-by-0, 10 or 29 for an overflow, and 30 for normal operation. Negative dividend: Set to 4 when the division-by-0, 11 or 30 for an overflow and 31 for normal operation. *5: Positive dividend: Set to 4 + (a) when the division-by-0, 11 + (a) or 30 + (a) for an overflow, and 31 + (a) for normal operation. Negative dividend: Set to 4 + (a) when the division-by-0, 12 + (a) or 31 + (a) for an overflow, and 32 + (a) for normal operation. *6: When the division-by-0, (b) for an overflow, and 2 × (b) for normal operation. *7: When the division-by-0, (c) for an overflow, and 2 × (c) for normal operation. *8: Set to 3 when byte (AH) is zero, 12 when the result is positive, and 13 when the result is negative. *9: Set to 3 when byte (ear) is zero, 12 when the result is positive, and 13 when the result is negative. *10: Set to 4 + (a) when byte (eam) is zero, 13 + (a) when the result is positive, and 14 + (a) when the result is negative. *11: Set to 3 when word (AH) is zero, 12 when the result is positive, and 13 when the result is negative. *12: Set to 3 when word (ear) is zero, 16 when the result is positive, and 19 when the result is negative. *13: Set to 4 + (a) when word (eam) is zero, 17 + (a) when the result is positive, and 20 + (a) when the result is negative. Notes: • When overflow occurs during DIV or DIVW instruction execution, the number of execution cycles takes two values because of detection before and after an operation. • When overflow occurs during DIV or DIVW instruction execution, the contents of AL are destroyed. • For (a) to (d), refer to “Table 4 Number of Execution Cycles for Effective Address in Addressing Modes” and “Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles.” 63 MB90550A Series Table 14 Mnemonic # ~ Logical 1 Instructions (Byte/Word) [39 Instructions] RG B Operation LH AH I S T N Z V C RMW AND AND AND AND AND A, #imm8 A, ear A, eam ear, A eam, A 2 2 2 3 2+ 4+ (a) 2 3 2+ 5+ (a) 0 1 0 2 0 0 0 (b) 0 2× (b) byte (A) ← (A) and imm8 byte (A) ← (A) and (ear) byte (A) ← (A) and (eam) byte (ear) ← (ear) and (A) byte (eam) ← (eam) and (A) – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * R R R R R – – – – – – – – – * OR OR OR OR OR A, #imm8 A, ear A, eam ear, A eam, A 2 2 2 3 2+ 4+ (a) 2 3 2+ 5+ (a) 0 1 0 2 0 0 0 (b) 0 2× (b) byte (A) ← (A) or imm8 byte (A) ← (A) or (ear) byte (A) ← (A) or (eam) byte (ear) ← (ear) or (A) byte (eam) ← (eam) or (A) – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * R R R R R – – – – – – – – – * XOR XOR XOR XOR XOR A, #imm8 A, ear A, eam ear, A eam, A 2 2 2 3 2+ 4+ (a) 2 3 2+ 5+ (a) 0 1 0 2 0 0 0 (b) 0 2× (b) byte (A) ← (A) xor imm8 byte (A) ← (A) xor (ear) byte (A) ← (A) xor (eam) byte (ear) ← (ear) xor (A) byte (eam) ← (eam) xor (A) – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * R R R R R – – – – – – – – – * NOT NOT NOT A ear eam 1 2 2 3 2+ 5+ (a) 0 2 0 0 byte (A) ← not (A) 0 byte (ear) ← not (ear) 2× (b) byte (eam) ← not (eam) – – – – – – – – – – – – – – – * * * * * * R R R – – – – – * ANDW ANDW ANDW ANDW ANDW ANDW A 1 2 A, #imm16 3 2 A, ear 2 3 A, eam 2+ 4+ (a) ear, A 2 3 eam, A 2+ 5+ (a) 0 0 1 0 2 0 0 0 0 (c) 0 2× (c) word (A) ← (AH) and (A) word (A) ← (A) and imm16 word (A) ← (A) and (ear) word (A) ← (A) and (eam) word (ear) ← (ear) and (A) word (eam) ← (eam) and (A) – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * R R R R R R – – – – – – – – – – – * ORW ORW ORW ORW ORW ORW A 1 2 A, #imm16 3 2 A, ear 2 3 A, eam 2+ 4+ (a) ear, A 2 3 eam, A 2+ 5+ (a) 0 0 1 0 2 0 0 0 0 (c) 0 2× (c) word (A) ← (AH) or (A) word (A) ← (A) or imm16 word (A) ← (A) or (ear) word (A) ← (A) or (eam) word (ear) ← (ear) or (A) word (eam) ← (eam) or (A) – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * R R R R R R – – – – – – – – – – – * XORW XORW XORW XORW XORW XORW A 1 2 A, #imm16 3 2 A, ear 2 3 A, eam 2+ 4+ (a) ear, A 2 3 eam, A 2+ 5+ (a) 0 0 1 0 2 0 0 0 0 (c) 0 2× (c) word (A) ← (AH) xor (A) word (A) ← (A) xor imm16 word (A) ← (A) xor (ear) word (A) ← (A) xor (eam) word (ear) ← (ear) xor (A) word (eam) ← (eam) xor (A) – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * R R R R R R – – – – – – – – – – – * 0 2 0 0 word (A) ← not (A) 0 word (ear) ← not (ear) 2× (c) word (eam) ← not (eam) – – – – – – – – – – – – – – – * * * * * * R R R – – – – – * NOTW A NOTW ear NOTW eam 1 2 2 3 2+ 5+ (a) Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 64 MB90550A Series Table 15 Logical 2 Instructions (Long Word) [6 Instructions] Mnemonic # ~ RG B Operation LH AH I S T N Z V C RMW ANDL A, ear ANDL A, eam 2 2+ 6 7+ (a) 2 0 0 (d) long (A) ← (A) and (ear) long (A) ← (A) and (eam) – – – – – – – – – – * * * * R R – – – – ORL ORL A, ear A, eam 2 2+ 6 7+ (a) 2 0 0 (d) long (A) ← (A) or (ear) long (A) ← (A) or (eam) – – – – – – – – – – * * * * R R – – – – XORL A, ea XORL A, eam 2 2+ 6 7+ (a) 2 0 0 (d) long (A) ← (A) xor (ear) long (A) ← (A) xor (eam) – – – – – – – – – – * * * * R R – – – – Table 16 Mnemonic Sign Inversion Instructions (Byte/Word) [6 Instructions] # ~ RG B Operation LH AH I S T N Z V C RMW 2 0 0 byte (A) ← 0 – (A) X – – – – * * * * – – – – – – – – – – – * * * * * * * * – * – – – – – * * * * – – – – – – – – – – – * * * * * * * * – * NEG A 1 NEG NEG ear eam 2 3 2+ 5+ (a) 2 0 NEGW A 1 0 NEGW ear NEGW eam 2 3 2+ 5+ (a) 2 Table 17 Mnemonic # ~ RG B NRML A, R0 2 *1 1 0 2 0 0 byte (ear) ← 0 – (ear) 2× (b) byte (eam) ← 0 – (eam) 0 word (A) ← 0 – (A) 0 word (ear) ← 0 – (ear) 2× (c) word (eam) ← 0 – (eam) Normalize Instruction (Long Word) [1 Instruction] Operation LH long (A) ← Shift until first digit is “1” – byte (R0) ← Current shift count AH I S T N Z V C RMW – – – – – * – – – *1: 4 when the contents of the accumulator are all zeroes, 6 + (R0) in all other cases (shift count). Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 65 MB90550A Series Table 18 Mnemonic RORC A ROLC A Shift Instructions (Byte/Word/Long Word) [18 Instructions] # ~ RG B 2 2 2 2 0 0 0 0 Operation LH AH I S T N Z V C RMW byte (A) ← Right rotation with carry byte (A) ← Left rotation with carry – – – – – – – – – – * * * * – – * * – – 2 3 2+ 5+ (a) 2 3 2+ 5+ (a) 2 0 0 2× (b) 2 0 0 2× (b) byte (ear) ← Right rotation with carry byte (eam) ← Right rotation with carry byte (ear) ← Left rotation with carry byte (eam) ← Left rotation with carry – – – – – – – – – – – – – – – – * * * * * * * * – – – – * * * * – * – * 2 2 2 *1 *1 *1 1 1 1 0 0 0 byte (A) ← Arithmetic right barrel shift (A, R0) byte (A) ← Logical right barrel shift (A, R0) byte (A) ← Logical left barrel shift (A, R0) – – – – – – – – * – – * – – – * * * * * * – – – * * * – – – ASRW A LSRW A/SHRW A LSLW A/SHLW A 1 1 1 2 2 2 0 0 0 0 0 0 word (A) ← Arithmetic right shift (A, 1 bit) – – – – – – – – * * * – – * R * – – – * * – – – * * * – – – ASRW A, R0 LSRW A, R0 LSLW A, R0 2 2 2 *1 *1 *1 1 1 1 0 0 0 word (A) ← Arithmetic right barrel shift (A, R0) word (A) ← Logical right barrel shift (A, R0) word (A) ← Logical left barrel shift (A, R0) – – – – – – – – * – – * – – – * * * * * * – – – * * * – – – ASRL A, R0 LSRL A, R0 LSLL A, R0 2 2 2 *2 *2 *2 1 1 1 0 0 0 long (A) ← Arithmetic right shift (A, R0) – – – – – – * – – * – – – * * * * * * – – – * * * – – – RORC ear RORC eam ROLC ear ROLC eam ASR LSR LSL A, R0 A, R0 A, R0 word (A) ← Logical right shift (A, 1 bit) word (A) ← Logical left shift (A, 1 bit) long (A) ← Logical right barrel shift (A, R0) long (A) ← Logical left barrel shift (A, R0) – – – – – – *1: 6 when R0 is 0, 5 + (R0) in all other cases. *2: 6 when R0 is 0, 6 + (R0) in all other cases. Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 66 MB90550A Series Table 19 Mnemonic BZ/BEQ BNZ/BNE BC/BLO BNC/BHS BN rel BP rel BV rel BNV rel BT rel BNT rel BLT rel BGE rel BLE rel BGT rel BLS rel BHI rel BRA rel rel rel rel rel Branch 1 Instructions [31 Instructions] RG B Operation * *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Branch when (Z) = 1 Branch when (Z) = 0 Branch when (C) = 1 Branch when (C) = 0 Branch when (N) = 1 Branch when (N) = 0 Branch when (V) = 1 Branch when (V) = 0 Branch when (T) = 1 Branch when (T) = 0 Branch when (V) xor (N) = 1 Branch when (V) xor (N) = 0 # ~ 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 JMP JMP JMP JMP JMPP JMPP JMPP @A addr16 @ear @eam @ear *3 @eam *3 addr24 1 3 2 2+ 2 2+ 4 2 3 3 4+ (a) 5 6+ (a) 4 0 0 1 0 2 0 0 0 0 0 (c) 0 (d) 0 CALL CALL CALL CALLV CALLP 2 @ear *4 @eam *4 2+ addr16 *5 3 1 #vct4 *5 2 @ear *6 6 7+ (a) 6 7 10 1 0 0 0 2 (c) 2× (c) (c) 2× (c) 2× (c) CALLP @eam *6 2+ 11+ (a) 0 *2 CALLP addr24 *7 4 0 2× (c) *1: *2: *3: *4: *5: *6: *7: 10 LH AH I S T N Z V C RMW – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Branch when ((V) xor (N)) or (Z) = 1 Branch when ((V) xor (N)) or (Z) = 0 Branch when (C) or (Z) = 1 Branch when (C) or (Z) = 0 Branch unconditionally word (PC) ← (A) word (PC) ← addr16 word (PC) ← (ear) word (PC) ← (eam) word (PC) ← (ear), (PCB) ← (ear +2) word (PC) ← (eam), (PCB) ← (eam +2) word (PC) ← ad24 0 to 15, (PCB) ← ad24 16 to 23 word (PC) ← (ear) word (PC) ← (eam) word (PC) ← addr16 Vector call instruction word (PC) ← (ear) 0 to 15, (PCB) ← (ear) 16 to 23 word (PC) ← (eam) 0 to 15, (PCB) ← (eam) 16 to 23 word (PC) ← addr0 to 15, (PCB) ← addr16 to 23 4 when branching, 3 when not branching. (b) + 3 × (c) Read (word) branch address. W: Save (word) to stack; R: read (word) branch address. Save (word) to stack. W: Save (long word) to W stack; R: read (long word) R branch address. Save (long word) to stack. Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 67 MB90550A Series Table 20 Mnemonic CBNE A, #imm8, rel CWBNE A, #imm16, rel CBNE CBNE ear, #imm8, rel eam, #imm8, rel* 10 CWBNE ear, #imm16, rel CWBNE eam, #imm16, rel*10 Branch 2 Instructions [19 Instructions] # ~ RG B Operation 3 4 1 * *1 0 0 0 0 Branch when byte (A) ≠ imm8 Branch when word (A) ≠ imm16 4 4+ 5 5+ *2 *3 *4 *3 1 0 1 0 0 (b) 0 (c) Branch when byte (ear) ≠ imm8 Branch when byte (eam) ≠ imm8 Branch when word (ear) ≠ imm16 Branch when word (eam) ≠ imm16 *5 2 0 DBNZ ear, rel 3 DBNZ eam, rel 3+ *6 N Z V C RMW – – – – – – * – – – – * * * * * * * – – – – – – – – – – * * * * * * * * * * * * * * * * – – – – Branch when byte (ear) = (ear) – 1, and (ear) ≠ 0 2 2× (b) Branch when byte (eam) = (eam) – 1, and (eam) ≠ 0 – – – – – * * * – – – – – – – * * * – * Branch when word (ear) = (ear) – 1, and (ear) ≠ 0 2× (c) Branch when word (eam) = (eam) – 1, and (eam) ≠ 0 – – – – – * * * – – – – – – – * * * – * Software interrupt Software interrupt Software interrupt Software interrupt Return from interrupt – – – – – – – – – – – – – – * – – – – * – – – – * – – – – – At constant entry, save old frame pointer to stack, set new frame pointer, and allocate local pointer area At constant entry, retrieve old frame pointer from stack. – – – – – – – – – – – – – – – – – – – – Return from subroutine Return from subroutine – – – – – – – – – – – – – – – – – – – – DWBNZ ear, rel 3 *5 2 DWBNZ eam, rel 3+ *6 2 INT INT INTP INT9 RETI #vct8 addr16 addr24 2 3 4 1 1 20 16 17 20 15 0 0 0 0 0 8× (c) 6× (c) 6× (c) 8× (c) *7 LINK #local8 2 6 0 (c) UNLINK 1 5 0 (c) RET *8 RETP *9 1 1 4 6 0 0 (c) (d) 0 LH AH I – – – – R R R R * S – – – – S S S S * T – – – – – – – – * – – – – * *1: 5 when branching, 4 when not branching *2: 13 when branching, 12 when not branching *3: 7 + (a) when branching, 6 + (a) when not branching *4: 8 when branching, 7 when not branching *5: 7 when branching, 6 when not branching *6: 8 + (a) when branching, 7 + (a) when not branching *7: Set to 3 × (b) + 2 × (c) when an interrupt request occurs, and 6 × (c) for return. *8: Retrieve (word) from stack *9: Retrieve (long word) from stack *10: In the CBNE/CWBNE instruction, do not use the RWj+ addressing mode. Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 68 MB90550A Series Table 21 Other Control Instructions (Byte/Word/Long Word) [36 Instructions] # ~ RG B Operation PUSHW A PUSHW AH PUSHW PS PUSHW rlst 1 1 1 2 4 4 4 *3 0 0 0 *5 (c) (c) (c) *4 POPW POPW POPW POPW A AH PS rlst 1 1 1 2 3 3 4 *2 0 0 0 *5 (c) (c) (c) *4 JCTX @A 1 14 0 AND CCR, #imm8 OR CCR, #imm8 2 2 3 3 0 0 MOV RP, #imm8 MOV ILM, #imm8 2 2 2 2 Mnemonic LH AH I S T N Z V C RMW word (SP) ← (SP) –2, ((SP)) ← (A) word (SP) ← (SP) –2, ((SP)) ← (AH) word (SP) ← (SP) –2, ((SP)) ← (PS) (SP) ← (SP) –2n, ((SP)) ← (rlst) – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – word (A) ← ((SP)), (SP) ← (SP) +2 word (AH) ← ((SP)), (SP) ← (SP) +2 word (PS) ← ((SP)), (SP) ← (SP) +2 (rlst) ← ((SP)), (SP) ← (SP) +2n – – – – * – – – – – – – – – – – – – – – – – * * * * * * * – – – – – – – – – – – – – * * * * * * * – 0 0 byte (CCR) ← (CCR) and imm8 – – byte (CCR) ← (CCR) or imm8 – – * * * * * * * * * * * * * * – – 0 0 0 0 byte (RP) ←imm8 byte (ILM) ←imm8 – – – – – – – – – – – – – – – – – – – – MOVEA RWi, ear 2 3 MOVEA RWi, eam 2+ 2+ (a) MOVEA A, ear 2 1 MOVEA A, eam 2+ 1+ (a) 1 1 0 0 0 0 0 0 word (RWi) ←ear word (RWi) ←eam word(A) ←ear word (A) ←eam – – – – – – * * – – – – – – – – – – – – ADDSP #imm8 ADDSP #imm16 2 3 3 3 0 0 0 0 word (SP) ← (SP) +ext (imm8) word (SP) ← (SP) +imm16 – – – – – – – – – – – – – – – – – – – – MOV MOV 2 2 *1 1 0 0 0 0 byte (A) ← (brgl) byte (brg2) ← (A) Z * – – – – – – – – * * * * – – – – – – 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 No operation – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – NOP ADB DTB PCB SPB NCC CMR A, brgl brg2, A 6× (c) Context switch instruction Prefix code for accessing AD space Prefix code for accessing DT space Prefix code for accessing PC space Prefix code for accessing SP space Prefix code for no flag change Prefix code for common register bank – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – *1: PCB, ADB, SSB, USB, and SPB : 1 state DTB, DPR : 2 states *2: 7 + 3 × (pop count) + 2 × (last register number to be popped), 7 when rlst = 0 (no transfer register) *3: 29 + (push count) – 3 × (last register number to be pushed), 8 when rlst = 0 (no transfer register) *4: Pop count × (c), or push count × (c) *5: Pop count or push count. Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 69 MB90550A Series Table 22 Bit Manipulation Instructions [21 Instructions] # ~ RG B MOVB A, dir:bp MOVB A, addr16:bp MOVB A, io:bp 3 4 3 5 5 4 0 0 0 (b) (b) (b) MOVB dir:bp, A MOVB addr16:bp, A MOVB io:bp, A 3 4 3 7 7 6 0 0 0 SETB dir:bp SETB addr16:bp SETB io:bp 3 4 3 7 7 7 CLRB dir:bp CLRB addr16:bp CLRB io:bp 3 4 3 BBC BBC BBC dir:bp, rel addr16:bp, rel io:bp, rel BBS BBS BBS Mnemonic Operation LH AH I S T N Z V C RMW Z Z Z * * * – – – – – – – – – * * * * * * – – – – – – – – – 2× (b) bit (dir:bp) b ← (A) 2× (b) bit (addr16:bp) b ← (A) 2× (b) bit (io:bp) b ← (A) – – – – – – – – – – – – – – – * * * * * * – – – – – – * * * 0 0 0 2× (b) bit (dir:bp) b ← 1 2× (b) bit (addr16:bp) b ← 1 2× (b) bit (io:bp) b ← 1 – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * 7 7 7 0 0 0 2× (b) bit (dir:bp) b ← 0 2× (b) bit (addr16:bp) b ← 0 2× (b) bit (io:bp) b ← 0 – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * 4 5 4 *1 *1 *2 0 0 0 (b) (b) (b) Branch when (dir:bp) b = 0 Branch when (addr16:bp) b = 0 Branch when (io:bp) b = 0 – – – – – – – – – – – – – – – – – – * * * – – – – – – – – – dir:bp, rel addr16:bp, rel io:bp, rel 4 5 4 *1 *1 *2 0 0 0 (b) (b) (b) Branch when (dir:bp) b = 1 Branch when (addr16:bp) b = 1 Branch when (io:bp) b = 1 – – – – – – – – – – – – – – – – – – * * * – – – – – – – – – SBBS addr16:bp, rel 5 *3 0 2× (b) Branch when (addr16:bp) b = 1, bit = 1 – – – – – – * – – * WBTS io:bp 3 *4 0 *5 Wait until (io:bp) b = 1 – – – – – – – – – – WBTC io:bp 3 *4 0 *5 Wait until (io:bp) b = 0 – – – – – – – – – – *1: *2: *3: *4: *5: byte (A) ← (dir:bp) b byte (A) ← (addr16:bp) b byte (A) ← (io:bp) b 8 when branching, 7 when not branching 7 when branching, 6 when not branching 10 when condition is satisfied, 9 when not satisfied Undefined count Until condition is satisfied Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” Table 23 Mnemonic SWAP SWAPW EXT EXTW ZEXT ZEXTW 70 Accumulator Manipulation Instructions (Byte/Word) [6 Instructions] # ~ RG B Operation 1 1 1 1 1 1 3 2 1 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 byte (A) 0 to 7 ↔ (A) 8 to 15 word (AH) ↔ (AL) byte sign extension word sign extension byte zero extension word zero extension LH AH I S T N Z V C RMW – – X – Z – – * – X – Z – – – – – – – – – – – – – – – – – – – – * * R R – – * * * * – – – – – – – – – – – – – – – – – – MB90550A Series Table 24 # ~ RG B MOVS/MOVSI MOVSD 2 2 2 * *2 5 * *5 3 * *3 SCEQ/SCEQI SCEQD 2 2 *1 *1 *5 *5 FISL/FILSI 2 6m +6 *5 Mnemonic String Instructions [10 Instructions] Operation LH AH I S T N Z V C RMW Byte transfer @AH+ ← @AL+, counter = RW0 Byte transfer @AH– ← @AL–, counter = RW0 – – – – – – – – – – – – – – – – – – – – *4 *4 Byte retrieval (@AH+) – AL, counter = RW0 Byte retrieval (@AH–) – AL, counter = RW0 – – – – – – – – – – * * * * * * * * – – *3 Byte filling @AH+ ← AL, counter = RW0 – – – – – * * – – – MOVSW/MOVSWI 2 MOVSWD 2 *2 *2 *8 *8 *6 *6 Word transfer @AH+ ← @AL+, counter = RW0 Word transfer @AH– ← @AL–, counter = RW0 – – – – – – – – – – – – – – – – – – – – SCWEQ/SCWEQI SCWEQD 2 2 *1 *1 *8 *8 *7 *7 Word retrieval (@AH+) – AL, counter = RW0 Word retrieval (@AH–) – AL, counter = RW0 – – – – – – – – – – * * * * * * * * – – FILSW/FILSWI 2 6m +6 *8 *6 Word filling @AH+ ← AL, counter = RW0 – – – – – * * – – – m: RW0 value (counter value) n: Loop count *1: 5 when RW0 is 0, 4 + 7 × (RW0) for count out, and 7 × n + 5 when match occurs *2: 5 when RW0 is 0, 4 + 8 × (RW0) in any other case *3: (b) × (RW0) + (b) × (RW0) when accessing different areas for the source and destination, calculate (b) separately for each. *4: (b) × n *5: 2 × (RW0) *6: (c) × (RW0) + (c) × (RW0) when accessing different areas for the source and destination, calculate (c) separately for each. *7: (c) × n *8: 2 × (RW0) Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 71 MB90550A Series ■ ORDERING INFORMATION Part number 72 Package MB90552APF MB90553APF MB90T552APF MB90T553APF MB90F553APF MB90P553APF 100-pin plastic QFP (FPT-100P-M06) MB90552APF MB90553APF MB90T552APF MB90T553APF MB90F553APF MB90P553APF 100-pin plastic LQFP (FPT-100P-M05) Remarks MB90550A Series ■ PACKAGE DIMENSIONS 100-pin plastic QFP (FPT-100P-M06) 23.90±0.40(.941±.016) 3.35(.132)MAX (Mounting height) 0.05(.002)MIN (STAND OFF) 20.00±0.20(.787±.008) 80 51 81 50 14.00±0.20 (.551±.008) 12.35(.486) REF 17.90±0.40 (.705±.016) 16.30±0.40 (.642±.016) INDEX 31 100 "A" LEAD No. 1 30 0.65(.0256)TYP 0.30±0.10 (.012±.004) 0.13(.005) 0.15±0.05(.006±.002) M Details of "A" part 0.25(.010) Details of "B" part "B" 0.10(.004) 0.30(.012) 10° 0.80±0.20 (.031±.008) 0.53(.021)MAX 22.30±0.40(.878±.016) C 0 0.18(.007)MAX 18.85(.742)REF 1994 FUJITSU LIMITED F100008-3C-2 Dimensions in mm (inches) 100-pin plastic LQFP (FPT-100P-M05) +0.20 16.00±0.20(.630±.008)SQ 75 1.50 –0.10 +.008 14.00±0.10(.551±.004)SQ 76 (Mouting height) .059 –.004 51 50 12.00 (.472) REF 15.00 (.591) NOM Details of "A" part 0.15(.006) INDEX 100 0.15(.006) 26 0.15(.006)MAX LEAD No. 1 "B" 25 0.40(.016)MAX "A" 0.50(.0197)TYP 0.18 .007 +0.08 –0.03 +.003 –.001 0.08(.003) M 0.127 .005 +0.05 –0.02 +.002 –.001 Details of "B" part 0.10±0.10 (STAND OFF) (.004±.004) 0.10(.004) C 0.50±0.20(.020±.008) 0~10° 1995 FUJITSU LIMITED F100007S-2C-3 Dimensions in mm (inches) 73 MB90550A Series FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: 81(44) 754-3763 Fax: 81(44) 754-3329 http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 http://www.fujitsu-ede.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220 http://www.fmap.com.sg/ F9910 FUJITSU LIMITED Printed in Japan All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. 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