FUJITSU SEMICONDUCTOR DATA SHEET DS07-12544-2E 8-bit Proprietary Microcontrollers CMOS F2MC-8L MB89590B/BW Series MB89593B/595B/P595B/ MB89593BW/595BW/P595BW ■ DESCRIPTION The MB89590B/BW series is a line of general-purpose, single-chip microcontrollers. In addition to a compact instruction set, these microcontrollers contain a variety of peripheral functions, such as PLL clock control, timers, a serial interface, a PWM timer, the USB hub function, and the USB function. The USB hub function, in particular, supports five ports (one of them is dedicated to an internal function) allowing them to interface with other USB devices. The microcontrollers also contain one USB function channel to support high speeds. ■ FEATURES • Package type 64-pin LQFP package (0.5 mm pitch) • High-speed operations at low voltage Minimum execution time : 0.33 µs (Automatically generates a 12 MHz main clock and a 48 MHz USB interface synchronization clock with an externally supplied 6 MHz clock and the internal PLL circuit.) • F2MC-8L CPU core Instruction set that is optimum to the controllers Multiplication and division instructions, 16-bit arithmetic operations, Branch instructions by bit testing, Bit manipulation instructions, etc. (Continued) ■ PACKAGE 64-pin plastic LQFP (FPT-64P-M03) MB89590B/BW Series (Continued) • PLL clock control The internal PLL clock circuit allows the use of low-speed clocks which are advantageous to noise characteristics. (6 MHz externally supplied clock : Internal system clock oscillated at 12 MHz) • Various timers 8-bit PWM timer (can be used as either 8-bit PWM timer × 2 channels or PPG timer × 1 channel) Internal 21-bit timebase timer • Internal USB transceiver circuit (Compatible with high and low speeds) • USB hub Compliant to USB Protocol Revision 1.0 Five downstream port channels (One of these channels is dedicated to a function.) Automatically responds to all USB protocols by hardware. Descriptor configuration information is provided as ROM data for automatic responding by hardware (vendor ID and product ID) . * String data is not supported. Allows switching between BUS power supply and own power supply modes. Power supply to the USB down ports is controlled port by port. • USB function Compliant to USB Protocol Revision 1.0 Support for full speed Allows four endpoints to be specified at maximum. Types of transfer supported : control/interrupt/bulk/isochronous Built-in DMAC (Maps the buffer for each endpoint on to the internal RAM to directly access the memory for function’s send and receive data.) • UART/serial interface Built-in UART/SIO function (selectable by switching) • External interrupt External interrupt (level detection × 8 channels) Eight inputs are independent of one another and can also be used for resetting from low-power consumption mode (the L-level detection feature available) . • Low power consumption (standby mode supported) Stop mode (There is almost no current consumption since oscillation stops.) Sleep mode (This mode stops the running CPU.) • A maximum of 45 general-purpose I/O ports General-purpose I/O ports (CMOS) : 34 General-purpose output ports (CMOS) : 8 General-purpose I/O ports (Nch open drain) : 3 • Power supply Supply voltage : 3.0 to 5.5 V 2 MB89590B/BW Series ■ PRODUCT LINEUP Part number Parameter MB89593B MB89595B MB89P595B MB89593BW MB89595BW MB89P595BW ROM size 8 KB 16 KB 8 KB 16 KB RAM size 512 B 1 KB 512 B 1 KB Package LQFP-64 (FPT-64P-M03) Operation at USB reset High impedance state MASK product Others MASK product OTP/EVA product Low-level output MASK product MASK product Number of instructions Instruction bit length Instruction length Data bit length Minimum execution time Interrupt processing time : 136 : 8 bits : 1 to 3 bytes : 1, 8, and 16 bits : 0. 33 µs (6 MHz) : 3 µs (6 MHz) Generalpurpose ports General-purpose I/O ports General-purpose output ports (34 : CMOS; 3 : Nch open drain) (8 : CMOS) USB hub Upstream port : 1 channel Downstream port : 5 channels (One is dedicated to an internal function.) Port power supply control method : By individual port Allows selection between own power supply and bus power supply CPU functions Peripher- USB al funcfunction tions PWM timer OTP/EVA product Supports full speed. Four endpoints at maximum Built-in DMAC (Allows DMA transfer to the internal RAM) 8-bit PWM timer operation × 2 channels (can also be used as a PPG × 1 channel timer) UART SIO Allows switching between UART (clock-synchronous/asynchronous data transfer allowed) and SIO (simple serial transfer) . Timebase timer 21-bit timebase timer Clock output Allows output of two main clock divisions Standby mode Sleep mode and Stop mode 3 MB89590B/BW Series ■ DIFFERENCES AMONG PRODUCTS 1. Memory Size Before evaluating using the OTP product, verify its differences from the product that will actually be used. 2. Current Consumption When operated at low speeds, a product mounted with either one-time PROM or EPROM consumes more current than a product mounted with a mask ROM. However, in sleep/stop mode the current consumption is the same. For detailed information on each package, see “■ PACKAGE DIMENSIONS.” 3. Differences Between the MB89590B series and the MB89590BW Series MB89590B series : Remains in high impedance state until USB connection takes place. Before the USB connection, use one general-purpose port output to control pullup resistance connection of this port by software. MB89590BW series : Outputs at low level until USB connection takes place. • Example MB89590B product connection 3.3 V MB89590B series Host PC General-purpose port 1.5 kΩ RPVP pin D+ RPVM pin D− • Example MB89590BW product connection 3.3 V Host PC MB89590BW series 1.5 kΩ 4 D+ RPVP pin D− RPVM pin MB89590B/BW Series ■ PIN ASSIGNMENT 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 P43/POW4 P42/POW3 P41/POW2 P40/POW1 D4VM D4VP D3VM D3VP D2VM D2VP D1VM D1VP RPVM RPVP C VCC (TOP VIEW) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 P53 P54 RST MOD0 MOD1 X0 X1 VSS P27 P26 P25 P24 P23 P22 P21 P20 P44/UCK P45/UO P46/UI/PWM1 P47/PWM2 P30/INT0/CLK P31/INT1 P32/INT2 P33/INT3 P34/INT4 P35/INT5 P36/INT6 P37/INT7 P50 VSS P51 P52 (FPT-64P-M03) 5 MB89590B/BW Series ■ PIN DESCRIPTION Pin No. Pin name Circuit type Function 1 P44/UCK E General-purpose CMOS I/O pin UART/S10 clock I/O 2 P45/UO B General-purpose CMOS I/O pin UART/S10 serial data output 3 P46/UI/ PWM1 E General-purpose CMOS I/O pin UART/S10 serial data input PWM timer 4 P47/PWM2 B General-purpose CMOS I/O pin PWM timer 5 P30/INT0/ CLK E General-purpose CMOS I/O pin Clock output pin This pin also serves as an external interrupt input pin. The external interrupt input is a hysteresis input. (Level detection) 6 P31/INT1 E General-purpose CMOS I/O pin This pin also serves as an external interrupt input pin. The external interrupt input is a hysteresis input. (Level detection) 7 P32/INT2 E General-purpose CMOS I/O pin This pin also serves as an external interrupt input pin. The external interrupt input is a hysteresis input. (Level detection) 8 P33/INT3 E General-purpose CMOS I/O pin This pin also serves as an external interrupt input pin. The external interrupt input is a hysteresis input. (Level detection) 9 P34/INT4 E General-purpose CMOS I/O pin This pin also serves as an external interrupt input pin. The external interrupt input is a hysteresis input. (Level detection) 10 P35/INT5 E General-purpose CMOS I/O pin This pin also serves as an external interrupt input pin. The external interrupt input is a hysteresis input. (Level detection) 11 P36/INT6 E General-purpose CMOS I/O pin This pin also serves as an external interrupt input pin. The external interrupt input is a hysteresis input. (Level detection) 12 P37/INT7 E General-purpose CMOS I/O pin This pin also serves as an external interrupt input pin. The external interrupt input is a hysteresis input. (Level detection) 13 P50 B General-purpose CMOS I/O pin 14 VSS Power supply pin (GND) 15 P51 B General-purpose CMOS I/O pin 16 P52 K General-purpose Nch open drain I/O pin 17 P53 K General-purpose Nch open drain I/O pin 18 P54 K General-purpose Nch open drain I/O pin 19 RST I Reset pin. (Reset on the negative logic low level.) (Continued) 6 MB89590B/BW Series Pin No. Pin name Circuit type Function 20 MOD0 F An operating mode designation pin. Connect directly to Vss. 21 MOD1 F An operating mode designation pin. Connect directly to Vss. 22 X0 23 X1 A Pins for the Crystal oscillator (6 MHz) 24 VSS Power supply pin (GND) 25 P27 B General-purpose CMOS output pin 26 P26 B General-purpose CMOS output pin 27 P25 B General-purpose CMOS output pin 28 P24 B General-purpose CMOS output pin 29 P23 B General-purpose CMOS output pin 30 P22 B General-purpose CMOS output pin 31 P21 B General-purpose CMOS output pin 32 P20 B General-purpose CMOS output pin 33 P17 B General-purpose CMOS I/O pin 34 P16 B General-purpose CMOS I/O pin 35 P15 B General-purpose CMOS I/O pin 36 P14 B General-purpose CMOS I/O pin 37 P13 B General-purpose CMOS I/O pin 38 P12 B General-purpose CMOS I/O pin 39 P11 B General-purpose CMOS I/O pin 40 P10 B General-purpose CMOS I/O pin 41 P07 B General-purpose CMOS I/O pin 42 P06 B General-purpose CMOS I/O pin 43 P05 B General-purpose CMOS I/O pin 44 P04 B General-purpose CMOS I/O pin 45 P03 B General-purpose CMOS I/O pin 46 P02 B General-purpose CMOS I/O pin 47 P01 B General-purpose CMOS I/O pin 48 P00 B General-purpose CMOS I/O pin 49 VCC Power supply pin 50 C Connect an external capacitor of 0.1 µF. When using with 3.3 V power supply, connect this pin with the Vcc pin to set to 3.3 V input. 51 RPVP USBDRV USB route port + pin 52 RPVM USBDRV USB router port − pin (Continued) 7 MB89590B/BW Series (Continued) 8 Pin No. Pin name Circuit type Function 53 D1VP USBDRV USB down port 1 + pin 54 D1VM USBDRV USB down port 1 − pin 55 D2VP USBDRV USB down port 2 + pin 56 D2VM USBDRV USB down port 2 − pin 57 D3VP USBDRV USB down port 3 + pin 58 D3VM USBDRV USB down port 3 − pin 59 D4VP USBDRV USB down port 4 + pin 60 D4VM USBDRV USB down port 4 − pin 61 P40/POW1 B General-purpose CMOS I/O pin. This pin also serves as a USB Down Port power control signal pin. 62 P41/POW2 B General-purpose CMOS I/O pin. This pin also serves as a USB Down Port power control signal pin. 63 P42/POW3 B General-purpose CMOS I/O pin. This pin also serves as a USB Down Port power control signal pin. 64 P43/POW4 B General-purpose CMOS I/O pin. This pin also serves as a USB Down Port power control signal pin. MB89590B/BW Series ■ I/O CIRCUIT TYPE Type Circuit Remarks Oscillation feedback resistance X1 Approx. 1 MΩ A X0 CMOS I/O R Pch Pullup control register Pch B Nch Input CMOS I/O R Hysteresis input Pch Pullup control register Pch E Nch Port input Resource input CMOS input F Input Hysteresis I/O Pullup resistance R Pch I Nch Input (Continued) 9 MB89590B/BW Series (Continued) Type Circuit Remarks USB I/O D+ input D– input D+ Operation input D– Full D+ output USBDRV Full D– output Low D+ output Low D– output Direction Speed Nch open drain I/O R Pch Pullup control register K Nch Input 10 MB89590B/BW Series ■ HANDLING DEVICES 1. Preventing Latchup Latchup may occur on CMOS ICs if voltage higher than Vcc or lower than Vss is applied to input or output pins other than the medium- and high-voltage pins or if voltage higher than the rating is applied between Vcc and Vss. When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. Also take care to prevent the analog input from exceeding the digital power supply (Vcc) when the power supply to the analog power system is turned on and off. 2. Treatment of Unused Input Pins Leaving unused input pins open could cause malfunctions and latchup leading to permanent damage to the pins. These unused pins should be connected to a pullup or pulldown resistance of at least 2 kΩ between the pin and the power supply. Unused I/O pins should be placed in output state to leave it open or pins that are in input state should be handled the same as unused input pins. 3. Power Supply Voltage Fluctuations Although Vcc power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that Vcc ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched. 11 MB89590B/BW Series ■ ONE-TIME PROM AND EPROM MICROCONTROLLER PROGRAMMING SPECIFICATIONS PROM mode is available on the MB89P595B/BW microcontrollers. The use of a dedicated adapter allows you to program the devices with a general-purpose ROM programmer. However, keep in mind that electronic signature mode is not available. 1. Memory Space Normal operating mode 0000H (Corresponding addresses on the ROM programmer) I/O 0080H RAM 0480H Not available C000H 0000H Program area (PROM) FFFFH Program area (PROM) 3FFFH 2. ROM programmer adapter and its compatible programmers Compatible adapter Compatible programmers and models Sun Hayato Co, Ltd. Ando Denki K. K. ROM2-64LQF-32DP-8LA AF9708 (Version 1.40 or higher) AF9709 (Version 1.40 or higher) AF9723 (Version 1.50 or higher) Package FTP-64P-M03 Inquiry: Sun Hayato Co., Ltd. Ando Denki K. K. : TEL. 81-3-3986-0403 : TEL. 81-3-3733-1160 3. Programming the EPROM (Using the Ando Denki K.K. programmer) (1) Set the EPROM programmer type code to 17209. (2) Load program data on to the EPROM programmer at 0000H to 3FFFH. (3) Program C000H to FFFFH with the EPROM programmer. 12 MB89590B/BW Series ■ BLOCK DIAGRAM X0 X1 Main clock oscillator Reset output Clock control circuit Power on reset circuit (watchdog timer) PLL circuit D1VM to D4VM Dp1-4 USB HUB circuit CMOS I/O Port P40/POW1 to P43/POW4 P46/UI/PWM1 8-bit PWM timer P47/PWM2 CMOS I/O Port Dp5 Internal bus D1VP to D4VP USB DRV RPVM 21-bit timebase timer Rp RPVP UART USB Function circuit SIO CMOS out Port P50 , P51 CMOS I/O Port P31/INT1 to P37/INT7 P44/UCK P45/UO P00 to P07, P10 to P17 DMAC P30/INT0/CLK RST P20 to P27 Clock output External interrupt (level) RAM 1 K / 512 Byte F2MC - 8L CPU Nch I/O Port P52 to P54 ROM 8 K / 16 KByte Other pins VSS VCC MOD0 MOD1 C 13 MB89590B/BW Series ■ CPU CORE 1. Memory Space The MB89590B/BW microcontrollers offer a memory space of 64 Kbytes consisting of the I/O, RAM and ROM areas. The memory space contains areas that are used for specific purposes, such as a general-purpose register and a vector table. • I/O area (addresses : 0000H through 007FH) This area is assigned with the control and data registers, for example, of peripheral functions to be built in. The I/O area is as accessible as the memory since the area is assigned to a part of the memory space. Direct addressing also allows the area to be accessed faster. • RAM area As an internal data area, a static RAM is built in. The internal RAM capacity varies with the product type. The area 80H to FFH can be accessed at high speed with direct addressing. The area 100H to 1FFH can be used a general-purpose register area. (The usable area is limited depending on the product.) When reset, RAM data becomes undefined. • ROM area As an internal program area, a ROM is built in. The internal ROM capacity varies with the product type. The area FFCOH to FFFFH should be used for a vector table, for example. • Memory Map MB89593B MB89593BW 0000H MB89P595B, MB89P595BW MB89595B, MB89595BW 0000H I/O I/O 0080H 0080H RAM RAM 0100H 0100H Register 0200H Register 0200H 0280H 0480H Not available Not available C000H E000H ROM* ROM FFC0H FFFFH Vector table (reset, interrupt, vector call instructions) 14 FFC0H FFFFH * The area is EPROM on the MB89P595B and MB89P595BW microcontrollers. MB89590B/BW Series 2. Registers The MB89590B/BW series has two types of registers; the registers dedicated to specific purposes in the CPU and the general-purpose registers. The dedicated registers are as follows: Program counter (PC) : A 16-bit register to indicate locations where instructions are stored. Accumulator (A) : A 16-bit register for temporary storage of operations. In the case of an 8-bit data processing instruction, the lower one byte is used. Temporary accumulator (T) : A 16-bit register which performs operations with the accumulator. In the case of an 8-bit data processing instruction, the lower one byte is used. Index register (IX) : A 16-bit register for index modification. Extra pointer (EP) : A 16-bit register to point to a memory address. Stack pointer (SP) : A 16-bit register to indicate a stack area. Program status (PS) : A 16-bit register to store a register pointer or a condition code. 16 bits : Program counter PC Initial value FFFDH A : Accumulator Indeterminate T : Temporary accumulator Indeterminate IX : Index register Indeterminate EP : Extra pointer Indeterminate SP : Stack pointer Indeterminate RP CCR PS : Program status I-flag = 0, IL1, 0 = 11 Initial values for other bits are indeterminate. 15 MB89590B/BW Series The PS register can further be divided into the register bank pointer in the higher 8 bits (RP) and the condition code register in the lower 8 bits (CCR) . (See the diagram below.) CCR RP PS bit15 bit14 bit13 bit12 bit11 bit10 bit9 R4 R3 R2 R1 R0 − − bit8 − bit7 H bit6 I bit5 IL1 bit4 IL0 bit3 N bit2 Z bit1 bit0 V C CCR initial value X011XXXXB H-flag I-flag IL 1, 0 N-flag Z-flag V-flag C-flag X : Undefined The RP points to the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule shown next. Rule for Conversion of Actual Addresses in the General-purpose Register Area RP higher bits "0" Generated addresses "0" "0" "0" "0" "0" A15 A14 A13 A12 A11 A10 "0" A9 "1" A8 R4 R3 A7 R2 A6 A5 R1 A4 OP code in lower bits R0 A3 b2 A2 b1 A1 b0 A0 The CCR consists of the bits indicating arithmetic operation results or transfer data contents and the bits that control CPU operations at the time of an interrupt. H flag I flag IL1, 0 16 : The flag is set to “1” when an arithmetic operation results in a carry from bit 3 to bit 4 or in a borrow from bit 4 to bit 3. The bit is cleared to “0” in other instances. The flag is for decimal adjustment instructions; do not use for other than additions and subtractions. : Interrupt is enabled when this flag is set to “1.” Interrupt is disabled when this flag is set to “0.” The flag is set to “0” when reset. : Indicates the level of the interrupt currently enabled. An interrupt is processed only if its level is higher than the value this bit indicates. IL1 IL0 Interrupt level 0 0 0 1 1 0 2 1 1 3 1 High-low Higher Lower = no interruption MB89590B/BW Series N flag Z flag V flag C flag : The flag is set to “1” when an arithmetic operation results in setting of the MSB to “1” or is cleared to “0” when the MSB is set to “1.” : The flag is set to “1” when an arithmetic operation results in “0” or is set to “0” in other instances. : The flag is set to “1” when an arithmetic operation results in two’s complement overflow or is cleared to “0” if no overflow occurs. : The flag is set to “1” when an arithmetic operation results in a carry from bit 7 or in a borrow to bit 7. The flag is cleared to “0” if neither of them occurs. In the case of a shift instruction, the flag is set to the shift-out value. The following general-purpose registers are provided: General-purpose registers : 8-bit data storage registers The general-purpose registers are 8 bits in length and located in the register banks in the memory. One bank contains eight registers and the MB89590B/BW microcontrollers allow a total of 16 banks to be used at maximum. The bank currently in use is indicated by the register bank pointer (RP) . Register Bank Configuration This address = 0100H + 8 × (RP) R0 R1 R2 R3 R4 R5 R6 R7 16 banks Memory area 17 MB89590B/BW Series ■ I/O MAP Address Register name Register description 00H PDR0 Port 0 data register 01H DDR0 Port 0 direction register 02H PDR1 Port 1 data register 03H DDR1 Port 1 direction register 04H PDR2 Port 2 data register 05H Vacancy 06H Vacancy Read/write Initial value R/W XXXXXXXX W 00000000 R/W XXXXXXXX W 00000000 R/W 00000000 07H SYCC System clock control register R/W XXX 1 1 X 0 0 08H STBC Standby control register R/W 0 0 0 1 XXXX 09H WDTC Watchdog timer control register R/W 0 XXXXXXX 0AH TBTC Timebase timer control register R/W 0 0 XXX 0 0 0 0BH Vacancy 0CH PDR3 Port 3 data register R/W XXXXXXXX 0DH DDR3 Port 3 direction register R/W 00000000 0EH Vacancy 0FH Vacancy 10H PDR4 Port 4 data register R/W XXXXXXXX 11H DDR4 Port 4 direction register R/W 00000000 12H PDR5 Port 5 data register R/W XXX 1 1 1 XX 13H DDR5 Port 5 direction register R/W XXXXXX 0 0 14H to 20H Vacancy 21H PURR0 Port 0 pullup option setting register R/W 11111111 22H PURR1 Port 1 pullup option setting register R/W 11111111 23H PURR2 Port 2 pullup option setting register R/W 11111111 24H PURR3 Port 3 pullup option setting register R/W 11111111 25H PURR4 Port 4 pullup option setting register R/W 11111111 26H PURR5 Port 5 pullup option setting register R/W XXX 1 1 1 1 1 27H CTR1 PWM control register 1 R/W 00000000 28H CTR2 PWM control register 2 R/W 000X0000 29H CTR3 PWM control register 3 R/W X 0 0 0 XXXX 2AH CMR1 PWM compare register 1 W XXXXXXXX 2BH CMR2 PWM compare register 2 W XXXXXXXX 2CH CKR R/W XXXXXXX 0 Clock output control register (Continued) 18 MB89590B/BW Series Address Register name 2DH SCS Register description Serial clock switching register Read/write Initial value R/W XXXXXXX 0 Vacancy 2EH 2FH SMC1 Serial mode control register 1 R/W 00000000 30H SMC2 Serial mode control register 2 R/W 00000000 31H SSD R 0 0 0 0 1 XXX 32H SIDR/SODR Serial input/serial output data register R/W XXXXXXXX 33H SRC Serial rate control register R/W XXXXXXXX Serial status and control register 34H to 3BH Vacancy 3CH EIE External interrupt control register R/W 00000000 3DH EIF External interrupt flag register R/W XXXXXXX 0 3EH Vacancy 3FH Vacancy 40H HMDR HUB mode register R/W 1 0 XXXXXX 41H HDSR1 Hub descriptor register 1 R/W XXXXXXXX 42H HDSR2 Hub descriptor register 2 R/W XXXXXXXX 43H HDSR3 Hub descriptor register 3 R/W XXXXXXXX 44H HSTR Hub status register R/W 00000000 45H OCCR Overcurrent register R/W 0 XXX 0 0 0 0 46H DADR Descriptor ROM address register R/W XXXXXXXX 47H SDSR String 0 descriptor select register R/W XXXXX 0 0 0 48H to 4FH Vacancy 50H UMDR USB reset mode register R/W 1 0 0 0 XX 0 0 51H DBAR DMA base address register R/W XXXXXXXX 52H TDCR0 Transfer data count register 0 R/W X0000000 53H TDCR1 Transfer data count register 1 R/W X0000000 R/W X0000000 54H 55H Vacancy TDCR21 Transfer data count register 2 Vacancy 56H 57H TDCR3 Transfer data count register 3 R/W X0000000 58H UCTR USB control register R/W 00000000 59H USTR1 USB status register 1 R/W 00000000 5AH USTR2 USB status register 2 R XXXXXX 0 0 (Continued) 19 MB89590B/BW Series (Continued) Address Register name 5BH UMSKR 5CH Register description Read/write Initial value USB interrupt mask register R/W 00000000 UFRMR1 USB frame status register 1 R XXXXXXXX 5DH UFRMR2 USB frame status register 2 R XXXXXXXX 5EH EPER USB endpoint enable register R/W XXXX 0 0 0 1 5FH EPBR0 Endpoint setup register 0 R/W X0000000 60H EPBR11 Endpoint setup register 11 R/W XX 0 0 0 0 XX 61H EPBR12 Endpoint setup register 12 R/W X0000000 62H EPBR21 Endpoint setup register 21 R/W XX 0 0 0 0 XX 63H EPBR22 Endpoint setup register 22 R/W X0000000 64H EPBR31 Endpoint setup register 31 R/W XX 0 0 0 0 XX 65H EPBR32 Endpoint setup register 32 R/W X0000000 66H to 7BH Vacancy 7CH ILR1 Interrupt level setting register 1 W 11111111 7DH ILR2 Interrupt level setting register 2 W 11111111 7EH ILR3 Interrupt level setting register 3 W 11111111 7FH Vacancy • Information about read/write R/W : Read or write enabled, R : Read only, W : Write only • Information about initial values 0 : The initial value of this bit is “0.” 1 : The initial bit of this bit is “1.” X : The initial value of this bit is undefined. Note : Vacancies are not for use. 20 MB89590B/BW Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter (VSS = 0 V) Symbol Value Unit Min. Max. VCC VSS − 0.3 VSS + 6.0 V Input voltage VI VSS − 0.3 VCC + 0.3 V Output voltage VO VSS − 0.3 VCC + 0.3 V “L” level average output current IOLAV 4 mA “L” level total maximum output current ΣIOL 100 mA ΣIOLAV 40 mA IOH −15 mA “H” level average output current IOHAV −4 mA “H” level total maximum output current ΣIOH −50 mA ΣIOHAV −20 mA Power consumption PD 300 mW Operating temperature TA −40 +85 °C Tstg −55 +150 °C Power supply voltage “L” level total average output current “H” level maximum output current “H” level total average output current Storage temperature Remarks Average value (operating current × operating rate) Average value (operating current × operating rate) Average value (operating current × operating rate) Average value (operating current × operating rate) WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 21 MB89590B/BW Series 2. Recommended Operating Conditions Parameter Symbol (VSS = 0 V) Value Min. Typ. Max. Unit Remarks Power supply voltage VCC 3.0 5.5 V Operating temperature TA −40 +85 °C Smoothing capacitor CS 0.1 1.0 µF at VCC = 5.0 V* Series resistance RS 16 Ω When the USB function is in use * : Use either a ceramic capacitor or a capacitor with similar frequency characteristics. The capacity of the smoothing capacitor for the Vcc pin should be greater than that of the Cs. When using with a supply voltage of 3.3 V, connect pin C with Vcc to input 3.3 V. • C and USB Port Pin Connection Diagram RS D1VP RS D1VM RS D2VP RS RPVP RS D2VM RS RPVM RS D3VP RS C CS D3VM RS D4VP RS D4VM 22 MB89590B/BW Series 5.5 Operating voltage VCC (V) 5.0 4.0 3.0 2.0 1.0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 CPU operating frequency (FCH MHz) (At instruction cycle 4/ FCH) 4.0 2.0 0.8 0.4 0.33 Minimum execution time (instruction cycle) (µs) However, FCH = clock frequency (Fc) × 2 WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 23 MB89590B/BW Series 3. DC Characteristics Parameter Symbol Pin name Condition VIH P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P54, MOD0, MOD1 VIHS “L” level output voltage Input leakage current (Hi-Z output leakage current) Unit Typ. Max. 0.7 VCC VCC + 0.3 V RST, INT0 to INT7, UCK, UI 0.8 VCC VCC + 0.3 V VIL P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P54, MOD0, MOD1 VSS − 0.3 0.3 VCC V VILS RST, INT0 to INT7, UCK, UI VSS − 0.3 0.2 VCC V VD1 P52 to P54 VSS − 0.3 VCC + 0.3 V VOH P00 to P07, P10 to P17, P20 to P24, P30 to P37, P40 to P47, P50, P51 IOH = −2.0 mA 4.0 V VOL P00 to P07, P10 to P17, P20 to P24, P30 to P37, P40 to P47, P50 to P54, RST IOL = 4.0 mA 0.4 V ILI P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50, P51 0.0 < VI < VCC −5 +5 µA “L” level input voltage “H” level output voltage Value Min. “H” level input voltage Open-drain output application voltage (VCC = 5.0 V, VSS = 0 V, TA = −40 °C to +85 °C) Remarks When no pullup resistance is specified (Continued) 24 MB89590B/BW Series (Continued) Parameter Open-drain output leakage current Pullup resistance (VCC = 5.0 V, VSS = 0 V, TA = −40 °C to +85 °C) Symbol Pin name ILIOD P52 to P54 RPULL P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P54, RST 0.0 < VI < VSS + 5.5 VI = 0.0 V Value Min. Typ. Max. +5 25 50 Unit Remarks µA 100 kΩ RST is excluded when pullup resistance available is specified. FCH = 12.0 MHz VCC = 5.0 V tinst = 0.333 µs 25 38 MB89P595B/ BW mA MB89595B/ BW ICCS1 FCH = 12.0 MHz VCC = 5.0 V tinst = 0.333 µs 20 30 mA Sleep mode ICCH TA = 25 °C 5 20 µA 10 pF ICC Power supply current Input capacitance Condition VCC CIN Other than Vcc f = 1 MHz and Vss Stop 25 MB89590B/BW Series 4. AC Characteristics (1) Reset Timing (VCC = 5.0 V, VSS = 0 V, TA = −40 °C to +85 °C) Parameter RST “L” pulse width Symbol Condition tZLZH Value Min. Max. 16 tHCLY Unit Remarks ns Note : tHCYL is the internal main clock oscillating cycle (1/2 Fc) . tZLZH RST 0.2 VCC 0.2 VCC (2) Power-on Reset (VSS = 0 V, TA = −40 °C to +85 °C) Parameter Symbol Condition Power supply rising time tR Power supply cutoff time tOFF Value Unit Min. Max. 0.066 50 ms 4 ns Remarks Due to repeated operations Note : The power supply must be up within the selected oscillation stabilization time. When the supply voltage needs to be varied while operating, it is recommended to smoothly start up the voltage. tR tOFF 3.5 V VCC 0.2 V 26 0.2 V 0.2 V MB89590B/BW Series (3) Clock Timing Parameter (VSS = 0 V, TA = −40 °C to +85 °C) Symbol Pin name Condition Value Min. Typ. Max. Unit Clock frequency FC X0, X1 6 MHz Clock cycle time tXCYL X0, X1 166.6 ns Internal main clock frequency FCH 12 MHz Internal clock cycle tHCYL 83.3 ns Remarks Twice the Fc tXCYL/2 • X0 and X1 Timing and Conditions tXCYL X0 0.2 VCC 0.2 VCC • Clock Conditions When a crystal resonator is used X0 X1 C1 C2 (4) Instruction Cycle Parameter Instruction cycle (Min. execution time) (VSS = 0 V, TA = −40 °C to +85 °C) Symbol Value Unit Remarks tinst 4 / FCH, 8 / FCH, 16 / FCH, 64 / FCH µs When operating at FCH = 12 MHz tinst = 0.33 µs (4 / FCH) 27 MB89590B/BW Series (5) UART Serial I/O Timing Parameter (VCC = 5.0 V, VSS = 0 V, TA = −40 °C to +85 °C) Symbol Pin name Serial clock cycle time tSCYC UCK UCK ↓ → UO tSLOV UCK, UO Valid UI → UCK ↑ tIVSH UI, UCK UCK ↑ → Rvalid UI hold time tSHIX UCK, UI Serial clock “H” pulse width tSHSL Serial clock “L” pulse width tSLSH Condition Internal shift clock mode UCK UCK ↓ → UO time tSLOV UCK, UO Valid UI → UCK ↑ tIVSH UI, UCK UCK ↑ → Rvalid UI hold time tSHIX UCK, UI External shift clock mode Value Max. 2 tinst* µs −200 200 ns 200 ns 200 ns 1 tinst* µs 1 tinst* µs 0 200 ns 200 ns 200 ns * : For information about tinst see “Instruction Cycle.” • Internal shift clock mode tSCYC UCK 2.4 V 0.8 V 0.8 V tSLOV 2.4 V 0.8 V UO tIVSH tSHIX 0.8 VCC 0.2 VCC UI 0.8 VCC 0.2 VCC • External shift clock mode tSLSH tSHSL UCK 0.8 VCC 0.2 VCC 0.8 VCC 0.2 VCC tSLOV 2.4 V UO 0.8 V tIVSH UI 28 0.8 VCC 0.2 VCC Unit Min. tSHIX 0.8 VCC 0.2 VCC Remarks MB89590B/BW Series (6) Peripheral Input Timing Parameter (VCC = 5.0 V, VSS = 0 V, TA = −40 °C to +85 °C) Symbol Peripheral input “H” pulse width 1 tILIH1 Peripheral input “L” pulse width 1 tIHIL1 Pin name Value Condition Unit Min. Max. 2 tinst* µs 2 tinst* µs Remarks INT0 to INT7 * : For information about tinst, see “Instruction Cycle.” tIHIL1 tILIH1 INT0 to INT7 0.8 VCC 0.2 VCC 0.8 VCC 0.2 VCC 29 MB89590B/BW Series ■ INSTRUCTIONS (136 INSTRUCTIONS) Execution instructions can be divided into the following four groups: • Transfer • Arithmetic operation • Branch • Others Table 1 lists symbols used for notation of instructions. Table 1 Symbol dir off ext #vct #d8 #d16 dir: b rel @ A AH AL T TH TL IX EP PC SP PS dr CCR RP Ri × (×) (( × )) Instruction Symbols Meaning Direct address (8 bits) Offset (8 bits) Extended address (16 bits) Vector table number (3 bits) Immediate data (8 bits) Immediate data (16 bits) Bit direct address (8:3 bits) Branch relative address (8 bits) Register indirect (Example: @A, @IX, @EP) Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.) Upper 8 bits of accumulator A (8 bits) Lower 8 bits of accumulator A (8 bits) Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.) Upper 8 bits of temporary accumulator T (8 bits) Lower 8 bits of temporary accumulator T (8 bits) Index register IX (16 bits) Extra pointer EP (16 bits) Program counter PC (16 bits) Stack pointer SP (16 bits) Program status PS (16 bits) Accumulator A or index register IX (16 bits) Condition code register CCR (8 bits) Register bank pointer RP (5 bits) General-purpose register Ri (8 bits, i = 0 to 7) Indicates that the very × is the immediate data. (Whether its length is 8 or 16 bits is determined by the instruction in use.) Indicates that the contents of × is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) The address indicated by the contents of × is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) Columns indicate the following: Mnemonic: Assembler notation of an instruction ~: The number of instructions #: The number of bytes Operation: Operation of an instruction TL, TH, AH: A content change when each of the TL, TH, and AH instructions is executed. Symbols in the column indicate the following: • “–” indicates no change. • dH is the 8 upper bits of operation description data. • AL and AH must become the contents of AL and AH prior to the instruction executed. • 00 becomes 00. N, Z, V, C: An instruction of which the corresponding flag will change. If + is written in this column, the relevant instruction will change its corresponding flag. OP code: Code of an instruction. If an instruction is more than one code, it is written according to the following rule: Example: 48 to 4F ← This indicates 48, 49, ... 4F. 30 MB89590B/BW Series Table 2 Mnemonic Transfer Instructions (48 instructions) ~ # Operation TL TH AH NZVC OP code MOV dir,A MOV @IX +off,A MOV ext,A MOV @EP,A MOV Ri,A MOV A,#d8 MOV A,dir MOV A,@IX +off MOV A,ext MOV A,@A MOV A,@EP MOV A,Ri MOV dir,#d8 MOV @IX +off,#d8 MOV @EP,#d8 MOV Ri,#d8 MOVW dir,A MOVW @IX +off,A 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 – – – – – AL AL AL AL AL AL AL – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –––– –––– –––– –––– –––– ++–– ++–– ++–– ++–– ++–– ++–– ++–– –––– –––– –––– –––– –––– –––– 45 46 61 47 48 to 4F 04 05 06 60 92 07 08 to 0F 85 86 87 88 to 8F D5 D6 MOVW ext,A MOVW @EP,A MOVW EP,A MOVW A,#d16 MOVW A,dir MOVW A,@IX +off 5 4 2 3 4 5 3 1 1 3 2 2 – – – AL AL AL – – – AH AH AH – – – dH dH dH –––– –––– –––– ++–– ++–– ++–– D4 D7 E3 E4 C5 C6 MOVW A,ext MOVW A,@A MOVW A,@EP MOVW A,EP MOVW EP,#d16 MOVW IX,A MOVW A,IX MOVW SP,A MOVW A,SP MOV @A,T MOVW @A,T MOVW IX,#d16 MOVW A,PS MOVW PS,A MOVW SP,#d16 SWAP SETB dir: b CLRB dir: b XCH A,T XCHW A,T XCHW A,EP XCHW A,IX XCHW A,SP MOVW A,PC 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 (dir) ← (A) ( (IX) +off ) ← (A) (ext) ← (A) ( (EP) ) ← (A) (Ri) ← (A) (A) ← d8 (A) ← (dir) (A) ← ( (IX) +off) (A) ← (ext) (A) ← ( (A) ) (A) ← ( (EP) ) (A) ← (Ri) (dir) ← d8 ( (IX) +off ) ← d8 ( (EP) ) ← d8 (Ri) ← d8 (dir) ← (AH),(dir + 1) ← (AL) ( (IX) +off) ← (AH), ( (IX) +off + 1) ← (AL) (ext) ← (AH), (ext + 1) ← (AL) ( (EP) ) ← (AH),( (EP) + 1) ← (AL) (EP) ← (A) (A) ← d16 (AH) ← (dir), (AL) ← (dir + 1) (AH) ← ( (IX) +off), (AL) ← ( (IX) +off + 1) (AH) ← (ext), (AL) ← (ext + 1) (AH) ← ( (A) ), (AL) ← ( (A) ) + 1) (AH) ← ( (EP) ), (AL) ← ( (EP) + 1) (A) ← (EP) (EP) ← d16 (IX) ← (A) (A) ← (IX) (SP) ← (A) (A) ← (SP) ( (A) ) ← (T) ( (A) ) ← (TH),( (A) + 1) ← (TL) (IX) ← d16 (A) ← (PS) (PS) ← (A) (SP) ← d16 (AH) ↔ (AL) (dir): b ← 1 (dir): b ← 0 (AL) ↔ (TL) (A) ↔ (T) (A) ↔ (EP) (A) ↔ (IX) (A) ↔ (SP) (A) ← (PC) AL AL AL – – – – – – – – – – – – – – – AL AL – – – – AH AH AH – – – – – – – – – – – – – – – – AH – – – – dH dH dH dH – – dH – dH – – – dH – – AL – – – dH dH dH dH dH ++–– ++–– ++–– –––– –––– –––– –––– –––– –––– –––– –––– –––– –––– ++++ –––– –––– –––– –––– –––– –––– –––– –––– –––– –––– C4 93 C7 F3 E7 E2 F2 E1 F1 82 83 E6 70 71 E5 10 A8 to AF A0 to A7 42 43 F7 F6 F5 F0 Note During byte transfer to A, T ← A is restricted to low bytes. Operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (Reverse arrangement of F2MC-8 family) 31 MB89590B/BW Series Table 3 Mnemonic ~ # ADDC A,Ri ADDC A,#d8 ADDC A,dir ADDC A,@IX +off ADDC A,@EP ADDCW A ADDC A SUBC A,Ri SUBC A,#d8 SUBC A,dir SUBC A,@IX +off SUBC A,@EP SUBCW A SUBC A INC Ri INCW EP INCW IX INCW A DEC Ri DECW EP DECW IX DECW A MULU A DIVU A ANDW A ORW A XORW A CMP A CMPW A RORC A 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ROLC A 2 1 CMP A,#d8 CMP A,dir CMP A,@EP CMP A,@IX +off CMP A,Ri DAA DAS XOR A XOR A,#d8 XOR A,dir XOR A,@EP XOR A,@IX +off XOR A,Ri AND A AND A,#d8 AND A,dir 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 Arithmetic Operation Instructions (62 instructions) Operation TL TH AH NZVC OP code – – – – – – – – – – – – – – – – – – – – – – – dL – – – – – – – – – – – – – – – – – – – – – – – – – – – – – 00 – – – – – – – – – – – dH – – – – – – dH – – – – dH – – – dH dH 00 dH dH dH – – – ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ +++– –––– –––– ++–– +++– –––– –––– ++–– –––– –––– ++R– ++R– ++R– ++++ ++++ ++–+ 28 to 2F 24 25 26 27 23 22 38 to 3F 34 35 36 37 33 32 C8 to CF C3 C2 C0 D8 to DF D3 D2 D0 01 11 63 73 53 12 13 03 C ← A← – – – ++–+ 02 (A) − d8 (A) − (dir) (A) − ( (EP) ) (A) − ( (IX) +off) (A) − (Ri) Decimal adjust for addition Decimal adjust for subtraction (A) ← (AL) ∀ (TL) (A) ← (AL) ∀ d8 (A) ← (AL) ∀ (dir) (A) ← (AL) ∀ ( (EP) ) (A) ← (AL) ∀ ( (IX) +off) (A) ← (AL) ∀ (Ri) (A) ← (AL) ∧ (TL) (A) ← (AL) ∧ d8 (A) ← (AL) ∧ (dir) – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– 14 15 17 16 18 to 1F 84 94 52 54 55 57 56 58 to 5F 62 64 65 (A) ← (A) + (Ri) + C (A) ← (A) + d8 + C (A) ← (A) + (dir) + C (A) ← (A) + ( (IX) +off) + C (A) ← (A) + ( (EP) ) + C (A) ← (A) + (T) + C (AL) ← (AL) + (TL) + C (A) ← (A) − (Ri) − C (A) ← (A) − d8 − C (A) ← (A) − (dir) − C (A) ← (A) − ( (IX) +off) − C (A) ← (A) − ( (EP) ) − C (A) ← (T) − (A) − C (AL) ← (TL) − (AL) − C (Ri) ← (Ri) + 1 (EP) ← (EP) + 1 (IX) ← (IX) + 1 (A) ← (A) + 1 (Ri) ← (Ri) − 1 (EP) ← (EP) − 1 (IX) ← (IX) − 1 (A) ← (A) − 1 (A) ← (AL) × (TL) (A) ← (T) / (AL),MOD → (T) (A) ← (A) ∧ (T) (A) ← (A) ∨ (T) (A) ← (A) ∀ (T) (TL) − (AL) (T) − (A) → C→A (Continued) 32 MB89590B/BW Series (Continued) Mnemonic AND A,@EP AND A,@IX +off AND A,Ri OR A OR A,#d8 OR A,dir OR A,@EP OR A,@IX +off OR A,Ri CMP dir,#d8 CMP @EP,#d8 CMP @IX +off,#d8 CMP Ri,#d8 INCW SP DECW SP ~ # Operation 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1 (A) ← (AL) ∧ ( (EP) ) (A) ← (AL) ∧ ( (IX) +off) (A) ← (AL) ∧ (Ri) (A) ← (AL) ∨ (TL) (A) ← (AL) ∨ d8 (A) ← (AL) ∨ (dir) (A) ← (AL) ∨ ( (EP) ) (A) ← (AL) ∨ ( (IX) +off) (A) ← (AL) ∨ (Ri) (dir) – d8 ( (EP) ) – d8 ( (IX) + off) – d8 (Ri) – d8 (SP) ← (SP) + 1 (SP) ← (SP) – 1 Table 4 Mnemonic BZ/BEQ rel BNZ/BNE rel BC/BLO rel BNC/BHS rel BN rel BP rel BLT rel BGE rel BBC dir: b,rel BBS dir: b,rel JMP @A JMP ext CALLV #vct CALL ext XCHW A,PC RET RETI ~ # 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6 2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1 Mnemonic PUSHW A POPW A PUSHW IX POPW IX NOP CLRC SETC CLRI SETI ~ # 4 4 4 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 TH AH NZVC OP code – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++++ ++++ ++++ ++++ –––– –––– 67 66 68 to 6F 72 74 75 77 76 78 to 7F 95 97 96 98 to 9F C1 D1 Branch Instructions (17 instructions) Operation If Z = 1 then PC ← PC + rel If Z = 0 then PC ← PC + rel If C = 1 then PC ← PC + rel If C = 0 then PC ← PC + rel If N = 1 then PC ← PC + rel If N = 0 then PC ← PC + rel If V ∀ N = 1 then PC ← PC + rel If V ∀ N = 0 then PC ← PC + reI If (dir: b) = 0 then PC ← PC + rel If (dir: b) = 1 then PC ← PC + rel (PC) ← (A) (PC) ← ext Vector call Subroutine call (PC) ← (A),(A) ← (PC) + 1 Return from subrountine Return form interrupt Table 5 TL TL TH AH NZVC OP code – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – dH – – –––– –––– –––– –––– –––– –––– –––– –––– –+–– –+–– –––– –––– –––– –––– –––– –––– Restore FD FC F9 F8 FB FA FF FE B0 to B7 B8 to BF E0 21 E8 to EF 31 F4 20 30 Other Instructions (9 instructions) Operation TL TH AH NZVC OP code – – – – – – – – – – – – – – – – – – – dH – – – – – – – –––– –––– –––– –––– –––– –––R –––S –––– –––– 40 50 41 51 00 81 91 80 90 33 L 34 MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R0 A,R0 A,R0 A,R0 R0,A A,R0 A,R0 A,R0 R0,#d8 R0,#d8 dir: 0 dir: 0,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R1 A,R1 A,R1 A,R1 R1,A A,R1 A,R1 A,R1 R1,#d8 R1,#d8 dir: 1 dir: 1,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R2 A,R2 A,R2 A,R2 R2,A A,R2 A,R2 A,R2 R2,#d8 R2,#d8 dir: 2 dir: 2,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R3 A,R3 A,R3 A,R3 R3,A A,R3 A,R3 A,R3 R3,#d8 R3,#d8 dir: 3 dir: 3,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R4 A,R4 A,R4 A,R4 R4,A A,R4 A,R4 A,R4 R4,#d8 R4,#d8 dir: 4 dir: 4,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R5 A,R5 A,R5 A,R5 R5,A A,R5 A,R5 A,R5 R5,#d8 R5,#d8 dir: 5 dir: 5,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R6 A,R6 A,R6 A,R6 R6,A A,R6 A,R6 A,R6 R6,#d8 R6,#d8 dir: 6 dir: 6,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R7 A,R7 A,R7 A,R7 R7,A A,R7 A,R7 A,R7 R7,#d8 R7,#d8 dir: 7 dir: 7,rel 9 A B C D E F A SUBC A XCH A, T XOR A AND A OR A MOV MOV CLRB BBC INCW DECW MOVW MOVW @A,T A,@A dir: 2 dir: 2,rel IX IX IX,A A,IX XOR AND OR DAA A,#d8 A,#d8 A,#d8 DAS R7 R6 R5 R4 R3 R2 R1 R0 DEC DEC DEC DEC DEC DEC DEC DEC R7 R6 R5 R4 R3 R2 R1 R0 rel rel rel rel CALLV BLT #7 rel CALLV BGE #6 rel CALLV BZ #5 CALLV BNZ #4 rel CALLV BN #3 CALLV BP #2 CALLV BC #1 CALLV BNC #0 rel CLRB BBC MOVW MOVW MOVW XCHW dir: 4 dir: 4,rel A,ext ext,A A,#d16 A,PC ADDCW SUBCW XCHW XORW ANDW ORW MOVW MOVW CLRB BBC INCW DECW MOVW MOVW A A A, T A A A @A,T A,@A dir: 3 dir: 3,rel EP EP EP,A A,EP ADDC CLRB BBC INCW DECW MOVW MOVW dir: 1 dir: 1,rel SP SP SP,A A,SP 8 A A SETC MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,@EP A,@EP A,@EP A,@EP @EP,A A,@EP A,@EP A,@EP @EP,#d8 @EP,#d8 dir: 7 dir: 7,rel A,@EP @EP,A EP,#d16 A,EP CMPW CMP JMP CALL PUSHW POPW MOV MOVW CLRC addr16 addr16 IX IX ext,A PS,A 7 F MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,@IX +d A,@IX +d A,@IX +d A,@IX +d @IX +d,A A,@IX +d A,@IX +d A,@IX +d @IX +d,#d8 @IX +d,#d8 dir: 6 dir: 6,rel A,@IX +d @IX +d,A IX,#d16 A,IX E 6 D MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,dir A,dir A,dir A,dir dir,A A,dir A,dir A,dir dir,#d8 dir,#d8 dir: 5 dir: 5,rel A,dir dir,A SP,#d16 A,SP C 5 B CLRB BBC INCW DECW JMP MOVW dir: 0 dir: 0,rel A A @A A,PC A MOV CMP ADDC SUBC A,#d8 A,#d8 A,#d8 A,#d8 A A DIVU SETI 9 4 8 RORC 7 3 6 ROLC A 5 PUSHW POPW MOV MOVW CLRI A A A,ext A,PS 4 2 A RETI 3 MULU RET 2 1 SWAP 1 NOP 0 0 H MB89590B/BW Series ■ INSTRUCTION MAP MB89590B/BW Series ■ ORDERING INFORMATION Part number MB89593BPFV MB89595BPFV MB89P595BPFV MB89593BWPFV MB89595BWPFV MB89P595BWPFV Package Remarks 64-pin plastic LQFP (FPT-64P-M03) 35 MB89590B/BW Series ■ PACKAGE DIMENSION 64-pin plastic LQFP (FPT-64P-M03) Note: Pins width and pins thickness include plating thickness. 12.00±0.20(.472±.008)SQ 10.00±0.10(.394±.004)SQ 48 33 49 32 0.08(.003) Details of "A" part INDEX +0.20 1.50 –0.10 +.008 (Mounting height) .059 –.004 64 17 "A" LEAD No. 1 0.50±0.08 (.020±.003) 0~8° 16 0.18 .007 +0.08 –0.03 +.003 –.001 0.08(.003) M 0.145±0.055 (.006±.002) 0.50±0.20 (.020±.008) 0.45/0.75 (.018/.030) C 0.10±0.10 (.004±.004) (Stand off) 0.25(.010) 1998 FUJITSU LIMITED F64009S-3C-6 Dimensions in mm (inches) 36 MB89590B/BW Series FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3386 http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. 3545 North First Street, San Jose, CA 95134-1804, U.S.A. Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: +1-800-866-8608 Fax: +1-408-922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fujitsu-fme.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220 http://www.fmap.com.sg/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 F0012 FUJITSU LIMITED Printed in Japan All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The contents of this document may not be reproduced or copied without the permission of FUJITSU LIMITED. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. 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