FUJITSU MB90623A

FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13606-1E
16-bit Proprietary Microcontroller
CMOS
F2MC-16L MB90620A Series
MB90622A/623A/P623A
■ DESCRIPTION
The MB90620A series is a line of general-purpose, 16-bit microcontrollers designed for those applications which
require high-speed real-time processing, proving to be suitable for various industrial machines, camera and
video devices, OA equipment, and for process control. The CPU used in this series is the F2MC*-16L. The
instruction set for the F2MC-16L CPU core is designed to be optimized for controller applications while inheriting
the AT architecture of the F2MC-16/16H series, allowing a wide range of control tasks to be processed efficiently
at high speed.
The peripheral resources integrated in the MB90620A series include: the UART (clock asynchronous/
synchronous transfer) × 1 channel, the extended serial I/O interface × 1 channel, the A/D converter (8/10-bit
precision) × 4 channels, the 16-bit PPG timer (PWM/single-shot function) × 2 channels, the 16-bit reload timer
× 3 channels, the 16-bit free-run timer (built-in compare register: 2 channels) × 2 channels, the external interrupt
× 8 channels, the watch timer × 1 channel, LCD controller/driver 32 segments × 4 commons.
*: F2MC stands for FUJITSU Flexible Microcontroller.
■ FEATURES
F2MC-16L CPU
• Minimum execution time: 83.33 ns (at machine clock frequency of 12 MHz)
• Dual-clock control systems
• PLL clock control
(Continued)
■ PACKAGE
100-pin Plastic LQFP
(FPT-100P-M05)
MB90620A Series
(Continued)
• Instruction set optimized for controller applications
Variety of data types: bit, byte, word, long-word
Expanded addressing modes: 23 types
High coding efficiency
Improvement of high-precision arithmetic operations through use of 32-bit accumulator
• Instruction set supports high-level language (C language) and multitasking
Inclusion of system stack pointer
Enhanced pointer-indirect instructions
Barrel shift instruction
• Improved execution speed: 4-byte instruction queue
• 8-level, 32-factor powerful interrupt service functions
• Automatic transfer function independent of CPU (EI2OS)
• General-purpose ports: max. 59 channels
• 18-bit timebase timer/15-bit watch timer
• Watchdog timer function
• CPU intermittent operation function
• Various standby modes
Peripheral blocks
• ROM:32 Kbytes (MB90622A)
48 Kbytes (MB90623A)
• One-time PROM: 48 Kbytes (MB90P623A)
• RAM: 1.64 Kbytes (MB90622A)
2 Kbytes (MB90623A/P623A)
• General-purpose ports: max. 59 channels
• Dual-clock control system
• PLL clock multiplication control system
• UART: 1 channel
Can be used for either asynchronous transfer or synchronous transfer with clock
• Extended serial I/O interface: 1 channel
Can be used for 8-bit synchronous transfer
• A/D converter (8/10-bit resolution): 4 channels
• PPG (Programable pulse generator): 2 channels
• 16-bit reload timer: 3 channels
• 16-bit free-run timer: 2 channels
With compare register 2 channels
• LCD controller/driver
32 segments, 4 commons
• External interrupts: 8 channels
• 18-bit timebase timer
• 15-bit watch timer
• Watchdog timer function
• CPU intermittent operation function
• Standby mode
Watch mode
Sleep mode
Stop mode
2
MB90620A Series
■ PRODUCT LINEUP
Part number
MB90622A
MB90623A
MB90P623A
Parameter
Classification
Mass production products
(Mask ROM products)
One-time model
ROM size
32 Kbytes
48 Kbytes
48 Kbytes
RAM size
1.64 Kbytes
2 Kbytes
2 Kbytes
CPU functions
Oscillation circuit
Number of instructions: 340
Instruction bit length: 8 or 16 bits
Instruction length: 1 to 7 bytes
Data bit length: 1, 4, 8, 16, or 32 bits
Minimum execution time: 83.33 ns at 12 MHz (internal)
Dual-clock system of main clock and sub clock
Ports
Max. 59 channels
I/O ports (CMOS): 17
I/O ports (CMOS) with pull-up resistor available: 24
I/O ports (open drain): 18
UART
Number of channels: 1
Clock synchronous communication (1202 to 9615 bps, full-duplex double buffering)
Clock asynchronous communication (62.5 K to 1 M bps, full-duplex double buffering)
Supports multiprocessor mode
Serial
Number of channels: 1
Internal or external clock mode
Clock synchronous transfer (62.5 kHz to 1 MHz, “LSB first” or “MSB first” transfer)
A/D converter
Resolution: 10 or 8 bits, Number of input channels: 4
Single-conversion mode (conversion for a specified input channel)
Scan conversion mode (continuous conversion for specified consecutive channels)
Continuous conversion mode (repeated conversion for a specified channel)
Stop conversion mode (periodical conversion)
Timer
Free-run timer
PPG timer
Number of channels: 3
16-bit reload timer operation (operation clock: SUB/2, φ/23, φ/25, external)
Number of channels: 2
16-bit up-counter (four types of count clocks)
2 channels on each timer of the compare register (compare matching interrupt available)
Number of channels: 2
PWM function, single-shot function
With external trigger function
LCD controller
/driver
Common output: 4 channels, Segment output: 32 channels
Direct driving of the LCD module
16 bytes of data memory for display
Operation clock source (main clock/sub clock selective)
Standby modes
Stop mode, sleep mode, and watch mode
PLL functions
Package
Main clock multiplication (×1, ×2, ×3 and ×4)
FPT-100P-M05
3
MB90620A Series
■ PIN ASSIGNMENT
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
P21
P20
P17
P16
P15
P14
P13
P12
P11
P10
P07
P06/INT6
P05/INT5
P04/INT4
P03/INT3
P02/INT2
P01/INT1
P00/INT0
V CC
X1
X0
V SS
X0A
X1A
SEG31/P77
(Top view)
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
V2
V3
COM0
COM1
COM2
COM3
AV CC
AVRH
AVRL
AV SS
P50/AN0
P51/AN1
P52/AN2
P53/AN3
V SS
SEG00
SEG01
SEG02
SEG03
SEG04
SEG05
MD0
MD1
MD2
SEG06
P22
P23
P24/SIN0
P25/SOT0
P26/SCK0
P27/CKOT
P30/SIN1
P31/SOT1
V SS
P32/SCK1
P33
P34
P35
P36
P37/TRG/ATG
P40/PPG0
P41/PPG1
P42/INT7/TIO0
P43/TIO1
P44/TIO2
V CC
P45
P46
V0
V1
(FPT-100P-M05)
4
RST
P76/SEG30
P75/SEG29
P74/SEG28
P73/SEG27
P72/SEG26
P71/SEG25
P70/SEG24
P67/SEG23
P66/SEG22
P65/SEG21
P64/SEG20
P63/SEG19
P62/SEG18
P61/SEG17
P60/SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG09
SEG08
SEG07
MB90620A Series
■ PIN DESCRIPTION
Pin no.
Pin name
77
78
X1A
X0A
79
VSS
80
81
X0
X1
82
VCC
83 to 89
P00 to P06
Circuit type
A
(Oscillation)
Crystal oscillator pins (32 kHz)
Power supply Digital circuit power supply (GND) pin
A
(Oscillation)
Crystal/FAR oscillator pins (4 MHz)
Power supply Digital circuit power supply pin
M
(CMOS/H)
INT0 to INT6
90
Function
General-purpose I/O ports
At this pin, a pull-up resistor is added in the input mode depending
on the settings of the pull-up resistor setting register.
External interrupt request input pins
When external interrupts are enabled, these inputs may be used at
any time; therefore, it is necessary to stop output by other functions
on these pins, except when using them for output deliberately.
P07
G
(CMOS)
General-purpose I/O port
At this pin, a pull-up resistor is added in the input mode depending
on the settings of the pull-up resistor setting register.
91 to 98
P10 to P17
G
(CMOS)
General-purpose I/O ports
At this pin, a pull-up resistor is added in the input mode depending
on the settings of the pull-up resistor setting register.
99, 100
1, 2
P20 to P23
G
(CMOS)
General-purpose I/O ports
At this pin, a pull-up resistor is added in the input mode depending
on the settings of the pull-up resistor setting register.
F
(CMOS/H)
General-purpose I/O port
At this pin, a pull-up resistor is added in the input mode depending
on the settings of the pull-up resistor setting register.
3
P24
SIN0
4
P25
UART serial data input pin
During UART input operations, these inputs may be used at any
time; therefore, it is necessary to stop output by other functions on
these pins, except when using them for output deliberately.
G
(CMOS)
SOT0
5
P26
SCK0
General-purpose I/O port
At this pin, a pull-up resistor is added in the input mode depending
on the settings of the pull-up resistor setting register.
UART serial data output pin
This function is available when the UART serial data output is
enabled.
F
(CMOS/H)
General-purpose I/O port
At this pin, a pull-up resistor is added in the input mode depending
on the settings of the pull-up resistor setting register.
UART serial data I/O pin
This function is available when the UART clock output is enabled.
During UART input operations, these inputs may be used at any
time; therefore, it is necessary to stop output by other functions on
these pins, except when using them for output deliberately.
(Continued)
5
MB90620A Series
Pin no.
6
Pin name
P27
Circuit type
Function
G
(CMOS)
General-purpose I/O port
At this pin, a pull-up resistor is added in the input mode depending
on the settings of the pull-up resistor setting register.
CKOT
7
P30
SIN1
8
P31
SOT1
9
VSS
10
P32
SCK1
11 to 14
15
P33 to P36
P37
TRG
Clock output pin
This function is available when clock output is enabled.
E
(CMOS/H)
D
(CMOS)
P40
E
(CMOS/H)
P41
PPG1
General-purpose I/O port
I/O extended serial data output pin
This function is available when serial data data output is enabled.
General-purpose I/O port
I/O extended serial clock I/O pins
This function is available when clock input is enabled.
This pin, as required, is used for input during input operation, and it
is necessary to disable output for other functions from this pin
unless such output is made intentionally.
D
(CMOS)
General-purpose I/O ports
E
(CMOS/H)
General-purpose I/O port
PPG0 and PPG1 external trigger input pin
A/D converter trigger input pin
During A/D converter input operations, these inputs may be used at
any time; therefore, it is necessary to stop output by other functions
on these pins, except when using them for output deliberately.
D
(CMOS)
PPG0
17
I/O extended serial data input pin
This pin, as required, is used for input during input operation, and it
is necessary to disable output for other functions from this pin
unless such output is made intentionally.
Power supply Digital circuit power supply (GND) pin
ATG
16
General-purpose I/O port
General-purpose I/O port
This function is available when PPG timer 0 output is disabled.
PPG timer 0 output pin
This function is available when the PPG timer 0 waveform output is
enabled.
D
(CMOS)
General-purpose I/O port
This function is available when PPG timer 1 output is disabled.
PPG timer 1 output pin
This function is available when the PPG timer 1 waveform output is
enabled.
(Continued)
6
MB90620A Series
Pin no.
18
19
Pin name
P42
Circuit type
L
(CMOS/H)
External interrupt request input pin
When external interrupts are enabled, these inputs may be used at
any time; therefore, it is necessary to stop output by other functions
on these pins, except when using them for output deliberately.
TIO0
Timer input pin
The data on this pin is used as event count signal for timer 0.
Timer output pin
This function is available when the timer output from timer 0 is
enabled.
P43
E
(CMOS/H)
P44
VCC
22, 23
P45, P46
24 to 27
V0 to V3
28 to 31
COM0 to
COM3
General-purpose I/O port
This function is available when the timer output from timer 1 is
disabled.
Timer input pin
The data on this pin is used as event count signal for timer 1.
Timer output pin
This function is available when the timer output from timer 1 is
enabled.
E
(CMOS/H)
TIO2
21
General-purpose I/O port
This function is available when the timer output from timer 0 is
disabled.
INT7
TIO1
20
Function
General-purpose I/O port
This function is available when the timer output from timer 2 is
disabled.
Timer input pin
The data on this pin is used as event count signal for timer 2.
Timer output pin
This function is available when the timer output from timer 2 is
enabled.
Power supply Digital circuit power supply pin
H
(CMOS)
Open-drain I/O ports
Power supply LCDC reference power supply pins
K
LCDC common pins
32
AVCC
Power supply Analog circuit power supply pin
This power supply must only be turned on or off when electric
potential of AVCC or greater is applied to VCC.
33
AVRH
Power supply Analog circuit reference voltage input pin
This pin must only be turned on or off when electric potential of
AVRH or greater is applied to AVCC.
34
AVRL
Power supply Analog circuit reference voltage input pin
35
AVSS
Power supply Analog circuit power supply (GND) pin
(Continued)
7
MB90620A Series
(Continued)
Pin no.
Pin name
36 to 39
P50 to P53
Circuit type
Function
I
(AD)
General-purpose I/O ports
This function is available when “port” is specified in the analog input
enable register.
AN0 to AN3
40
VSS
A/D converter analog input pins
This function is available when the analog input enable register
specification is “AD.”
Power supply Digital circuit power supply (GND) pin
41 to 46
SEG00 to
SEG05
K
47 to 49
MD0 to MD2
50 to 59
SEG06 to
SEG15
K
LCDC segment-only pins
60 to 67
P60 to P67
J
Open-drain I/O ports
This is available when enabled by the LCR2.
C
(CMOS)
SEG16 to
SEG23
68 to 74
P70 to P76
8
Operating mode selection input pins
Connect directly to VCC or VSS.
LCDC segment pins
J
SEG24 to
SEG30
Open-drain I/O ports
This is available when enabled by the LCR2.
LCDC segment pins
75
RST
B
(CMOS/H)
76
P77
J
SEG31
LCDC segment-only pins
External reset request input pin
Open-drain I/O port
This is available when enabled by the LCR2.
LCDC segment pin
MB90620A Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
• Oscillation feedback resistor:
Approximately 1 MΩ
X1 (A)
X0 (A)
Standby control signal
B
• Hysteresis input with pull-up
resistor
C
• CMOS input port
D
• CMOS level input/output
V CC
Digital output
Digital output
V SS
Diffused resistor
CMOS
Standby control signal
E
• CMOS level output
• Hysteresis input
Standby control signal
(Continued)
9
MB90620A Series
Type
Circuit
Remarks
F
Pull-up control
• With input pull-up resistor control
• CMOS level output
• Hysteresis input
Standby control signal
G
Pull-up control
• With input pull-up resistor control
• CMOS level input/output
CMOS
Standby control signal
H
• Open-drain type input/output
CMOS
Standby control signal
I
• CMOS level input/output
• Analog input
Analog input
CMOS
Standby control signal
(Continued)
10
MB90620A Series
(Continued)
Type
Circuit
Remarks
J
• Open-drain type output
• CMOS level input
• Combined with the LCD output
LCD output
LCD output
CMOS
Standby control signal
K
• LCD output pin
LCD output
LCD output
L
• CMOS level output
• Hysteresis input
M
Pull-up controller
• With input pull-up resistor control
• CMOS level output
• Hysteresis input
11
MB90620A Series
■ HANDLING DEVICES
1. Preventing Latchup
Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to the input and output
pins other than medium- and high voltage pins or if higher than the voltage is applied between VCC and VSS.
When latchup occurs, power supply current increases rapidly and might thermally damage elements. When
using, take great care not to exceed the absolute maximum ratings.
2. Treatment of Unused Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down
resistors.
3. External Reset Input
To reset the internal circuit by the Low-level input to the RST pin, the Low-level input to the RST pin must be
maintained for at least five machine cycles. Pay attention to it if the chip uses external clock input.
4. VCC and VSS Pins
Apply equal potential to the VCC and VSS pins.
5. Precautions when Using an External Clock
When an external clock is used, drive X0 pin.
• Using of External Clock
X0, (X0A)
MB90620A
X1, (X1A)
6. Sequence for Applying A/D Converter Power Supply and Analog Inputs
Be sure to turn on the digital power supply (VCC) before applying the A/D converter power supply (AVCC, AVRH,
and AVRL) and the analog inputs (AN0 to AN15).
In addition, when the power is turned off, turn off the A/D converter power supply (AVCC, AVRH, and AVRL) and
the analog inputs (AN0 to AN15) first, and then turn off the digital power supply (AVCC).
Whether applying or cutting off the power, be certain that AVRH does not exceed AVCC.
7. Program Mode
In the MB90P623, all of the bits (48 K × 8 bits) are set to “1” when the IC is shipped from Fujitsu and after
erasure. To input data, program the IC by selectively setting the desired bits to “0”. Bits cannot be set to “1”
electrically.
12
MB90620A Series
8. Recommended Screening Conditions
High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked
OTPROM width microcontroller program.
Program, verify
Aging
+150°C, 48 Hrs.
Data verification
Assembly
9. Programming Yield
All bit cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature.
For this reason, a programming yield of 100% cannot be assured at all times.
13
MB90620A Series
■ PROGRAMMING TO THE EPROM ON THE MB90P623A
In EPROM mode, the MB90P623 EPROM functions equivalent to the MBM27C1000. This allows the PROM to
be programmed with a general-purpose EPROM programmer by using the dedicated socket adapter.
1. EPROM Mode Pin Assignments
• MBM27C1000 compatible pins
MBM27C1000
MB90P623A
MBM27C1000
MB90P623A
Pin no.
Pin name
Pin no.
Pin name
Pin no.
Pin name
Pin no.
Pin name
1
VPP
49
MD2 (VPP)
32
VCC
—
—
2
OE*
10
P32
31
PGM
11
P33
3
A15
98
P17
30
N.C.
—
—
4
A12
95
P14
29
A14
97
P16
5
A07
6
P27
28
A13
96
P15
6
A06
5
P26
27
A08
91
P10
7
A05
4
P25
26
A09
92
P11
8
A04
3
P24
25
A11
94
P13
9
A03
2
P23
24
A16
7
P30
10
A02
1
P22
23
A10
93
P12
11
A01
100
P21
22
CE
8
P31
12
A00
99
P20
21
A07
90
P07
13
D00
83
P00
20
D06
89
P06
14
D01
84
P01
19
D05
88
P05
15
D02
85
P02
18
D04
87
P04
16
GND*
—
—
17
D03
86
P03
* : Connect a capacitance of 20 pF across OE (pin no.2) and GND (pin no.16) pins of the MBM27C1000.
• Power supply, GND connection pins
14
Classification
Pin no.
Pin name
Power supply
21
82
VCC
VCC
GND
9
34
35
40
75
79
12
13
14
VSS
AVRL
AVSS
VSS
RST
VSS
P34
P35
P36
MB90620A Series
• Non-MBM27C1000 compatible pins
Pin no.
47
48
80
78
Pin name
Treatment
Connect a pull-up
resistor of 4.7 kΩ
MD0
MD1
X0
X0A
81
77
28 to 31
41 to 46
50 to 59
X1
X1A
COM0 to COM3
SEG00 to SEG05
SEG06 to SEG15
OPEN
15
16 to 20
22
23
24 to 27
32
33
36 to 39
60 to 74
76
P37
P40 to P44
P45
P46
V0 to V3
AVCC
AVRH
P50 to P53
P60 to p76
P77
Connect a pull-up
resistor of about
1 MΩ to each pin.
2. EPROM Programmer Socket Adapter
Part no.
Package
Compatible socket adapter
Sun Hayato Co., Ltd.
MB90P623APFV
SQFP-100
ROM-100SQF-32DP-16L
Inquiry: Sun Hayato Co., Ltd.: TEL (81)-3-3986-0403
FAX (81)-3-5396-9106
15
MB90620A Series
3. Programming Procedure
(1) Set the EPROM programmer to the MBM27C1000.
(2) Load the program data into the EPROM programmer at 14000H to 1FFFFH.
The ROM addresses from FF4000H to FFFFFFH in operating mode of MB90P623A series correspond to 14000H
to 1FFFFH in EPROM mode.
Operating mode
FFFFFF H
EPROM mode
1FFFF H
EPROM
FF4000H
EPROM
14000H
(3) Insert the MB90P623A in the socket adapter, and mount the socket adapter on the EPROM programmer.
Pay attention to the orientation of the device and of the socket adapter when doing so.
(4) Activate the programming.
(5) If programming cannot be performed successfully, connect a 0.1 µF or similar capacitor between VCC and
GND and between VPP and GND.
Note: Because the mask ROM products (MB90623A) do not have an EPROM mode, they cannot read data from
the EPROM programmer.
16
MB90620A Series
■ BLOCK DIAGRAM
X0, X1
RST
X0A, X1A
MD0 to MD2
6
CPU
F2MC-16L
Clock controller
Interrupt controller
RAM
3
Timer × 3
SIN0
SOT0
SCK0
UART
CKOT
Communication prescaler
F2MC-16L bus
ROM
TIO0 to TIO2
Free-run timer × 2
+
Compare register
2
SIN1
SOT1
SCK1
PPG0, PPG1
TRG
PPG × 2
Extended serial
I/O interface
8
INT0 to INT7
External interrupt
AV cc
2
AVRH, AVRL
AV ss
ATG
4
AN0 to AN3
40
A/D converter
LCD controller/driver
SEG00
to
SEG31
V0 to V3
COM0 to COM3
I/O ports
8
8
8
8
7
4
8
8
P00
to
P07
P10
to
P17
P20
to
P27
P30
to
P37
P40
to
P46
P50
to
P53
P60
to
P67
P70
to
P77
• P00 to P27 (24 channels): Input pull-up resistor setting enable pins
• P45, P46, P60 to P77 (18 channels): Open-drain pins
17
MB90620A Series
■ MEMORY MAP
FFFFFFH
ROM area
Address#1
FF0000H
010000H
ROM area
(FF bank image)
Address#2
: Internal access
004000H
002000H
: No access
Address#3
RAM
Register
000100H
0000C0H
Peripherals
000000H
Product
Address #1
Address #2
Address #3
MB90622A
FF8000H
008000H
000780H
MB90623A
FF4000H
004000H
000900H
MB90P623A
FF4000H
004000H
000900H
Note: While the ROM data image of bank FF can be seen in the upper portion of bank 00, this is done
only to permit effective use of the C compiler’s small model. Because the lower 16 bits of bank FF
address and the lower 16 bits of bank 00 are the same, it is possible to reference tables in ROM
without declaring the “far” specification in the pointer.
18
MB90620A Series
■ I/O MAP
Register
name
Access
000000H Port 0 data register
PDR0
R/W
Port 0
XXXXXXXX
000001H Port 1 data register
PDR1
R/W
Port 1
XXXXXXXX
000002H Port 2 data register
PDR2
R/W
Port 2
XXXXXXXX
000003H Port 3 data register
PDR3
R/W
Port 3
XXXXXXXX
000004H Port 4 data register
PDR4
R/W
Port 4
– XXXXXXX
000005H Port 5 data register
PDR5
R/W
Port 5
– – – – XXXX
000006H Port 6 data register
PDR6
R/W
Port 6
XXXXXXXX
000007H Port 7 data register
PDR7
R/W
Port 7
– XXXXXXX
Address
Register
000008H
to 0FH
Resource
name
Initial value
Vacancy*
000010H Port 0 direction register
DDR0
R/W
Port 0
00000000
000011H Port 1 direction register
DDR1
R/W
Port 1
00000000
000012H Port 2 direction register
DDR2
R/W
Port 2
00000000
000013H Port 3 direction register
DDR3
R/W
Port 3
00000000
000014H Port 4 direction register
DDR4
R/W
Port 4
–0000000
000015H Port 5 direction register
DDR5
R/W
Port 5
––––0000
000016H Port 6 direction register
DDR6
R/W
Port 6
00000000
000017H Port 7 direction register
DDR7
R/W
Port 7
00000000
000018H
to 19H
Vacancy*
00001AH Port 0 pull-up resistor setting register
RDR0
R/W
Port 0
00000000
00001BH Port 1 pull-up resistor setting register
RDR1
R/W
Port 1
00000000
00001CH Port 2 pull-up resistor setting register
RDR2
R/W
Port 2
00000000
00001DH Analog input enable register
ADER
R/W
A/D
––––1111
00001EH Clock output enable register
CKOT
R/W
Clock output (CKOT)
––––0000
Vacancy*
00001FH
000020H Serial mode register
SMR
R/W
000021H Serial control register
SCR
R/W
000022H
Serial input register/
Serial output register
000023H Serial status register
000024H
000025H
Serial mode control status register
000026H Serial data register
SIDR/
SODR
R/W
SSR
R/W
SMCS
R/W
SDR
R/W
00000000
00000100
UART
XXXXXXXX
0001––00
–––00000
Extended serial
I/O interface
00000010
XXXXXXXX
(Continued)
19
MB90620A Series
Register
name
Access
CDCR
R/W
UART, I/O, serial 0 – – – 1 1 1 1
000028H DTP/Interrupt enable register
ENIR
R/W
00000000
000029H DTP/Interrupt source register
EIRR
R/W
ELVR
R/W
Address
000027H
00002AH
00002BH
00002CH
00002DH
00002EH
00002FH
000030H
000031H
000032H
000033H
000034H
000035H
Register
Communication prescaler control
register
Request level setting register
A/D control status register
A/D data register
000039H
00003AH
00003BH
00003CH
00003DH
000041H
000042H
000043H
000044H
000045H
ADCR0
ADCR1
PPG0 duty factor setting register
PDUT0
W
PPG0 control status register
PCNL0
PCNH0
00000000
00000000
00000000
R/W
W
Initial value
00000000
8/10-bit
A/D converter
PCSR0
00000000
XXXXXXXX
0 0 0 0 0 0 XX
XXXXXXXX
XXXXXXXX
16-bit
PPG timer 0
XXXXXXXX
XXXXXXXX
00000000
R/W
0000000–
Vacancy*
PPG1 cycle setting register
PCSR1
W
PPG1 duty factor setting register
PDUT1
W
PPG1 control status register
00003EH,
3FH
000040H
ADCS1
DTP/external
interrupt
R/W
PPG0 cycle setting register
000036H
to 37H
000038H
ADCS0
Resource
name
PCNL1
PCNH1
XXXXXXXX
XXXXXXXX
16-bit
PPG timer 1
XXXXXXXX
XXXXXXXX
00000000
R/W
0000000–
Vacancy*
Timer control status register
TMCSR0
R/W
16-bit timer register
TMR0
R/W
16-bit reload register
TMRLR0
R/W
00000000
––––0000
16-bit
reload timer 0
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
(Continued)
20
MB90620A Series
Address
000046H
000047H
000048H
000049H
00004AH
00004BH
Register
name
Access
TMCSR1
R/W
16-bit timer register 1
TMR1
R/W
16-bit reload register 1
TMRLR1
R/W
Register
Timer control status register 1
00004CH
to 4FH
000050H
Resource
name
Initial value
00000000
––––0000
16-bit
reload timer 1
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
Vacancy*
00000000
TMCSR2
R/W
16-bit timer register 2
TMR2
R/W
16-bit reload register 2
TMRLR2
R/W
Timer data register 0
TCDT0
R
000058H Timer control status register 0
TCS0
R/W
00000000
000059H Compare control status register 0
CCS0
R/W
0000––00
Timer 0 compare register 0
TCR00
R/W
Timer 0 compare register 1
TCR01
R/W
000051H
000052H
000053H
000054H
000055H
000056H
000057H
00005AH
00005BH
00005CH
00005DH
Timer control status register 2
00005EH,
5FH
000060H
––––0000
16-bit
reload timer 2
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
00000000
16-bit free-run
timer 0
00000000
XXXXXXXX
Compare
register block
XXXXXXXX
XXXXXXXX
XXXXXXXX
Vacancy*
00000000
Timer data register 1
TCDT1
R
000062H Timer control status register 1
TCS1
R/W
00000000
000063H Compare control status register 1
CCS1
R/W
0000––00
Timer 1 compare register 0
TCR10
R/W
Timer 1 compare register 1
TCR11
R/W
000061H
000064H
000065H
000066H
000067H
16-bit free-run
timer 1
00000000
XXXXXXXX
Compare
register block
XXXXXXXX
XXXXXXXX
XXXXXXXX
(Continued)
21
MB90620A Series
Address
Register
000068H
to 6FH
Register
name
Access
Resource
name
Initial value
Vacancy*
000070H
LCD display data RAM
to 7FH
VRAM
000080H LCDC control register 0
LCR0
000081H LCDC control register 1
LCR1
LCD controller/
driver
R/W
000082H
to 8FH
Vacancy*
000090H
to 9EH
System reserved area*
00009FH
Delayed interrupt source generation/
release register
0000A0H
Low-power consumption mode control
register
0000A1H Clock selection register
0000A2H
to A7H
XXXXXXXX
R/W
XXXXXXXX
00010000
0––00000
DIRR
R/W
Delayed interrupt
generation module
–––––––0
LPMCR
R/W
00011000
CKSCR
R/W
Low-power
consumption
11111100
Vacancy*
0000A8H Watchdog timer control register
WDTC
R/W
Watchdog timer
XXXXXXXX
0000A9H Timebase timer control register
TBTC
R/W
Timebase timer
1––00000
0000AAH Watch timer control register
WTC
R/W
Watch timer
1 X– 0 0 0 0 0
0000ABH
to AFH
Vacancy*
0000B0H Interrupt control register 00
ICR00
R/W
00000111
0000B1H Interrupt control register 01
ICR01
R/W
00000111
0000B2H Interrupt control register 02
ICR02
R/W
00000111
0000B3H Interrupt control register 03
ICR03
R/W
00000111
0000B4H Interrupt control register 04
ICR04
R/W
00000111
0000B5H Interrupt control register 05
ICR05
R/W
00000111
0000B6H Interrupt control register 06
ICR06
R/W
0000B7H Interrupt control register 07
ICR07
R/W
0000B8H Interrupt control register 08
ICR08
R/W
00000111
0000B9H Interrupt control register 09
ICR09
R/W
00000111
0000BAH Interrupt control register 10
ICR10
R/W
00000111
0000BBH Interrupt control register 11
ICR11
R/W
00000111
0000BCH Interrupt control register 12
ICR12
R/W
00000111
0000BDH Interrupt control register 13
ICR13
R/W
00000111
Interrupt
controller
00000111
00000111
(Continued)
22
MB90620A Series
(Continued)
Register
name
Access
0000BEH Interrupt control register 14
ICR14
R/W
0000BFH Interrupt control register 15
ICR15
R/W
Address
Register
0000C0H
to FFH
Resource
name
Interrupt
controller
Initial value
00000111
00000111
Vacancy*
* : Access prohibited.
Explanation of initial values
0: The initial value of this bit is “0”.
1: The initial value of this bit is “1”.
X: The initial value of this bit is undefined.
–: This bit is not used. No initial value is defined.
23
MB90620A Series
■ INTERRUPT SOURCES AND THEIR INTERRUPT VECTORS AND INTERRUPT
CONTROL REGISTERS
Interrupt source
Interrupt vector
I2OS
support
No.
Address
ICR
Address
Reset
×
#08
08H
FFFFDCH
—
—
INT9 instruction
×
#09
09H
FFFFD8H
—
—
Exception
×
#10
0AH
FFFFD4H
—
—
External interrupt #0
#11
0BH
FFFFD0H
External interrupt #1
#12
0CH
FFFFCCH
ICR00
0000B0H
External interrupt #2
#13
0DH
FFFFC8H
External interrupt #3
#14
0EH
FFFFC4H
ICR01
0000B1H
External interrupt #4
#15
0FH
FFFFC0H
External interrupt #5
#16
10H
FFFFBCH
ICR02
0000B2H
External interrupt #6
#17
11H
FFFFB8H
External interrupt #7
#18
12H
FFFFB4H
ICR03
0000B3H
Extended serial I/O interface
#19
13H
FFFFB0H
ICR04
0000B4H
Free-run timer 0 overflow
#21
15H
FFFFA8H
Free-run timer 1 overflow
#22
16H
FFFFA4H
ICR05
0000B5H
Free-run timer 0 and compare register 0 matched
#23
17H
FFFFA0H
Free-run timer 0 and compare register 1 matched
#24
18H
FFFF9CH
ICR06
0000B6H
Free-run timer 1 and compare register 0 matched
#25
19H
FFFF98H
Free-run timer 1 and compare register 1 matched
#26
1AH
FFFF94H
ICR07
0000B7H
PPG timer #0
#27
1BH
FFFF90H
PPG timer #1
#28
1CH
FFFF8CH
ICR08
0000B8H
16-bit reload timer #0
#29
1DH
FFFF88H
16-bit reload timer #1
#30
1EH
FFFF84H
ICR09
0000B9H
16-bit reload timer #2
#31
1FH
FFFF80H
ICR10
0000BAH
A/D converter measurement complete
#33
21H
FFFF78H
ICR11
0000BBH
ICR12
0000BCH
Watch prescaler
×
#35
23H
FFFF70H
Timebase timer interval interrupt
×
#36
24H
FFFF6CH
UART 0 transmission complete
#37
25H
FFFF68H
ICR13
0000BDH
UART 1 reception complete
#39
27H
FFFF60H
ICR14
0000BEH
#42
2AH
FFFF54H
ICR15
0000BFH
Delayed interrupt generation module
×
: The request flag is cleared by the I2OS interrupt clear signal (without stop requests).
: The request flag is cleared by the I2OS interrupt clear signal (with stop requests).
: The request flag is not cleared by the I2OS interrupt clear signal.
Note: Do not set I2OS startup in an ICRXX that does not support I2OS.
24
Interrupt control
register
MB90620A Series
■ PERIPHERALS
1. Parallel Ports
The MB90620A series has 59 input/output pins.
In the twenty four input/output ports mapped on port 0 to 2, pull-up resistors are selectively added during input
state operations depending on the settings in the resistor setting register.
P45, P46, port 6 and port 7 are open-drain ports.
Port 6 and port 7 are combined with the LCD segment pin function.
(1) Register configuration
Port data register
Address: PDR1
PDR3
PDR5
PDR7
Port data register
Address: PDR0
PDR2
PDR4
PDR6
15
bit
000001H
000003H
000005H
000007H
13
12
11
10
9
8
PD×7
PD×6
PD×5
PD×4
PD×3
PD×2
PD×1
PD×0
7
6
5
4
3
2
1
0
PD×7
PD×6
PD×5
PD×4
PD×3
PD×2
PD×1
PD×0
9
8
bit
000000H
000002H
000004H
000006H
14
PDRx
PDRx
Notes: Bit 7 of port 4 does not have a register bit.
Bit 4 to bit 7 of port 5 does not have a register bit.
Port direction register
Address: DDR1
DDR3
DDR5
DDR7
Port direction register
Address: DDR0
DDR2
DDR4
DDR6
15
bit
000011H
000013H
000015H
000017H
13
12
11
10
DD×7
DD×6
DD×5
DD×4
DD×3
DD×2
DD×1
DD×0
7
6
5
4
3
2
1
0
DD×7
DD×6
DD×5
DD×4
DD×3
DD×2
DD×1
DD×0
bit
000010H
000012H
000014H
000016H
14
DDRx
DDRx
Notes: Bit 7 of port 4 does not have a register bit.
Bit 4 to bit 7 of port 5 does not have a register bit.
Pull-up resistor setting register
bit
15
14
13
12
11
10
9
8
RD×7
RD×6
RD×5
RD×4
RD×3
RD×2
RD×1
RD×0
7
6
5
4
3
2
1
0
RD×7
RD×6
RD×5
RD×4
RD×3
RD×2
RD×1
RD×0
15
14
13
12
11
10
9
8
—
—
—
—
ADE3
ADE2
ADE1
ADE0
Address: 00001BH
RDR1
Pull-up resistor setting register
bit
Address: 00001AH
00001CH
RDR0, RDR2
Analog input enable register
bit
Address: 00001DH
ADER
25
MB90620A Series
(2) Block Diagram
• I/O Port
Internal data bus
Data register read
Pin
Data register
Data register write
Direction register
Direction register write
Direction register read
Internal data bus
• Open-drain Port
RMW
(Read-modify-write
instruction)
Data register read
Pin
Data register
Data register write
• Port combined with the A/D converter functions
Internal data bus
RMW
(Read-modify-write instruction)
Data register read
Data register
Data register write
Direction register
Direction register write
ADER
ADER register write
ADER register read
26
Pin
MB90620A Series
• Port with a pull-up resistor option
Pull-up resistor (Approx. 50 kΩ)
Bus
Data register
Port input/output
Direction register
Resistor register
27
MB90620A Series
2. UART
The UART is a serial I/O port for CLK asynchronous (start-stop synchronization) communications or for CLK
synchronous communications. The features of this module are described below:
• Full-duplex double buffer
• CLK asynchronous (start-stop synchronization) communications and CLK synchronous communications
capable
• Supports multiprocessor mode
• Built-in dedicated baud rate generator
•
•
•
•
CLK asynchronous: 9615, 31250, 4808, 2404, 1202 bps
For a 6, 8, 10, 12, or 16 MHz clock.
CLK synchronous: 1 M, 500K, 250K, 125K, 62.5K bps
Permits setting of any desired baud rate according to an external clock input
Error detection function (parity errors, framing errors, and overrun errors)
NRZ code as transfer signal
Supports Intelligent I/O Service
(1) Register Configuration
bit
7
6
5
4
3
2
1
0
MD1
MD0
CS2
CS1
CS0
15
14
13
12
11
10
9
8
PEN
P
SBL
CL
A/D
REC
RXE
TXE
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
15
14
13
12
11
10
9
8
PE
OPE
FRE
RDRF
TDRE
—
RIE
TIE
15
14
13
12
11
10
9
8
MD
—
—
—
DIV3
DIV2
DIV1
DIV0
Address: 000020H
bit
Reserved SCKE
SOE
Address: 000021H
bit
Address: 000022H
bit
Address: 000023H
bit
Address: 000027H
28
Serial mode register
(SMR)
Serial control register
(SCR)
Serial input register
Serial output register
(SIDR/SODR)
Serial status register
(SSR)
Communication prescaler
control register
(CDCR)
MB90620A Series
(2) Block Diagram
Control signals
Reception interrupt
(to CPU)
Dedicated baud
rate generator
SCK0
16-bit timer 0
(internally connected)
Transmission interrupt
(to CPU)
Transmission clock
Clock selection
circuit
Reception clock
External clock
SIN0
Reception control
circuit
Transmission control
circuit
Start bit detection
circuit
Transmission start
circuit
Reception bit
counter
Transmission bit
counter
Reception parity
counter
Transmission parity
counter
SOT0
Reception status
determination circuit
Reception error
generation signal
for I2OS (to CPU)
Reception shifter
Transmission shifter
Transmission start
Reception end
SODR
SIDR
F2MC-16L bus
SMR
register
MD1
MD0
CS2
CS1
CS0
SCKE
SOE
SCR
register
PEN
P
SBL
CL
A/D
REC
RXE
TXE
SSR
register
PE
ORE
FRE
RDRF
TDRE
RIE
TIE
Control signals
29
MB90620A Series
3. Extended Serial I/O Interface
This block consists of an 8-bit serial I/O interface that can perform clock synchronous data transfer. Either LSBfirst or MSB-first data transfer can be selected. The serial I/O port to be used can also be selected.
The following two serial I/O operation modes are available.
Internal shift clock mode: Data transfer is synchronization with the internal clock.
External shift clock mode: Data transfer is synchronization with the clock input from the external pin (SCK1).
By manipulating the general-purpose port that shares the external pin (SCK1),
this mode also enables the data transfer operation to be driven by CPU
instructions.
(1) Register Configuration
bit
15
14
13
12
11
10
9
8
SMD0
SIE
SIR
BUSY
STOP
STRT
Address: 000025H
SMD2 SMD1
bit
7
6
5
4
3
2
1
0
—
—
—
—
MODE
BDS
SOE
SCOE
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Serial mode control
status register
(SMCS)
Address: 000024H
bit
Address: 000026H
Serial data register
(SDR)
(2) Block Diagram
Internal data bus
D7 to D0 (LSB-first)
(MSB-first) D0 to D7
Transfer direction selection
SIN1
Read
Write
SDR (Serial data register)
SOT1
SCK1
Control circuit
Shift clock counter
Internal clock
2
SMD2
1
SMD1
0
SMD0
SIE
SIR
BUSY
STOP
Interrupt
request
Internal data bus
30
STRT
MODE
BDS
SOE
SCOE
MB90620A Series
4. A/D Converter
The A/D converter converts the analog input voltage into a digital value. The features of this module are as follows:
Conversion time: Minimum of 7 µs per channel (12 MHz machine clock)
RC-type successive approximation conversion method with sample and hold circuit
8-bit/10-bit resolution
Analog input is selectable by software from among 4 channels
A/D conversion mode selectable from the following three:
One-shot conversion mode: Converts a specified channel once.
Continuous conversion mode: Converts a specified channel repeatedly.
Stop conversion mode: Pauses after converting one channel and wait until the next activation (permits
synchronization of start of conversion).
• Conversion mode:
Single-conversion mode: Converts one channel (when the start and stop channels are the same).
Scan conversion mode: Converts several consecutive channels (when the start and stop channels are
different).
• When A/D conversion is completed, an “A/D conversion complete” interrupt request can be issued to the CPU.
Because generating this interrupt can be used to activate the I2OS and transfer the A/D conversion results to
memory, this function is suitable for continuous processing.
• Activation sources can be selected from among software, an external trigger (falling edge), and timer (rising
edge).
•
•
•
•
•
(1) Register Configuration
bit
15
14
13
12
11
10
BUSY
INT
INTE
PAUS
STS1
STS0
7
6
5
4
3
2
9
8
Address: 00002DH
bit
STRT Reserved
1
0
Address: 00002CH
MD1
bit
MD0 Reserved ANS1
ANS0 Reserved ANE1
ANE0
15
14
13
12
11
10
9
8
0
0
0
0
0
0
D9
D8
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
A/D converter control
status register
(ADCS1, ADCS0)
Address: 00002FH
bit
Address: 00002EH
A/D converter data register
(ADCR1, ADCR0)
31
MB90620A Series
(2) Block Diagram
AV CC
AVRH
AVRL AV SS
D/A converter
MPX
AN0
Sequential
comparison register
Input circuit
AN1
AN2
Comparator
Data bus
AN3
Decoder
Sample and
hold circuit
Data register
ADCR1, ADCR0
A/D converter control
status register 0
A/D converter control
status register 1
ATG
Trigger activation
Reload timer 0
Operating clock
φ
32
ADCS1,
ADCS0
Prescaler
MB90620A Series
5. 16-bit Timer (with Event Count Function)
The 16-bit timer consists of a 16-bit down counter, a 16-bit reload register, one input and output pin (TINX,TOTX),
and a control register. Three internal clocks and an external clock can be selected for the input clock. When in
reload mode, a toggled output waveform is output, while in one-shot mode a square wave indicating that the
count is in progress is output pin (TOTX). The input pin (TINX) serves as an event input in event count mode, and
can be used for trigger input or gate input in internal clock mode.
(1) Register Configuration
7
bit
Address: 000040H
: 000046H
: 000050H
6
MOD0 OUTE
bit
Address: 000041H
: 000047H
: 000051H
bit
15
5
4
3
2
1
0
OUTL
RELD
INTE
UF
CNTE
TRG
9
8
15
14
13
12
11
10
—
—
—
—
CSL1
CSL0
Timer control status register
0 to 2
(TMCSR0 to TMCSR2)
MOD2 MOD1
0
Address: 000042H
: 000048H
: 000052H
16-bit timer register 0 to 2
(TMR0 to TMR2)
bit
Address: 000044H
: 00004AH
: 000054H
15
0
16-bit reload register 0 to 2
(TMRLR0 to TMRLR2)
33
MB90620A Series
(2) Block Diagram
16
16-bit reload register
8
Reload
RELD
16-bit down counter
OUTE
UF
16
OUTL
2
OUT
CTL.
F2MC-16L bus
GATE
2
IRQ
UF
CSL1
Clock selector
CNTE
CSL0
TRG
IN CTL.
Port (Tin)
(Tout)
EXCK
φ
φ
φ
2
2
2
1
3
5
3
Prescaler
clear
MOD2
MOD1
Internal clock
MOD0
3
Clear
I2OSCLR
Retrigger
2
34
INTE
MB90620A Series
6. 16-bit Free-run Timer
The 16-bit free-run timer consists of a 16-bit up counter, a control status register, and a compare register.
•
•
•
•
Count clock is selectable from 4 types.
A counter over flow interrupt can be generated.
An interrupt can be generated on matching with the compare register value.
Initialization of the counter on matching with compare register 0 value is enabled depending on the mode
settings.
(1) Register Configuration
bit
Address: 000056H
: 000060H
bit
bit
Address: 000059H
: 000063H
bit
Address: 000058H
: 000062H
bit
Address:
:
:
:
00005AH
00005CH
000064H
000066H
bit
15
14
13
12
11
10
9
8
T15
T14
T13
T12
T11
T10
T09
T08
7
6
5
4
3
2
1
0
T07
T06
T05
T04
T03
T02
T01
T00
15
14
13
12
11
10
9
8
ICP1
ICP0
ICE1
ICE0
—
—
CST1
CST0
7
6
5
4
3
2
1
0
Reserved
IVF
IVFE
STOP
MODE
CLR
CLK1
CLK0
15
14
13
12
11
10
9
8
C15
C14
C13
C12
C11
C10
C09
C08
7
6
5
4
3
2
1
0
C07
C06
C05
C04
C03
C02
C01
C00
Timer data register 0, 1
(TCDT0, TCDT1)
Compare control status
0, 1 register
(CCS0, CCS1)
Timer control status 0, 1
register
(TCS0, TCS1)
Timer 0, 1 compare register
(TCR00, TCR01/
TCR10, TCR11)
35
MB90620A Series
(2) Block Diagram
φ
Interrupt request
IVF
IVFE
STOP
MODE
CLR
CLK1
CLK0
Divider
Bus
Comparator 0
Clock
16-bit up-counter
T00 to T15
Compare match interrupt
Compare register X0
T00 to T15
Compare register X1
36
Compare match interrupt
MB90620A Series
7. 16-bit PPG Timer
This module can output a pulse synchronized with an external trigger or a software trigger. In addition, the cycle
and duty ratio of the output pulse can be changed as desired by overwriting the two 16-bit register values.
PWM function:
Synchronizes pulse with trigger, and permits programming of the pulse output by
overwriting the register values mentioned above.
This function permits use as a D/A converter with the addition of external circuits.
One-shot function: Detects the edge of trigger input, and permits single-pulse output.
(1) Register Configuration
bit
Address: 00035H
: 0003DH
15
14
13
12
CNTE STGR MDSE RTRG
11
10
9
8
CKS1
CKS0
PGMS
—
7
6
5
4
3
2
1
0
EGS1
EGS0
IREN
IRQF
IRS1
IRS0
POEN
OSEL
bit
15
14
13
12
11
10
9
8
bit
7
6
5
4
3
2
1
0
bit
Address: 00034H
: 0003CH
PPG0, 1 control status register
(PCNH0, PCNH1)
PPG0, 1 control status register
(PCNL0, PCNL1)
Address: 00031H
: 00039H
PPG0, 1 cycle setting register
(PCSR0, PCSR1)
Address: 00030H
: 00038H
bit
15
14
13
12
11
10
9
8
bit
7
6
5
4
3
2
1
0
Address: 00033H
: 0003BH
Address: 00032H
: 0003AH
PPG0, 1 duty setting register
(PDUT0, PDUT1)
37
MB90620A Series
(2) Block Diagram
PCSR
PDUT
Prescaler
φ/2
φ/8
cmp
Load
ck
φ/32
φ/128
16-bit down-counter
Start
Borrow
PPG mask
S
Q
PPG output
R
Reverse bit
Enable
TRG input
Edge ditection
Software trigger
38
Interrupt
selector
IRQ
MB90620A Series
8. LCD Controller/driver
The LCD controller driver consists of the display controller for generating the segment signal and common signal
according to data set in the display data memory, the segment driver and the common driver capable of directly
driving the LCD panel (Liquid Crystal Display).
Primary functions are as follows;
•
•
•
•
•
•
LCD direct drive function
Common output 4 channels (COM0 to COM3), segment output 32 channels (SEG0 to SEG31)
Built-in 16 bytes of data memory for display
Duty ratio selective from 1/2, 1/3 and 1/4
Driving clock source selective from the main clock (4 MHz) and the sub clock (32 kHz)
SEG 16 to SEG 31 can be used as open-drain ports.
(1) Register Configuration
LCD control register
bit
15
8 7
Address: 000080H
: 000081H
0
LCR1
LCR0/LCR1
LCR0
LCD display RAM
Address: 000080H
b3
b2
b1
b0
SEG00
b7
b6
b5
b4
SEG01
b3
b2
b1
b0
SEG02
b7
b6
b5
b4
SEG03
b3
b2
b1
b0
SEG04
b7
b6
b5
b4
SEG05
:
:
:
:
:
:
:
:
b3
b2
b1
b0
SEG16
b7
b6
b5
b4
SEG17
b3
b2
b1
b0
SEG18
b7
b6
b5
b4
SEG19
:
:
:
:
b3
b2
b1
b0
SEG28
b7
b6
b5
b4
SEG29
b3
b2
b1
b0
SEG30
b7
b6
b5
b4
SEG31
COM3
COM2
COM1
COM0
Address: 000080H
Address: 000080H
:
:
Address: 000080H
Address: 000080H
:
Address: 000080H
Address: 000080H
39
MB90620A Series
(2) Block Diagram
4 MHz
Power supply input (V0 to V3)
32 kHz
LCDC control register LCR
Common driver
Timing
controller
Internal bus
Segment driver
32
LCD display RAM (16 bytes)
Controller
40
COM0
COM1
COM2
COM3
AC converter
Prescaler
4
Driver
SEG00
SEG01
SEG02
SEG03
SEG04
•
•
•
•
•
•
•
•
SEG27
SEG28
SEG29
SEG30
SEG31
MB90620A Series
9. DTP/External Interrupt
The DTP (Data Transfer Peripheral) is a peripheral, positioned between peripherals external to the device and
the F2MC-16L CPU, that accepts DMA requests or interrupt requests generated by external peripherals and
transfers them to the F2MC-16L CPU to activate the Intelligent I/O Service or interrupt processing.
In the case of the Intelligent I/O Service, there are two request levels that can be selected: high and low; in the
case of an external interrupt request, there are a total of four request levels that can be selected: high, low, rising
edge and falling edge.
(1) Register Configuration
bit
15
0
Address: 000029H
: 000028H
EIRR
bit
DTP/Interrupt enable register
ENIR
15
0
Address: 00002BH
: 00002AH
Request level setting register
ELVR
(2) Block Diagram
F2MC-16L bus
4
DTP/Interrupt enable register
4
Gate
Source F/F
4
3
Edge detector
Request input
DTP/Interrupt source register
8
Request level setting register
10. Watchdog Timer, Timebase Timer, and Watch Timer Functions
The watchdog timer consists of a 2-bit watchdog counter that uses the carry signal from the 18-bit timebase
timer or the 15-bit watch timer as a clock source, a control register, and a watchdog reset controller.
The timebase timer consists of an 18-bit timer and a circuit that controls interval interrupts. Note that the timebase
timer uses the main clock, regardless of the setting of the MCS bit and SCS bit in CKSCR.
The watch timer consists of a 15-bit timer and a circuit that controls interval interrupts. Note that the watch timer
uses the sub clock, regardless of the setting of the MCS bit and SCS bit in CKSCR.
(1) Register Configuration
bit
Address: 0000A8H
bit
Address: 0000A9H
bit
Address: 0000AAH
7
6
5
4
3
2
1
0
PONR
—
WRST
ERST
SRST
WTE
WT1
WT0
15
14
13
12
11
10
9
8
Reserved
—
—
TBIE
TBOF
TBR
TBC1
TBC0
7
6
5
4
3
2
1
0
WDCS
SCE
WTIE
WTOF
WTR
WTC2
WTC1 WTC0
Watchdog timer control register
(WDTC)
Timebase timer control register
(TBTC)
Watch timer control register
(WTC)
41
MB90620A Series
(2) Block Diagram
Main clock
TBTC
TBC1
Selector
TBC0
212
214
216
219
TBTRES
Clock input
Timebase timer
212
214
216
219
TBR
F2MC-16L bus
TBIE
AND
Q
S
R
TBOF
Timebase
interrupt
WDTC
WT1
Selector
WT0
2-bit counter
OF
CLR
Watchdog reset
generator
CLR
WDGRST
To internal reset
generator
WTE
WTC
AND
SCM
WDCS
SCE
Power-on reset
sub clock stops
S
Q R
WTC2
WTC1
WTC0
Selector
WTR
WTIE
AND
Q
S
R
29
210 213 214 215
210
11
2
Watch timer
212
213
14
2
Clock input
215
WTRES
Sub clock
WTOF
Timer
interrupt
WDTC
PONR
From power-on generation
WRST
42
ERST
RST pin
SRST
From RST bit in
the STBYC register
MB90620A Series
11. Delayed Interrupt Generation Module
The delayed interrupt generation module generates task switching interrupts. This module can be used to
generate/cancel interrupt requests to the F2MC-16L CPU by software.
(1) Register Configuration
bit
Address: 00009FH
15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
R0
Delayed interrupt source
generation/release register
(DIRR)
(2) Block Diagram
F2MC-16L bus
Delayed interrupt source generation/release decoder
Source latch
Interrupt controller
Delayed interrupt generation module
F2MC-16L CPU
WRITE
Other requests
IL
ICR yy
CMP
DDIR
ICR xx
CMP
ILM
INTA
43
MB90620A Series
12. Low-power Consumption Controller (CPU Intermittent Operation Function, Oscillation
Stabilization Delay Time, Clock Multiplier Function)
The following are the operating modes: PLL clock mode, PLL sleep mode, PLL watch mode, Pseudo-watch
mode, main clock mode, main sleep mode, main watch mode, main stop mode, sub clock mode, sub sleep
mode, sub watch mode, sub stop mode, and hardware standby mode. Aside from the PLL clock mode, all of
the other operating modes are low-power consumption modes.
In main clock mode and main sleep mode, the main clock (main OSC oscillation clock) and the sub clock (sub
OSC oscillation clock) operate. In these modes, the main clock divided by 2 is used as the operation clock, the
sub clock (sub OSC oscillation clock) is used as the timer clock, and the PLL clock (VCO oscillation clock) is
stopped.
In sub clock mode and sub sleep mode, only the sub clock operates. In these modes, the sub clock is used as
the operation clock, and the main clock and PLL clock are stopped.
In PLL sleep mode and main sleep mode, only the CPU’s operation clock is stopped; all clocks other than the
CPU clock operate.
In Pseudo-watch mode, only the watch timer and timebase timer operate.
In PLL watch mode, main watch mode, and sub watch mode, only the watch timer operates. In this mode, only
the sub clock is used for operation, while the main clock and the PLL clock are stopped (the difference between
the PLL watch mode, the main watch mode and the sub watch mode is that it resumes operation after an interrupt
in the PLL clock mode, the main clock modes and the sub clock mode respectively, and there is no difference
in the watch mode).
The main stop mode, sub stop mode, and hardware standby mode stop oscillation, making it possible to retain
data while consuming the least amount of power. (The difference between the main stop mode and the sub stop
mode is that it resumes operation in the main clock mode and the sub clock mode respectively, and there is no
difference in the stop mode.)
The CPU intermittent operation function intermittently runs the clock supplied to the CPU when accessing
registers, on-chip memory, on-chip resources, and the external bus. Processing is possible with lower power
consumption by reducing the execution speed of the CPU while supplying a hig-speed clock and using on-chip
resources.
The PLL clock multiplier can be selected as either 2, 4, 6, or 8 by setting the CS1 and CS0 bits. These clocks
are divided by 2 to be used as a machine clock.
The WS1 and WS0 bits can be used to set the main clock oscillation stabilization delay time for when stop mode
and hardware standby mode are woken up.
(1) Register Configuration
bit
Address: 0000A0H
bit
Address: 0000A1H
44
7
6
5
4
3
2
1
0
STP
SLP
SPL
RST
TMD
CG1
CG0
SSR
15
14
13
12
11
10
9
8
SCM
MCM
WS1
WS0
SCS
MCS
CS1
CS0
Low-power consumption
mode control register
(LPMCR)
Clock selection register
(CKSCR)
MB90620A Series
(2) Block Diagram
CKSCR
Sub clock
(OSC oscillation)
SCM
Sub clock
SCS
switching control
CKSCR
MCM
MCS
Main clock
(OSC oscillation)
PLL multiplier
circuit
1
2
3
4
CPU
system clock
generation
F2MC-16L bus
CKSCR
1/2 S
CS1
CPU
CS0
Clock selector
CPU clock
0/9/17/33
intermittent cycle selection
LPMCR
CG1
CG0
LPMCR
CPU intermittent
operation function
Cycle count
selection circuit
Peripheral
clock
generation
SCM
SLP
STP
Peripheral clock
SLEEP
Standby
controller
TMD
RST
MSTP
Main OSC stop
STOP
Sub OSC stop
cancel
Interrupt request
or RST
CKSCR
WS1
WS0
Oscillation
stabilization
delay time
selector
24
213
215
218
Clock input
Timebase timer
LPMCR
SPL
Pin high-impedance controller
SSR
Self-refresh control circuit
LPMCR
RST
Internal reset
generator
212 214 216 219
Pin HI-Z
Self-refresh
RST pin
Internal RST
To watchdog timer
WDGRST
45
MB90620A Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(VSS = AVSS = 0.0 V)
Value
Symbol
Parameter
Unit
Min.
Max.
VSS – 0.3
VSS + 7.0
V
VSS – 0.3
VSS + 7.0
V
VSS – 0.3
VSS + 7.0
V
VI
VSS – 0.3
VCC + 0.3
V
Output voltage*
VO
VSS – 0.3
VCC + 0.3
V
“L” level output current
IOL

15
mA
“L” level total output current
ΣIOL

50
mA
“H” level output current
IOH

–4
mA
“H” level total output current
ΣIOH
—
–48
mA
Power consumption
Pd
—
+400
mW
Operating temperature
TA
–40
+85
°C
Storage temperature
TSTG
–55
+150
°C
VCC
CC 1
AV *
Power supply voltage
AVRH*
AVRL
Input voltage*2
2
1
Remarks
*1: AVCC, AVRH and AVRL must not exceed VCC. In addition, AVRL must not exceed AVRH.
*2: VI or VO must not exceed VCC + 0.3 V.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
2. Recommended Operating Conditions
(VSS = AVSS = 0.0 V)
Parameter
Power supply voltage
“H” level input voltage
“L” level input voltage
Operating temperature
Symbol
Value
Unit
Remarks
Min.
Max.
4.0
5.5
V
Normal operation
2.7
5.5
V
Maintaining the stop status
VIH
0.7 VCC
VSS + 0.3
V
Except VIHS
VIHS
0.8 VCC
VSS + 0.3
V
Hysteresis inputs
VIL
VSS – 0.3
0.8
V
Except VILS
VILS
VSS – 0.3
0.2 VCC
V
Hysteresis inputs
TA
–40
+85
°C
VCC
WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All
the device’s electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside
these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representative beforehand.
46
MB90620A Series
3. DC Characteristics
(VCC = 4.0 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Pin
name
Condition
Value
Min.
Typ.
Max.
Unit
Remarks
“H” level output
voltage
VOH
—
VCC = 4.5 V
IOH = –4.0 mA
VCC – 0.5
—
—
V
“L” level output
voltage
VOL
—
VCC = 4.5 V
IOH = –4.0 mA
—
—
0.4
V
Input leakage
current
IIL
—
VCC = 5.5 V
<VSS <VI <VCC
–10
—
10
µA
Pull-up resistor
R
—
22
—
110
kΩ
ICC
—
40
80
mA In 12 MHz operation
ICC
—
30
60
mA In 8 MHz operation
ICC
—
15
40
mA In 4 MHz operation
—
10
40
mA In 12 MHz sleep
ICCL
—
6
10
mA
In 32 KHz sub
operation
ICCT
—
50
200
µA
In 32 KHz watch
mode
ICCH
—
1
10
µA
In stop mode
Power supply
current
—
ICCS
VCC
—
LCD voltage
division resistor
RLCD
—
Between VCC
and V0,
VCC = 5.0 V
300
500
750
kΩ
COM0 to COM3
output impedance
RVCOM
—
V1 – V3 = 5.0
V
—
—
2.5
kΩ
SEG 0 to SEG31
output impedance
RVSEG
—
V1 – V3 = 5.0
V
—
—
15
kΩ
LCD leakage
current
ILCDL
—
—
–10
—
10
µA
Input capacitance
CIN
Except
VCC, VSS
—
—
10
—
pF
Open-drain output
leakage current
Ileak
Opendrain pin
—
—
0.1
10
µA
47
MB90620A Series
4. AC Characteristics
(1) Clock Timing
• When VCC = 4.0 V to 5.5 V
(VCC = 4.0 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
Symbol
Pin name
Condition
Source oscillation
frequency
FC
X0, X1
Source oscillation cycle
time
tC
Frequency fluctuation
ratio*1 (when locked)
Parameter
Value
Unit
Min.
Max.
—
3
24
MHz
X0, X1
—
41.66
333
ns
∆f
—
—
—
3
%
Input clock pulse width
PWH, PWL
X0
—
12
—
ns
Input clock rising/falling
time
tcr, tcf
X0
—
—
5
ns
Internal operating clock
frequency
fCP
—
—
32 K*2
12 M
Hz
Internal operating clock
cycle time
tCP
—
—
83.5
31250
ns
Remarks
Use duty ratio
of 30 to 70%
as a guide
*1: The frequency fluctuation ratio indicates the maximum fluctuation ratio from the set center frequency while
locked with multiply.
∆f =
α
f0
+α
× 100 (%)
Center frequency f 0
–α
*2: 32 KHz operation means sub operation.
• Relationship between Operating Clock Frequency and Power Supply Voltage
V CC [V]
5.5
4.0
f CP [Hz]
32 K
48
12 M
MB90620A Series
• Clock Timing
tC
0.8 V CC
0.2 V CC
P WH
P WL
t cf
t cr
• PLL Operation Assurance Range
Power supply V CC (V)
Relationship between internal operation clock frequency and power supply voltage
5.5
Normal
operation range
PLL operation
assurance range
4.0
2.7
1.5
3
Internal clock
8
12
: Operation assurance range
f CP
(MHz)
: PLL operation assurance range
Relationship between source oscillation frequency,
internal operating clock frequency
Internal clock f CP (MHz)
Multiply by 3 Multiply by 2
Multiply by 1
No multiplier
12
8
4
0
3 4
8
12
16
24
FC
(MHz)
Source oscillation clock FC (MHz)
49
MB90620A Series
(2) Reset Input Timing
(VCC = 4.0 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Reset input time
Pin
Symbol name
tRSTL
Value
Condition
RST
Min.
Max.
4 tC
—
—
Unit
Remarks
ns
t RSTL
RST
0.2Vcc
0.2Vcc
(3) Power-on Reset
(VCC = 4.0 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Pin name Condition
Value
Min.
Max.
Unit
Power supply rising time
tR
VCC
—
—
30
ms
Power supply cut-off time
tOFF
VCC
—
1
—
ms
tR
2.25 V
V CC
0.2 V
If power supply voltage needs to be changed in the course of operation, a smooth voltage rise is
recommended by suppressing the voltage variation as shown below. Also, do not use the PLL clock
when varying the voltage.
However, the supply voltage can be changed when using the PLL clock if the voltage drops by less
than 1 mV/s.
5.0 V
V CC
2.7 V
Hoding RAM data
V SS
50
It is recommended that the rate of
increase in the voltage be kept to
no more than 50 mV/ms.
Remarks
MB90620A Series
(4) UART Timing
(VCC = 4.0 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Pin
name
Serial clock cycle time
tSCYC
—
SCK0 ↓ → SOT0 delay time
tSLOV
—
Valid SIN0 → SCK0 ↑
tIVSH
—
SCK0 ↑ → Valid SIN0 hold time
tSHIX
—
Serial clock “H” pulse width
tSHSL
—
Serial clock “L” pulse width
tSLSH
—
SCK0 ↓ → SOT0 delay time
tSLOV
—
Valid SIN0 → SCK0 ↑
tIVSH
—
SCK0 ↑ → Valid SIN0 hold time
tSHIX
—
Condition
For internal shift
clock mode output
pin,
CL = 80 pF+1 TTL
For external shift
clock mode output
pin,
CL = 80 pF+1 TTL
Value
Unit
Min.
Max.
8 tCP
—
ns
–80
80
ns
100
—
ns
60
—
ns
4 tCP
—
ns
4 tCP
—
ns
—
150
ns
60
—
ns
60
—
ns
Remarks
Notes: • These are the AC characteristics for CLK synchronous mode.
• CL is the load capacitance added to pins during testing.
• tCP is the internal operating clock cycle time (unit: ns).
• The values in the table are target values.
51
MB90620A Series
• Internal Shift Clock Mode
t SCYC
SCK0
2.4 V
0.8 V
0.8 V
t SLOV
2.4 V
SOT0
0.8 V
t IVSH
SIN0
t SHIX
0.8 V CC
0.8 V CC
0.2 V CC
0.2 V CC
• External Shift Clock Mode
t SLSH
SCK0
t SHSL
0.8 V CC
0.8 V CC
0.2 V CC
0.2 V CC
t SLOV
SOT0
2.4 V
0.8 V
t IVSH
SIN0
52
t SHIX
0.8 V CC
0.8 V CC
0.2 V CC
0.2 V CC
MB90620A Series
(5) Extended Serial I/O Timing
(VCC = 4.0 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Pin
Symbol name
Value
Condition
Min.
Max.
Unit
Serial clock cycle time
tSCYC
—
—
8 tXMCYL
—
ns
SCK1 ↓ → SOT1 delay time
tSLOV
—
VCC = 5.0 V ±10%
—
80
ns
Valid SIN1 → SCK1 ↑
tIVSH
—
—
1 tXMCYL
—
ns
SCK1 ↑ → Valid SIN1 hold time tSHIX
—
—
1 tXMCYL
—
ns
Serial clock “H” pulse width
tSHSL
—
VCC = 5.0 V ±10%
230
—
ns
Serial clock “L” pulse width
tSLSH
—
VCC = 5.0 V ±10%
230
—
ns
SCK1 ↓ → SOT1 delay time
tSLOV
—
—
2 tXMCYL
—
ns
Valid SIN1 → SCK1 ↑
tIVSH
—
—
1 tXMCYL
—
ns
SCK1 ↑ → Valid SIN1 hold time tSHIX
—
—
1 tXMCYL
—
ns
Remarks
For internal shift
clock mode
output pin,
CL = 80 pF+1 TTL
For external shift
clock mode
output pin,
CL = 80 pF
Max. 2 MHz
Notes: • CL is the load capacitance added to pins during testing.
• tXMCYL is the internal operation clock cycle time (unit: ns).
• Internal Shift Clock Mode
t SCYC
SCK1
2.4 V
0.8 V
0.8 V
t SLOV
2.4 V
SOT1
0.8 V
t IVSH
SIN1
t SHIX
0.8 V CC
0.8 V CC
0.2 V CC
0.2 V CC
• External Shift Clock Mode
t SLSH
SCK1
t SHSL
0.8 V CC
0.8 V CC
0.2 V CC
0.2 V CC
t SLOV
SOT1
2.4 V
0.8 V
t IVSH
SIN1
t SHIX
0.8 V CC
0.8 V CC
0.2 V CC
0.2 V CC
53
MB90620A Series
(6) Timer Input Timing
(VCC = 4.0 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Input pulse width
Symbol
tTIWH
tTIWL
Pin name
Condition
TIO0 to TIO2
—
0.8 V CC
Value
Min.
Max.
4 tCP
—
Unit
Remarks
ns
0.8 V CC
0.2 V CC
0.2 V CC
t TIWH
t TIWL
(7) Trigger Input Timing
(VCC = 4.0 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Trigger input width
Symbol
tTRWH
tTRWL
Pin name
ADT
TRG
0.8 V CC
Condition
—
Value
Min.
Max.
4 tCP
—
ns
0.8 V CC
0.2 V CC
t TRWH
54
Unit
0.2 V CC
t TRWL
Remarks
A/D trigger
MB90620A Series
5. A/D Converter Electrical Characteristics
(AVCC = VCC = +2.7 V to 5.5 V, AVSS = VSS = 0.0 V, +2.7 V ≤ AVRH – AVRL, TA = –40°C to +85°C)
Parameter
Resolution
Symbol
Pin name
—
—
Value
Min.
Typ.
Max.
—
10
10
Unit
bit
Total error
—
—
—
—
±3.0
LSB
Linearity error
—
—
—
—
±1.5
LSB
Differential linearity error
—
—
—
—
±1.5
LSB
Zero transition voltage
VOT
AN0 to AN3
–1.5
+0.5
+2.5
LSB
Full-scale transition voltage
VFST
AN0 to AN3
AVRH – 3.5
AVRL – 1.5
AVRH + 0.5
LSB
Conversion time
—
—
8.16
—
—
µs
Analog port input current
IAIN
AN0 to AN3
—
—
10
µA
Analog input voltage
VAIN
AN0 to AN3
AVRL
—
AVRH
V
Reference voltage
Power supply current
Reference voltage supply current
Interchannel disparity
—
AVRH
AVRL
—
AVCC
V
—
AVRL
—
—
AVRH
V
IA
AVCC
—
5
—
mA
IAH
AVCC
—
—
5*
µA
IR
AVCC
—
200
—
µA
IRH
AVCC
—
—
5*
µA
—
AN0 to AN3
—
—
4
LSB
* : Current when the A/D converter is not operating and the CPU is stopped (when VCC = AVCC = AVRH = +5.5 V)
Notes: • The smaller | AVRH – AVRL |, the greater the error would become relatively.
• The output impedance of the external circuit for the analog input must satisfy the following conditions:
The output impedance of the external circuit should be less than approximately 7 kΩ.
• If the output impedance of the external circuit is too high, an analog voltage sampling time might be
insufficient (sampling time = 5 µs @ at a machine clock of 12 MHz).
• Analog Input Circuit Model Diagram
C0
Analog input
Comparator
R ON0
R ON1
R ON0 = Approx. 1.5 kΩ (5.0 V)
R ON1 = Approx. 1.0 kΩ (5.0 V)
C 0 = Approx. 60 pF (5.0 V)
C 1 = Approx. 4 pF (5.0 V)
C1
Note: Use the values shown as guides only.
55
MB90620A Series
6. A/D Converter Glossary
• Resolution
Analog changes that are identifiable with the A/D converter.
If the resolution is 10 bits, the analog voltage can be resolved into 210 = 1024 steps.
• Total error
The deviation between the actual and logic value attributable to offset error, gain error, non-linearity error, and
noise.
• Linearity error
The deviation between the actual conversion characteristic of the device and the line linking the zero transition
point (“00 0000 0000” ↔ “00 0000 0001”) and the full scale transition point (“11 1111 1110” ↔ “11 1111 1111”).
• Differential linearity error
The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value
Digital output
11 1111 1111
11 1111 1110
•
•
•
(1 LSB × N + V OT)
•
•
•
•
•
•
•
Linearity error
•
00 0000 0010
00 0000 0001
00 0000 0000
Analog input
V OT
1 LSB =
V NT V (N+1)T
V FST – V OT
1022
Linearity error =
V NT – (1 LSB × N + V OT )
1 LSB
Differential linearity error =
56
[LSB]
V(N + 1)T – V NT
– 1 [LSB]
1 LSB
V FST
MB90620A Series
■ EXAMPLE CHARACTERISTICS
Power supply current vs temperature characteristics example
MB90623A/622A
Current consumption characteristics example
60
PLL Stop
External oscillator: 8 MHz (Internal 4 MHz)
Power supply voltage: 5.0 V
Current value (mA)
50
40
30
20
10
0
–40
25
85
Temperature (°C)
Power supply current vs temperature characteristics example
MB90623A/622A
Current consumption characteristics example
60
PLL Stop
External oscillator: 16 MHz (Internal 8 MHz)
Power supply voltage: 5.0 V
Current value (mA)
50
40
30
20
10
0
25
Temperature (°C)
–40
85
Power supply current vs temperature characteristics example
60
MB90623A/622A
Current consumption characteristics example
PLL Stop
External oscillator: 24 MHz (Internal 12 MHz)
Power supply voltage: 5.0 V
Current value (mA)
50
40
30
20
10
0
–40
25
85
Temperature (°C)
(Continued)
57
MB90620A Series
Operation frequency vs power supply current characteristics example
MB90623A/622A
Current consumption characteristics example
60
PLL Stop
External oscillator/2 = Internal frequency
Power supply voltage: 5.0 V
Temperature: 25°C
Current value (mA)
50
40
30
20
10
0
12
8
4
Internal frequency (MHz)
Sleep mode power supply current characteristics example
Sleep mode
current consumption characteristics example
8
External oscillator: 4 MHz
Temperature: 25°C
Current value (mA)
7
6
5
4
3
2
1
0
4.0
5.0
4.5
5.5
Power supply voltage (V)
Power supply voltage vs power supply current characteristics example
Power supply voltage vs power
supply current characteristics example
60
Power supply current (mA)
Temperature: 25°C
50
40
EXT24 MHz (Internal 12 MHz)
EXT20 MHz (Internal 10 MHz)
30
EXT16 MHz (Internal 8 MHz)
20
EXT 8 MHz (Internal 4 MHz)
10
0
4.0
4.5
5.0
5.5
Power supply voltage (V)
(Continued)
58
MB90620A Series
Sub operation mode power supply current characteristics example
Sub operation mode
current consumption characteristics example
10
9
Operation frequency: 32 KHz
Temperature: 25°C
Current value (mA)
8
7
6
5
4
3
2
1
0
4.0
5.0
4.5
5.5
Power supply voltage (V)
Watch mode power supply current characteristics example
Watch mode
current consumption characteristics example
16
Operation frequency: 32 KHz
Temperature: 25°C
Current value (mA)
14
12
10
8
6
4
2
0
4.0
5.0
4.5
5.5
Power supply voltage (V)
Power supply current characteristics during PLL operation
Power supply current characteristics
during PLL operation
Power supply current (mA)
60
Oscillation frequency: 4 MHz
Temperature: 25°C
50
40
Multiply by 3 (Internal 12 MHz)
30
Multiply by 2 (Internal 8 MHz)
20
Multiply by 1 (Internal 4 MHz)
10
0
4.0
4.5
5.0
5.5
Power supply voltage (V)
(Continued)
59
MB90620A Series
(Continued)
Pseudo-watch mode power supply current characteristics example
Pseudo-watch mode current consumption
characteristics example
2.00
Oscillation frequency: main 4 MHz
sub 32 KHz
Temperature: 25°C
1.80
Current value (mA)
1.60
1.40
1.20
1.00
0.80
0.60
0.40
0.20
0.00
5.0
4.5
4.0
5.5
Power supply voltage (V)
CPU intermittent mode power supply current characteristics
CPU intermittent mode
power supply current characteristics
Power supply current (mA)
30
Power supply voltage: 5.0 V
Temperature: 25°C
25
20
15
Oscillation 6 MHz
Oscillation 4 MHz
Oscillation 2 MHz
10
5
0
None
Interval (1/3)
Interval (1/6)
Power supply voltage (V)
60
Interval (1/9)
MB90620A Series
■ INSTRUCTIONS (340 INSTRUCTIONS)
Table 1
Explanation of Items in Tables of Instructions
Item
Mnemonic
Meaning
Upper-case letters and symbols: Represented as they appear in assembler.
Lower-case letters:
Replaced when described in assembler.
Numbers after lower-case letters: Indicate the bit width within the instruction.
#
Indicates the number of bytes.
~
Indicates the number of cycles.
m : When branching
n : When not branching
See Table 4 for details about meanings of other letters in items.
RG
B
Operation
Indicates the number of accesses to the register during execution of the instruction.
It is used calculate a correction value for intermittent operation of CPU.
Indicates the correction value for calculating the number of actual cycles during execution of the
instruction. (Table 5)
The number of actual cycles during execution of the instruction is the correction value summed
with the value in the “~” column.
Indicates the operation of instruction.
LH
Indicates special operations involving the upper 8 bits of the lower 16 bits of the accumulator.
Z : Transfers “0”.
X : Extends with a sign before transferring.
– : Transfers nothing.
AH
Indicates special operations involving the upper 16 bits in the accumulator.
* : Transfers from AL to AH.
– : No transfer.
Z : Transfers 00H to AH.
X : Transfers 00H or FFH to AH by signing and extending AL.
I
S
T
N
Indicates the status of each of the following flags: I (interrupt enable), S (stack), T (sticky bit),
N (negative), Z (zero), V (overflow), and C (carry).
* : Changes due to execution of instruction.
– : No change.
S : Set by execution of instruction.
R : Reset by execution of instruction.
Z
V
C
RMW
Indicates whether the instruction is a read-modify-write instruction. (a single instruction that
reads data from memory, etc., processes the data, and then writes the result to memory.)
* : Instruction is a read-modify-write instruction.
– : Instruction is not a read-modify-write instruction.
Note: A read-modify-write instruction cannot be used on addresses that have different
meanings depending on whether they are read or written.
61
MB90620A Series
Table 2
Explanation of Symbols in Tables of Instructions
Symbol
A
32-bit accumulator
The bit length varies according to the instruction.
Byte : Lower 8 bits of AL
Word : 16 bits of AL
Long : 32 bits of AL:AH
AH
AL
Upper 16 bits of A
Lower 16 bits of A
SP
Stack pointer (USP or SSP)
PC
Program counter
PCB
Program bank register
DTB
Data bank register
ADB
Additional data bank register
SSB
System stack bank register
USB
User stack bank register
SPB
Current stack bank register (SSB or USB)
DPR
Direct page register
brg1
DTB, ADB, SSB, USB, DPR, PCB, SPB
brg2
DTB, ADB, SSB, USB, DPR, SPB
Ri
R0, R1, R2, R3, R4, R5, R6, R7
RWi
RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7
RWj
RW0, RW1, RW2, RW3
RLi
RL0, RL1, RL2, RL3
dir
Compact direct addressing
addr16
addr24
ad24 0 to 15
ad24 16 to 23
Direct addressing
Physical direct addressing
Bit 0 to bit 15 of addr24
Bit 16 to bit 23 of addr24
io
imm4
imm8
imm16
imm32
ext (imm8)
disp8
disp16
bp
62
Meaning
I/O area (000000H to 0000FFH)
4-bit immediate data
8-bit immediate data
16-bit immediate data
32-bit immediate data
16-bit data signed and extended from 8-bit immediate data
8-bit displacement
16-bit displacement
Bit offset
vct4
vct8
Vector number (0 to 15)
Vector number (0 to 255)
( )b
Bit address
MB90620A Series
(Continued)
Symbol
Meaning
rel
Branch specification relative to PC
ear
eam
Effective addressing (codes 00 to 07)
Effective addressing (codes 08 to 1F)
rlst
Register list
Table 3
Code
00
01
02
03
04
05
06
07
Notation
R0
R1
R2
R3
R4
R5
R6
R7
RW0
RW1
RW2
RW3
RW4
RW5
RW6
RW7
Effective Address Fields
Address format
RL0
(RL0)
RL1
(RL1)
RL2
(RL2)
RL3
(RL3)
Number of bytes in address
extension *
Register direct
“ea” corresponds to byte, word, and
long-word types, starting from the
left
08
09
0A
0B
@RW0
@RW1
@RW2
@RW3
Register indirect
0C
0D
0E
0F
@RW0 +
@RW1 +
@RW2 +
@RW3 +
Register indirect with post-increment
10
11
12
13
14
15
16
17
@RW0 + disp8
@RW1 + disp8
@RW2 + disp8
@RW3 + disp8
@RW4 + disp8
@RW5 + disp8
@RW6 + disp8
@RW7 + disp8
Register indirect with 8-bit
displacement
18
19
1A
1B
@RW0 + disp16
@RW1 + disp16
@RW2 + disp16
@RW3 + disp16
Register indirect with 16-bit
displacement
1C
1D
1E
1F
@RW0 + RW7
@RW1 + RW7
@PC + disp16
addr16
Register indirect with index
Register indirect with index
PC indirect with 16-bit displacement
Direct address
—
0
0
1
2
0
0
2
2
Note: The number of bytes in the address extension is indicated by the “+” symbol in the “#” (number of bytes)
column in the tables of instructions.
63
MB90620A Series
Table 4
Number of Execution Cycles for Each Type of Addressing
(a)
Code
Operand
Number of execution cycles
for each type of addressing
Number of register
accesses for each type of
addressing
Listed in tables of instructions
Listed in tables of instructions
00 to 07
Ri
RWi
RLi
08 to 0B
@RWj
2
1
0C to 0F
@RWj +
4
2
10 to 17
@RWi + disp8
2
1
18 to 1B
@RWj + disp16
2
1
1C
1D
1E
1F
@RW0 + RW7
@RW1 + RW7
@PC + disp16
addr16
4
4
2
1
2
2
0
0
Note: “(a)” is used in the “~” (number of states) column and column B (correction value) in the tables of instructions.
Table 5
Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles
(b) byte
Operand
(c) word
(d) long
Number Number
Number Number
Number Number
of
of
of
of cycles access
of cycles access
of cycles access
Internal register
+0
1
+0
1
+0
2
Internal memory even address
Internal memory odd address
+0
+0
1
1
+0
+2
1
2
+0
+4
2
4
Even address on external data bus (16 bits)
Odd address on external data bus (16 bits)
+1
+1
1
1
+1
+4
1
2
+2
+8
2
4
External data bus (8 bits)
+1
1
+4
2
+8
4
Notes: • “(b)”, “(c)”, and “(d)” are used in the “~” (number of states) column and column B (correction value)
in the tables of instructions.
• When the external data bus is used, it is necessary to add in the number of wait cycles used for ready
input and automatic ready.
Table 6
Correction Values for Number of Cycles Used to Calculate Number of Program Fetch Cycles
Instruction
Byte boundary
Word boundary
Internal memory
—
+2
External data bus (16 bits)
—
+3
External data bus (8 bits)
+3
—
Notes: • When the external data bus is used, it is necessary to add in the number of wait cycles used for ready
input and automatic ready.
• Because instruction execution is not slowed down by all program fetches in actuality, these correction
values should be used for “worst case” calculations.
64
MB90620A Series
Table 7
Mnemonic
Transfer Instructions (Byte) [41 Instructions]
#
~
R
G
B
Operation
L A
H H
I
S T N Z V C RM
W
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVN
A, dir
A, addr16
A, Ri
A, ear
A, eam
A, io
A, #imm8
A, @A
A, @RLi+disp8
A, #imm4
2
3
1
2
2+
2
2
2
3
1
3
4
2
2
3+ (a)
3
2
3
10
1
0
0
1
1
0
0
0
0
2
0
(b)
(b)
0
0
(b)
(b)
0
(b)
(b)
0
byte (A) ← (dir)
byte (A) ← (addr16)
byte (A) ← (Ri)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← (io)
byte (A) ← imm8
byte (A) ← ((A))
byte (A) ← ((RLi)+disp8)
byte (A) ← imm4
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
*
*
*
*
*
*
*
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
R
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
A, dir
A, addr16
A, Ri
A, ear
A, eam
A, io
A, #imm8
A, @A
A,@RWi+disp8
A, @RLi+disp8
2
3
2
2
2+
2
2
2
2
3
3
4
2
2
3+ (a)
3
2
3
5
10
0
0
1
1
0
0
0
0
1
2
(b)
(b)
0
0
(b)
(b)
0
(b)
(b)
(b)
byte (A) ← (dir)
byte (A) ← (addr16)
byte (A) ← (Ri)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← (io)
byte (A) ← imm8
byte (A) ← ((A))
byte (A) ← ((RWi)+disp8)
byte (A) ← ((RLi)+disp8)
X
X
X
X
X
X
X
X
X
X
*
*
*
*
*
*
*
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
/MOV
dir, A
addr16, A
Ri, A
ear, A
eam, A
io, A
@RLi+disp8, A
Ri, ear
Ri, eam
ear, Ri
eam, Ri
Ri, #imm8
io, #imm8
dir, #imm8
ear, #imm8
eam, #imm8
@AL, AH
@A, T
2
3
1
2
2+
2
3
2
2+
2
2+
2
3
3
3
3+
2
3
4
2
2
3+ (a)
3
10
3
4+ (a)
4
5+ (a)
2
5
5
2
4+ (a)
3
0
0
1
1
0
0
2
2
1
2
1
1
0
0
1
0
0
(b)
(b)
0
0
(b)
(b)
(b)
0
(b)
0
(b)
0
(b)
(b)
0
(b)
(b)
byte (dir) ← (A)
byte (addr16) ← (A)
byte (Ri) ← (A)
byte (ear) ← (A)
byte (eam) ← (A)
byte (io) ← (A)
byte ((RLi) +disp8) ← (A)
byte (Ri) ← (ear)
byte (Ri) ← (eam)
byte (ear) ← (Ri)
byte (eam) ← (Ri)
byte (Ri) ← imm8
byte (io) ← imm8
byte (dir) ← imm8
byte (ear) ← imm8
byte (eam) ← imm8
byte ((A)) ← (AH)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
–
–
*
–
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
*
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
XCH
XCH
XCH
XCH
A, ear
A, eam
Ri, ear
Ri, eam
2
2+
2
2+
4
5+ (a)
7
9+ (a)
2
0
4
2
0
2× (b)
0
2× (b)
byte (A) ↔ (ear)
byte (A) ↔ (eam)
byte (Ri) ↔ (ear)
byte (Ri) ↔ (eam)
Z
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
65
MB90620A Series
Table 8
Mnemonic
Transfer Instructions (Word/Long Word) [38 Instructions]
#
~
R
G
B
Operation
L A
H H
I
S T N Z V C RM
W
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
A, dir
A, addr16
A, SP
A, RWi
A, ear
A, eam
A, io
A, @A
A, #imm16
A, @RWi+disp8
A, @RLi+disp8
2
3
1
1
2
2+
2
2
3
2
3
3
4
1
2
2
3+ (a)
3
3
2
5
10
0
0
0
1
1
0
0
0
0
1
2
(c)
(c)
0
0
0
(c)
(c)
(c)
0
(c)
(c)
word (A) ← (dir)
word (A) ← (addr16)
word (A) ← (SP)
word (A) ← (RWi)
word (A) ← (ear)
word (A) ← (eam)
word (A) ← (io)
word (A) ← ((A))
word (A) ← imm16
word (A) ← ((RWi) +disp8)
word (A) ← ((RLi) +disp8)
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
–
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
dir, A
addr16, A
SP, A
RWi, A
ear, A
eam, A
io, A
@RWi+disp8, A
@RLi+disp8, A
RWi, ear
RWi, eam
ear, RWi
eam, RWi
RWi, #imm16
io, #imm16
ear, #imm16
eam, #imm16
2
3
1
1
2
2+
2
2
3
2
2+
2
2+
3
4
4
4+
3
4
1
2
2
3+ (a)
3
5
10
3
4+ (a)
4
5+ (a)
2
5
2
4+ (a)
0
0
0
1
1
0
0
1
2
2
1
2
1
1
0
1
0
(c)
(c)
0
0
0
(c)
(c)
(c)
(c)
(0)
(c)
0
(c)
0
(c)
0
(c)
word (dir) ← (A)
word (addr16) ← (A)
word (SP) ← (A)
word (RWi) ← (A)
word (ear) ← (A)
word (eam) ← (A)
word (io) ← (A)
word ((RWi) +disp8) ← (A)
word ((RLi) +disp8) ← (A)
word (RWi) ← (ear)
word (RWi) ← (eam)
word (ear) ← (RWi)
word (eam) ← (RWi)
word (RWi) ← imm16
word (io) ← imm16
word (ear) ← imm16
word (eam) ← imm16
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
*
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOVW AL, AH
/MOVW @A, T
2
3
0
(c)
word ((A)) ← (AH)
–
–
–
–
–
*
*
–
–
–
XCHW
XCHW
XCHW
XCHW
A, ear
A, eam
RWi, ear
RWi, eam
2
2+
2
2+
4
5+ (a)
7
9+ (a)
2
0
4
2
0
2× (c)
0
2× (c)
word (A) ↔ (ear)
word (A) ↔ (eam)
word (RWi) ↔ (ear)
word (RWi) ↔ (eam)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOVL
MOVL
MOVL
A, ear
A, eam
A, #imm32
2
2+
5
4
5+ (a)
3
2
0
0
0
(d)
0
long (A) ← (ear)
long (A) ← (eam)
long (A) ← imm32
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
MOVL
MOVL
ear, A
eam, A
2
2+
4
5+ (a)
2
0
0
(d)
long (ear) ← (A)
long (eam) ← (A)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
–
–
–
–
–
–
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
66
MB90620A Series
Table 9
Addition and Subtraction Instructions (Byte/Word/Long Word) [42 Instructions]
#
~
R
G
B
ADD
A,#imm8
ADD
A, dir
ADD
A, ear
ADD
A, eam
ADD
ear, A
ADD
eam, A
ADDC
A
ADDC
A, ear
ADDC
A, eam
ADDDC A
SUB
A, #imm8
SUB
A, dir
SUB
A, ear
SUB
A, eam
SUB
ear, A
SUB
eam, A
SUBC
A
SUBC
A, ear
SUBC
A, eam
SUBDC A
2
2
2
2+
2
2+
1
2
2+
1
2
2
2
2+
2
2+
1
2
2+
1
2
5
3
4+ (a)
3
5+ (a)
2
3
4+ (a)
3
2
5
3
4+ (a)
3
5+ (a)
2
3
4+ (a)
3
0
0
1
0
2
0
0
1
0
0
0
0
1
0
2
0
0
1
0
0
0
(b)
0
(b)
0
2× (b)
0
0
(b)
0
0
(b)
0
(b)
0
2× (b)
0
0
(b)
0
ADDW
ADDW
ADDW
ADDW
ADDW
ADDW
ADDCW
ADDCW
SUBW
SUBW
SUBW
SUBW
SUBW
SUBW
SUBCW
SUBCW
A
A, ear
A, eam
A, #imm16
ear, A
eam, A
A, ear
A, eam
A
A, ear
A, eam
A, #imm16
ear, A
eam, A
A, ear
A, eam
1
2
2+
3
2
2+
2
2+
1
2
2+
3
2
2+
2
2+
2
3
4+ (a)
2
3
5+ (a)
3
4+ (a)
2
3
4+ (a)
2
3
5+ (a)
3
4+ (a)
0
1
0
0
2
0
1
0
0
1
0
0
2
0
1
0
0
0
(c)
0
0
2× (c)
0
(c)
0
0
(c)
0
0
2× (c)
0
(c)
A, ear
A, eam
A, #imm32
A, ear
A, eam
A, #imm32
2
2+
5
2
2+
5
6
7+ (a)
4
6
7+ (a)
4
2
0
0
2
0
0
0
(d)
0
0
(d)
0
Mnemonic
ADDL
ADDL
ADDL
SUBL
SUBL
SUBL
L A
H H
I
S T N Z V C RM
W
byte (A) ← (A) +imm8
byte (A) ← (A) +(dir)
byte (A) ← (A) +(ear)
byte (A) ← (A) +(eam)
byte (ear) ← (ear) + (A)
byte (eam) ← (eam) + (A)
byte (A) ← (AH) + (AL) + (C)
byte (A) ← (A) + (ear) + (C)
byte (A) ← (A) + (eam) + (C)
byte (A) ← (AH) + (AL) + (C) (decimal)
byte (A) ← (A) –imm8
byte (A) ← (A) – (dir)
byte (A) ← (A) – (ear)
byte (A) ← (A) – (eam)
byte (ear) ← (ear) – (A)
byte (eam) ← (eam) – (A)
byte (A) ← (AH) – (AL) – (C)
byte (A) ← (A) – (ear) – (C)
byte (A) ← (A) – (eam) – (C)
byte (A) ← (AH) – (AL) – (C) (decimal)
Z
Z
Z
Z
–
Z
Z
Z
Z
Z
Z
Z
Z
Z
–
–
Z
Z
Z
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
*
–
–
–
–
–
–
–
–
–
*
–
–
–
–
word (A) ← (AH) + (AL)
word (A) ← (A) +(ear)
word (A) ← (A) +(eam)
word (A) ← (A) +imm16
word (ear) ← (ear) + (A)
word (eam) ← (eam) + (A)
word (A) ← (A) + (ear) + (C)
word (A) ← (A) + (eam) + (C)
word (A) ← (AH) – (AL)
word (A) ← (A) – (ear)
word (A) ← (A) – (eam)
word (A) ← (A) –imm16
word (ear) ← (ear) – (A)
word (eam) ← (eam) – (A)
word (A) ← (A) – (ear) – (C)
word (A) ← (A) – (eam) – (C)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
*
–
–
–
–
–
–
–
*
–
–
long (A) ← (A) + (ear)
long (A) ← (A) + (eam)
long (A) ← (A) +imm32
long (A) ← (A) – (ear)
long (A) ← (A) – (eam)
long (A) ← (A) –imm32
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
Operation
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
67
MB90620A Series
Table 10
Increment and Decrement Instructions (Byte/Word/Long Word) [12 Instructions]
Mnemonic
#
~
R
G
B
Operation
L A
H H
I
S
T
N
Z
V
C RM
W
INC
INC
ear
eam
2
2
2
0
byte (ear) ← (ear) +1
2+ 5+ (a) 0 2× (b) byte (eam) ← (eam) +1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
DEC
DEC
ear
eam
2
3
2
0
byte (ear) ← (ear) –1
2+ 5+ (a) 0 2× (b) byte (eam) ← (eam) –1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
INCW
INCW
ear
eam
2
3
2
0
word (ear) ← (ear) +1
2+ 5+ (a) 0 2× (c) word (eam) ← (eam) +1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
DECW ear
DECW eam
2
3
2
0
word (ear) ← (ear) –1
2+ 5+ (a) 0 2× (c) word (eam) ← (eam) –1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
INCL
INCL
ear
eam
2
7
4
0
long (ear) ← (ear) +1
2+ 9+ (a) 0 2× (d) long (eam) ← (eam) +1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
DECL
DECL
ear
eam
2
7
4
0
long (ear) ← (ear) –1
2+ 9+ (a) 0 2× (d) long (eam) ← (eam) –1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Table 11
Mnemonic
#
Compare Instructions (Byte/Word/Long Word) [11 Instructions]
~
R
G
B
Operation
L A
H H
I
S
T
N
Z
V
C RM
W
CMP
CMP
CMP
CMP
A
A, ear
A, eam
A, #imm8
1
1
2
2
2+ 3+ (a)
2
2
0
1
0
0
0
0
(b)
0
byte (AH) – (AL)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← imm8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
CMPW
CMPW
CMPW
CMPW
A
A, ear
A, eam
A, #imm16
1
1
2
2
2+ 3+ (a)
3
2
0
1
0
0
0
0
(c)
0
word (AH) – (AL)
word (A) ← (ear)
word (A) ← (eam)
word (A) ← imm16
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
CMPL
CMPL
CMPL
A, ear
A, eam
A, #imm32
2
6
2
2+ 7+ (a) 0
5
3
0
0
(d)
0
word (A) ← (ear)
word (A) ← (eam)
word (A) ← imm32
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
68
MB90620A Series
Table 12
Mnemonic
Multiplication and Division Instructions (Byte/Word/Long Word) [11 Instructions]
#
~
R
G
B
Operation
L A
H H
I
S
T
N
Z
V
C RM
W
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
DIVU
A
1
*1
0
0
DIVU
A, ear
2
*
2
1
0
DIVU
A, eam 2+
*
3
0
6
*
DIVUW
A, ear
*
4
1
0
DIVUW
A, eam 2+
*5
0
7
*
MULU
MULU
MULU
A
1
A, ear
2
A, eam 2+
*8
*9
*10
0
1
0
0 byte (AH) *byte (AL) → word (A)
0 byte (A) *byte (ear) → word (A)
(b) byte (A) *byte (eam) → word (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MULUW
MULUW
MULUW
A
1
A, ear
2
A, eam 2+
*11
*12
*13
0
1
0
0 word (AH) *word (AL) → long (A)
0 word (A) *word (ear) → long (A)
(c) word (A) *word (eam) → long (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*1:
*2:
*3:
*4:
*5:
*6:
*7:
*8:
*9:
*10:
*11:
*12:
*13:
2
word (AH) /byte (AL)
Quotient → byte (AL) Remainder → byte (AH)
word (A)/byte (ear)
Quotient → byte (A) Remainder → byte (ear)
word (A)/byte (eam)
Quotient → byte (A) Remainder → byte (eam)
long (A)/word (ear)
Quotient → word (A) Remainder → word (ear)
long (A)/word (eam)
Quotient → word (A) Remainder → word (eam)
3 when the result is zero, 7 when an overflow occurs, and 15 normally.
4 when the result is zero, 8 when an overflow occurs, and 16 normally.
6 + (a) when the result is zero, 9 + (a) when an overflow occurs, and 19 + (a) normally.
4 when the result is zero, 7 when an overflow occurs, and 22 normally.
6 + (a) when the result is zero, 8 + (a) when an overflow occurs, and 26 + (a) normally.
(b) when the result is zero or when an overflow occurs, and 2 × (b) normally.
(c) when the result is zero or when an overflow occurs, and 2 × (c) normally.
3 when byte (AH) is zero, and 7 when byte (AH) is not zero.
4 when byte (ear) is zero, and 8 when byte (ear) is not zero.
5 + (a) when byte (eam) is zero, and 9 + (a) when byte (eam) is not 0.
3 when word (AH) is zero, and 11 when word (AH) is not zero.
4 when word (ear) is zero, and 12 when word (ear) is not zero.
5 + (a) when word (eam) is zero, and 13 + (a) when word (eam) is not zero.
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
69
MB90620A Series
Table 13
Mnemonic
#
~
Logical 1 Instructions (Byte/Word) [39 Instructions]
R
G
B
Operation
L A
H H
I
S
T
N
Z
V
C RM
W
AND
AND
AND
AND
AND
A, #imm8
A, ear
A, eam
ear, A
eam, A
2
2
2
3
2+ 4+ (a)
2
3
2+ 5+ (a)
0
0
1
0
0
(b)
2
0
0 2× (b)
byte (A) ← (A) and imm8
byte (A) ← (A) and (ear)
byte (A) ← (A) and (eam)
byte (ear) ← (ear) and (A)
byte (eam) ← (eam) and (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
–
–
–
–
–
–
–
–
–
*
OR
OR
OR
OR
OR
A, #imm8
A, ear
A, eam
ear, A
eam, A
2
2
2
3
2+ 4+ (a)
2
3
2+ 5+ (a)
0
0
1
0
0
(b)
2
0
0 2× (b)
byte (A) ← (A) or imm8
byte (A) ← (A) or (ear)
byte (A) ← (A) or (eam)
byte (ear) ← (ear) or (A)
byte (eam) ← (eam) or (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
–
–
–
–
–
–
–
–
–
*
XOR
XOR
XOR
XOR
XOR
A, #imm8
A, ear
A, eam
ear, A
eam, A
2
2
2
3
2+ 4+ (a)
2
3
2+ 5+ (a)
0
0
1
0
0
(b)
2
0
0 2× (b)
byte (A) ← (A) xor imm8
byte (A) ← (A) xor (ear)
byte (A) ← (A) xor (eam)
byte (ear) ← (ear) xor (A)
byte (eam) ← (eam) xor (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
–
–
–
–
–
–
–
–
–
*
NOT
NOT
NOT
A
ear
eam
1
2
0
0
byte (A) ← not (A)
2
3
2
0
byte (ear) ← not (ear)
2+ 5+ (a) 0 2× (b) byte (eam) ← not (eam)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
R
R
R
–
–
–
–
–
*
ANDW
ANDW
ANDW
ANDW
ANDW
ANDW
A
1
2
A, #imm16 3
2
A, ear
2
3
A, eam
2+ 4+ (a)
ear, A
2
3
eam, A
2+ 5+ (a)
0
0
0
0
1
0
0
(c)
2
0
0 2× (c)
word (A) ← (AH) and (A)
word (A) ← (A) and imm16
word (A) ← (A) and (ear)
word (A) ← (A) and (eam)
word (ear) ← (ear) and (A)
word (eam) ← (eam) and (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
–
*
ORW
ORW
ORW
ORW
ORW
ORW
A
1
2
A, #imm16 3
2
A, ear
2
3
A, eam
2+ 4+ (a)
ear, A
2
3
eam, A
2+ 5+ (a)
0
0
0
0
1
0
0
(c)
2
0
0 2× (c)
word (A) ← (AH) or (A)
word (A) ← (A) or imm16
word (A) ← (A) or (ear)
word (A) ← (A) or (eam)
word (ear) ← (ear) or (A)
word (eam) ← (eam) or (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
–
*
XORW
XORW
XORW
XORW
XORW
XORW
A
1
2
A, #imm16 3
2
A, ear
2
3
A, eam
2+ 4+ (a)
ear, A
2
3
eam, A
2+ 5+ (a)
0
0
0
0
1
0
0
(c)
2
0
0 2× (c)
word (A) ← (AH) xor (A)
word (A) ← (A) xor imm16
word (A) ← (A) xor (ear)
word (A) ← (A) xor (eam)
word (ear) ← (ear) xor (A)
word (eam) ← (eam) xor (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
R
R
R
–
–
–
–
–
*
NOTW A
NOTW ear
NOTW eam
1
2
0
0
word (A) ← not (A)
2
3
2
0
word (ear) ← not (ear)
2+ 5+ (a) 0 2× (c) word (eam) ← not (eam)
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
70
MB90620A Series
Table 14
Logical 2 Instructions (Long Word) [6 Instructions]
#
R
G
B
Operation
ANDL A, ear
ANDL A, eam
2
6
2
2+ 7+ (a) 0
0
(d)
ORL
ORL
A, ear
A, eam
2
6
2
2+ 7+ (a) 0
XORL A, ea
XORL A, eam
2
6
2
2+ 7+ (a) 0
Mnemonic
~
Table 15
Mnemonic
L A
H H
I
S
T
N
Z
V
C RM
W
long (A) ← (A) and (ear)
long (A) ← (A) and (eam)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
0
(d)
long (A) ← (A) or (ear)
long (A) ← (A) or (eam)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
0
(d)
long (A) ← (A) xor (ear)
long (A) ← (A) xor (eam)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
Sign Inversion Instructions (Byte/Word) [6 Instructions]
#
~
R
G
B
Operation
2
0
0
byte (A) ← 0 – (A)
NEG
A
1
NEG
NEG
ear
eam
2
3
2
0
byte (ear) ← 0 – (ear)
2+ 5+ (a) 0 2× (b) byte (eam) ← 0 – (eam)
2
0
1
NEGW ear
NEGW eam
2
3
2
0
word (ear) ← 0 – (ear)
2+ 5+ (a) 0 2× (c) word (eam) ← 0 – (eam)
Table 16
Mnemonic
NRML A, R0
0
word (A) ← 0 – (A)
NEGW A
L A
H H
I
S
T
N
Z
V
C RM
W
X
–
–
–
–
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
*
–
–
–
–
–
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
*
Normalize Instruction (Long Word) [1 Instruction]
#
~
RG
B
2
*1
1
0
Operation
long (A) ← Shift
until first digit
L A
H H
I
S
T
N
Z
V
C RM
W
–
–
–
–
–
*
–
–
–
–
is “1”
byte (R0) ← Current
shift count
*1: 4 when the contents of the accumulator are all zeroes, 6 + (R0) in all other cases (shift count).
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
71
MB90620A Series
Table 17
Shift Instructions (Byte/Word/Long Word) [18 Instructions]
#
~
R
G
B
RORC A
ROLC A
2
2
2
2
0
0
0
0
RORC
RORC
ROLC
ROLC
ear
eam
ear
eam
2
3
2+ 5+ (a)
2
3
2+ 5+ (a)
2
0
2
0
0
2× (b)
0
2× (b)
ASR
LSR
LSL
A, R0
A, R0
A, R0
2
2
2
*1
*1
*1
1
1
1
ASRW A
LSRW A/SHRW A
LSLW A/SHLW A
1
1
1
2
2
2
ASRW A, R0
LSRW A, R0
LSLW A, R0
2
2
2
ASRL
LSRL
LSLL
2
2
2
Mnemonic
A, R0
A, R0
A, R0
L A
H H
I
S T N Z V C RM
W
byte (A) ← Right rotation with carry
byte (A) ← Left rotation with carry
–
–
–
–
–
–
–
–
–
–
*
*
*
*
–
–
*
*
–
–
byte (ear) ← Right rotation with carry
byte (eam) ← Right rotation with carry
byte (ear) ← Left rotation with carry
byte (eam) ← Left rotation with carry
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
–
–
*
*
*
*
–
*
–
*
0
0
0
byte (A) ← Arithmetic right barrel shift (A, R0)
byte (A) ← Logical right barrel shift (A, R0)
byte (A) ← Logical left barrel shift (A, R0)
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
0
0
0
0
0
0
word (A) ← Arithmetic right shift (A, 1 bit)
word (A) ← Logical right shift (A, 1 bit)
word (A) ← Logical left shift (A, 1 bit)
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
R
*
*
*
*
–
–
–
*
*
*
–
–
–
*1
*1
*1
1
1
1
0
0
0
word (A) ← Arithmetic right barrel shift (A, R0)
word (A) ← Logical right barrel shift (A, R0)
word (A) ← Logical left barrel shift (A, R0)
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
*2
*2
*2
1
1
1
0
0
0
long (A) ← Arithmetic right shift (A, R0)
long (A) ← Logical right barrel shift (A, R0)
long (A) ← Logical left barrel shift (A, R0)
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
Operation
*1: 6 when R0 is 0, 5 + (R0) in all other cases.
*2: 6 when R0 is 0, 6 + (R0) in all other cases.
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
72
MB90620A Series
Table 18
Mnemonic
BZ/BEQ
BNZ/BNE
BC/BLO
BNC/BHS
BN
rel
BP
rel
BV
rel
BNV
rel
BT
rel
BNT
rel
BLT
rel
BGE
rel
BLE
rel
BGT
rel
BLS
rel
BHI
rel
BRA
rel
rel
rel
rel
rel
L A
H H
I
S T N Z V C RM
W
Branch when (Z) = 1
Branch when (Z) = 0
Branch when (C) = 1
Branch when (C) = 0
Branch when (N) = 1
Branch when (N) = 0
Branch when (V) = 1
Branch when (V) = 0
Branch when (T) = 1
Branch when (T) = 0
Branch when (V) xor (N) = 1
Branch when (V) xor (N) = 0
Branch when ((V) xor (N)) or (Z) = 1
Branch when ((V) xor (N)) or (Z) = 0
Branch when (C) or (Z) = 1
Branch when (C) or (Z) = 0
Branch unconditionally
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
word (PC) ← (A)
word (PC) ← addr16
word (PC) ← (ear)
word (PC) ← (eam)
word (PC) ← (ear), (PCB) ← (ear +2)
word (PC) ← (eam), (PCB) ← (eam +2)
word (PC) ← ad24 0 to 15,
(PCB) ← ad24 16 to 23
word (PC) ← (ear)
word (PC) ← (eam)
word (PC) ← addr16
Vector call instruction
word (PC) ← (ear) 0 to 15
(PCB) ← (ear) 16 to 23
word (PC) ← (eam) 0 to 15
(PCB) ← (eam) 16 to 23
word (PC) ← addr0 to 15,
(PCB) ← addr16 to 23
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
#
~
RG
B
Operation
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
2
0
0
0
0
0
(c)
0
(d)
0
1
0
0
0
2
(c)
2× (c)
(c)
2× (c)
2× (c)
0
*2
0
2× (c)
JMP
JMP
JMP
JMP
JMPP
JMPP
JMPP
@A
addr16
@ear
@eam
@ear *3
@eam *3
addr24
1
3
2
2+
2
2+
4
CALL
CALL
CALL
CALLV
CALLP
@ear *4
@eam *4
addr16 *5
#vct4 *5
@ear *6
2
2+
3
1
2
CALLP
@eam *6
2+
CALLP
addr24 *7
4
*1:
*2:
*3:
*4:
*5:
*6:
*7:
Branch 1 Instructions [31 Instructions]
2
3
3
4+ (a)
5
6+ (a)
4
6
7+ (a)
6
7
10
11+ (a)
10
4 when branching, 3 when not branching.
(b) + 3 × (c)
Read (word) branch address.
W: Save (word) to stack; R: read (word) branch address.
Save (word) to stack.
W: Save (long word) to W stack; R: read (long word) R branch address.
Save (long word) to stack.
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
73
MB90620A Series
Table 19
Mnemonic
Branch 2 Instructions [19 Instructions]
#
~ RG
B
CBNE
A, #imm8, rel
CWBNE A, #imm16, rel
3
4
*1
*1
0
0
0
0
CBNE
CBNE
CWBNE
CWBNE
ear, #imm8, rel
eam, #imm8, rel*9
ear, #imm16, rel
eam, #imm16, rel*9
4
4+
5
5+
*2
*3
*4
*3
1
0
1
0
0
(b)
0
(c)
DBNZ
ear, rel
3
*5
2
0
L A
H H
I
S
T
N
Z
V
C RM
W
Branch when byte (A) ≠ imm8
Branch when word (A) ≠ imm16
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
Branch when byte (ear) ≠ imm8
Branch when byte (eam) ≠ imm8
Branch when word (ear) ≠ imm16
Branch when word (eam) ≠ imm16
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
*
*
*
–
*
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
*
*
*
–
*
Software interrupt
Software interrupt
Software interrupt
Software interrupt
Return from interrupt
–
–
–
–
–
–
–
–
–
–
R
R
R
R
*
S
S
S
S
*
–
–
–
–
*
–
–
–
–
*
–
–
–
–
*
–
–
–
–
*
–
–
–
–
*
–
–
–
–
–
At constant entry, save old frame
pointer to stack, set new frame
pointer, and allocate local pointer
area
At constant entry, retrieve old frame
pointer from stack.
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Return from subroutine
Return from subroutine
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Operation
Branch when byte (ear) =
(ear) – 1, and (ear) ≠ 0
2× (b) Branch when byte (eam) =
(eam) – 1, and (eam) ≠ 0
DBNZ
eam, rel
3+
*6
2
DWBNZ
ear, rel
3
*5
2
DWBNZ
eam, rel
3+
*6
2
Branch when word (ear) =
(ear) – 1, and (ear) ≠ 0
2× (c) Branch when word (eam) =
(eam) – 1, and (eam) ≠ 0
INT
INT
INTP
INT9
RETI
#vct8
addr16
addr24
2
3
4
1
1
20
16
17
20
15
0
0
0
0
0
8× (c)
6× (c)
6× (c)
8× (c)
6× (c)
LINK
#local8
2
6
0
(c)
UNLINK
1
5
0
(c)
RET *7
RETP *8
1
1
4
6
0
0
(c)
(d)
*1:
*2:
*3:
*4:
*5:
*6:
*7:
*8:
*9:
0
5 when branching, 4 when not branching
13 when branching, 12 when not branching
7 + (a) when branching, 6 + (a) when not branching
8 when branching, 7 when not branching
7 when branching, 6 when not branching
8 + (a) when branching, 7 + (a) when not branching
Retrieve (word) from stack
Retrieve (long word) from stack
In the CBNE/CWBNE instruction, do not use the RWj+ addressing mode.
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
74
MB90620A Series
Table 20
Mnemonic
Other Control Instructions (Byte/Word/Long Word) [28 Instructions]
#
~
RG
B
Operation
L A
H H
I
S T N Z V C RM
W
PUSHW
PUSHW
PUSHW
PUSHW
A
AH
PS
rlst
1
1
1
2
4
4
4
*3
0
0
0
*5
(c)
(c)
(c)
*4
word (SP) ← (SP) –2, ((SP)) ← (A)
word (SP) ← (SP) –2, ((SP)) ← (AH)
word (SP) ← (SP) –2, ((SP)) ← (PS)
(SP) ← (SP) –2n, ((SP)) ← (rlst)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
POPW
POPW
POPW
POPW
A
AH
PS
rlst
1
1
1
2
3
3
4
*2
0
0
0
*5
(c)
(c)
(c)
*4
word (A) ← ((SP)), (SP) ← (SP) +2
word (AH) ← ((SP)), (SP) ← (SP) +2
word (PS) ← ((SP)), (SP) ← (SP) +2
(rlst) ← ((SP)), (SP) ← (SP) +2n
–
–
–
–
*
–
–
–
–
–
*
–
–
–
*
–
–
–
*
–
–
–
*
–
–
–
*
–
–
–
*
–
–
–
*
–
–
–
–
–
JCTX
@A
1
14
0
–
–
*
*
*
*
*
*
*
–
AND
OR
CCR, #imm8
CCR, #imm8
2
2
3
3
0
0
0
0
byte (CCR) ← (CCR) and imm8
byte (CCR) ← (CCR) or imm8
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
MOV RP, #imm8
MOV ILM, #imm8
2
2
2
2
0
0
0
0
byte (RP) ←imm8
byte (ILM) ←imm8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOVEA RWi, ear
MOVEA RWi, eam
MOVEA A, ear
MOVEA A, eam
2
2+
2
2+
3
2+ (a)
1
1+ (a)
1
1
0
0
0
0
0
0
word (RWi) ←ear
word (RWi) ←eam
word(A) ←ear
word (A) ←eam
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ADDSP #imm8
ADDSP #imm16
2
3
3
3
0
0
0
0
word (SP) ← (SP) +ext (imm8)
word (SP) ← (SP) +imm16
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOV
MOV
2
2
*1
1
0
0
0
0
byte (A) ← (brgl)
byte (brg2) ← (A)
Z
–
*
–
–
–
–
–
–
–
*
*
*
*
–
–
–
–
–
–
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
No operation
Prefix code for accessing AD space
Prefix code for accessing DT space
Prefix code for accessing PC space
Prefix code for accessing SP space
Prefix code for no flag change
Prefix code for common register bank
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
NOP
ADB
DTB
PCB
SPB
NCC
CMR
A, brgl
brg2, A
6× (c) Context switch instruction
*1: PCB, ADB, SSB, USB, and SPB : 1 state
DTB, DPR
: 2 states
*2: 7 + 3 × (pop count) + 2 × (last register number to be popped), 7 when rlst = 0 (no transfer register)
*3: 29 + (push count) – 3 × (last register number to be pushed), 8 when rlst = 0 (no transfer register)
*4: Pop count × (c), or push count × (c)
*5: Pop count or push count.
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
75
MB90620A Series
Table 21
Mnemonic
Bit Manipulation Instructions [21 Instructions]
#
~
RG
B
Operation
(b)
(b)
(b)
byte (A) ← (dir:bp) b
byte (A) ← (addr16:bp) b
byte (A) ← (io:bp) b
L A
H H
I
S T N Z V C RM
W
Z
Z
Z
*
*
*
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
MOVB
MOVB
MOVB
A, dir:bp
A, addr16:bp
A, io:bp
3
4
3
5
5
4
0
0
0
MOVB
MOVB
MOVB
dir:bp, A
addr16:bp, A
io:bp, A
3
4
3
7
7
6
0
0
0
2× (b) bit (dir:bp) b ← (A)
2× (b) bit (addr16:bp) b ← (A)
2× (b) bit (io:bp) b ← (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
–
*
*
*
SETB
SETB
SETB
dir:bp
addr16:bp
io:bp
3
4
3
7
7
7
0
0
0
2× (b) bit (dir:bp) b ← 1
2× (b) bit (addr16:bp) b ← 1
2× (b) bit (io:bp) b ← 1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
CLRB
CLRB
CLRB
dir:bp
addr16:bp
io:bp
3
4
3
7
7
7
0
0
0
2× (b) bit (dir:bp) b ← 0
2× (b) bit (addr16:bp) b ← 0
2× (b) bit (io:bp) b ← 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
BBC
BBC
BBC
dir:bp, rel
addr16:bp, rel
io:bp, rel
4
5
4
*1
*1
*2
0
0
0
(b)
(b)
(b)
Branch when (dir:bp) b = 0
Branch when (addr16:bp) b = 0
Branch when (io:bp) b = 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
–
–
BBS
BBS
BBS
dir:bp, rel
addr16:bp, rel
io:bp, rel
4
5
4
*1
*1
*2
0
0
0
(b)
(b)
(b)
Branch when (dir:bp) b = 1
Branch when (addr16:bp) b = 1
Branch when (io:bp) b = 1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
–
–
SBBS
addr16:bp, rel
5
*3
0
–
–
–
–
–
–
*
–
–
*
WBTS
io:bp
3
*4
0
WBTC
io:bp
3
*4
0
*1:
*2:
*3:
*4:
*5:
2× (b) Branch when (addr16:bp) b = 1, bit = 1
*
5
Wait until (io:bp) b = 1
–
–
–
–
–
–
–
–
–
–
*
5
Wait until (io:bp) b = 0
–
–
–
–
–
–
–
–
–
–
8 when branching, 7 when not branching
7 when branching, 6 when not branching
10 when condition is satisfied, 9 when not satisfied
Undefined count
Until condition is satisfied
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
76
MB90620A Series
Table 22
Accumulator Manipulation Instructions (Byte/Word) [6 Instructions]
Mnemonic
#
~
R
G
B
Operation
SWAP
SWAPW/XCHW AL, AH
EXT
EXTW
ZEXT
ZEXTW
1
1
1
1
1
1
3
2
1
2
1
1
0
0
0
0
0
0
0
0
0
0
0
0
byte (A) 0 to 7 ↔ (A) 8 to 15
word (AH) ↔ (AL)
byte sign extension
word sign extension
byte zero extension
word zero extension
Table 23
L A
H H
I
S
T
N
Z
V
C RM
W
–
–
X
–
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
R
R
–
–
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
L A
H H
I
S
T
N
Z
V
C RM
W
–
*
–
X
–
Z
–
–
–
–
–
–
String Instructions [10 Instructions]
#
~
R
G B
MOVS/MOVSI
MOVSD
2
2
*2
*2
*5
*5
*3 Byte transfer @AH+ ← @AL+, counter = RW0
*3 Byte transfer @AH– ← @AL–, counter = RW0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
SCEQ/SCEQI
SCEQD
2
2
*1
*1
*5
*5
*4 Byte retrieval (@AH+) – AL, counter = RW0
*4 Byte retrieval (@AH–) – AL, counter = RW0
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
FISL/FILSI
2
6m +6
*5
*3 Byte filling @AH+ ← AL, counter = RW0
–
–
–
–
–
*
*
–
–
–
MOVSW/MOVSWI
MOVSWD
2
2
*2
*2
*8
*8
*6 Word transfer @AH+ ← @AL+, counter = RW0
*6 Word transfer @AH– ← @AL–, counter = RW0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
SCWEQ/SCWEQI
SCWEQD
2
2
*1
*1
*8
*8
*7 Word retrieval (@AH+) – AL, counter = RW0
*7 Word retrieval (@AH–) – AL, counter = RW0
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
FILSW/FILSWI
2
6m +6
*8
*6 Word filling @AH+ ← AL, counter = RW0
–
–
–
–
–
*
*
–
–
–
Mnemonic
Operation
m: RW0 value (counter value)
n: Loop count
*1: 5 when RW0 is 0, 4 + 7 × (RW0) for count out, and 7 × n + 5 when match occurs
*2: 5 when RW0 is 0, 4 + 8 × (RW0) in any other case
*3: (b) × (RW0) + (b) × (RW0) when accessing different areas for the source and destination, calculate (b) separately
for each.
*4: (b) × n
*5: 2 × (RW0)
*6: (c) × (RW0) + (c) × (RW0) when accessing different areas for the source and destination, calculate (c) separately
for each.
*7: (c) × n
*8: 2 × (RW0)
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
77
MB90620A Series
■ ORDERING INFORMATION
Model
MB90622PFV
MB90623PFV
MB90P623PFV
78
Package
100-pin Plastic LQFP
(FPT-100P-M05)
Remarks
MB90620A Series
■ PACKAGE DIMENSIONS
100-pin Plastic LQFP
(FPT-100P-M05)
+0.20
16.00±0.20(.630±.008)SQ
75
1.50 −0.10
+.008
.059 −.004
51
14.00±0.10(.551±.004)SQ
76
(Mounting height)
50
12.00
(.472)
REF
15.00
(.591)
NOM
Details of "A" part
0.15(.006)
INDEX
100
0.15(.006)
26
0.15(.006)MAX
LEAD No.
"B"
25
1
0.40(.016)MAX
"A"
0.50(.0197)TYP
+0.08
0.18 −0.03
+.003
.007 −.001
+0.05
0.08(.003)
M
0.127 −0.02
+.002
.005 −.001
Details of "B" part
0.10±0.10
(STAND OFF)
(.004±.004)
0.10(.004)
C
1995 FUJITSU LIMITED F100007S-2C-3
0.50±0.20(.020±.008)
0~10˚
Dimension in mm (inches)
79
MB90620A Series
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-88, Japan
Tel: (044) 754-3763
Fax: (044) 754-3329
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, U.S.A.
Tel: (408) 922-9000
Fax: (408) 432-9044/9045
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LIMITED
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
Fax: (65) 281-0220
All Rights Reserved.
The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document presented
as examples of semiconductor device applications, and are not
intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the
use of this information or circuit diagrams.
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement
equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded (such
as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
Any semiconductor devices have inherently a certain rate of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required
for export of those products from Japan.
F9704
 FUJITSU LIMITED Printed in Japan
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