FUJITSU SEMICONDUCTOR DATA SHEET DS07-16506-1E 32-bit Microcontroller CMOS FR60Lite MB91230 Series MB91233L/MB91F233/MB91F233L/MB91V230 ■ DESCRIPTION The MB91230 series is a line of standard microcontrollers, based on a 32-bit high-performance RISC CPU and containing variety of I/O resources, for embedded control applications which require high CPU performance at high speed processing. Audio motor control storage : Designed to specifications for embedded control applications which high CPU performance power processing. The MB91230 series belongs to the FR60Lite family. ■ FEATURES • 32-bit RISC, load/store architecture with a 5 stage pipeline • Maximum operating frequency: 33.6 MHz (oscillation frequency = 4.2 MHz, oscillation frequency 8-multiplier (PLL clock multiplication method) ) • 16-bit fixed length instructions (basic instructions) • Execution speed of instructions : 1 instruction per cycle (Continued) ■ PACKAGES 401-pin Ceramic PGA 120-pin Plastic LQFP 128-pin plastic FLGA (PGA-401C-A02) (FPT-120P-M05) (LGA-128P-M01) MB91230 Series (Continued) • Memory-to-memory transfer, bit handling, and barrel shift instructions, etc. : Instructions suitable for embedded applications • Function entry/exit instructions, multiple-register load/store instructions : Instructions adapted for C-language • Register interlock function : Facilitates coding in assembler • Built-in multiplier with instruction-level support - 32-bit multiplication with sign : 5 cycles - 16-bit multiplication with sign : 3 cycles • Interrupt (PC and PS save) : 6 cycles (16 priority levels) • Harvard architecture allowing program access and data access to be executed simultaneously • Instruction compatible with FR family • Capacity of built-in ROM and ROM type - MASK ROM : 256 KB - FLASH ROM : 256 KB • Capacity of built-in RAM : 16 KB • General-purpose ports : Maximum 98 ports (including N-ch open-drain port : 4 ports) • A/D converter (series-parallel type) - Resolution : 10-bit : 8 ch (4 ch × 2 unit) - Conversion time : 1.69 µs (Minimum conversion time) • D/A converter (R-2R type) - Resolution : 8-bit : 2 ch (independence) - Conversion speed : 0.6 µs (when load capacitance 20 pF) • External interrupt input : 16 ch • Bit search module (for REALOS) - Function for searching the MSB (Upper bit) in each word for the first “0” or “1” inverted point • UART (full-duplex double buffer) : 4 ch - Selectable parity On/Off - Asynchronous (start-stop synchronized) or clock-synchronous communications selectable - Internal timer for dedicated baud rate (U-timer) on each channel - External clock can be used as transfer clock - Error detection function for parity, frame and overrun • PPG : 16-bit × 6 ch • Up/down counter : 2 ch (8-bit × 2 ch or 16-bit × 1 ch) • Reload timer : 16-bit × 4 ch • Free-run timer : 16-bit × 2 ch • Watch timer : 15-bit × 1 ch • PWC : 8-bit × 2 ch • Input capture : 2 ch (interface with free-run timer 0) • Output compare : 4 ch (free-run timer 0 and output compare unit 0/1 cooperate, free-run timer 1 and output compare units 2/3) • LCD controller : SEG00 to SEG31/COM0 to COM3 (also serving as a port) • Clock monitor (peripheral clock output function) : 1 ch • Timebase/watchdog timer (26-bit) • Real-time clock (counting even with the real-time clock stopped) • Low Power Consumption Mode • Sleep/stop function • Package : LQFP-120, FLGA-128 • Technology : CMOS 0.35 µm • Power supply • Dual power supply configuration [internal logic 3.3 V, I/O 5.5 V(3.3 V for ADC and DAC input/output)] Note : Do not set the external bus mode in which the MB91230 series cannot operate. 2 MB91230 Series ■ PIN ASSIGNMENT • MB91233L, MB91F233, MB91F233L 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 P25/SOT2 P24/SIN2 P23/PWI1/OP3 P22/PWI0/OP2 P21/CKI1/OP1 P20/CKI0/OP0 P17/INT7 P16/INT6 P15/INT5 P14/INT4 P13/INT3 P12/INT2 X0 X1 VSS VCC P11/INT1 P10/INT0 P07/IC1 P06/IC0 P05/SCK1 P04/SOT1 P03/SIN1 P02/SCK0 P01/SOT0 P00/SIN0 V3 V2 V1 V0 (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 INIT MD0 MD1 MD2 P73/COM3 P72/COM2 P71/COM1 P70/COM0 P67/SEG31∗ P66/SEG30∗ P65/SEG29∗ P64/SEG28∗ PB3/SEG27 PB2/SEG26 VSS VCC PB1/SEG25 PB0/SEG24 PA7/SEG23 PA6/SEG22 PA5/SEG21 PA4/SEG20 PA3/SEG19 PA2/SEG18 PA1/SEG17 PA0/SEG16 P97/SEG15 P96/SEG14 P95/SEG13 P94/SEG12 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 P57/INT15/TIN0/ADTG0 PF3/TOT3 PF4/TIN3/ADTG1 PD0/DA0 PD1/DA1 AVCC AVRH AVSS PC0/AN0 PC1/AN1 PC2/AN2 PC3/AN3 PC4/AN4 PC5/AN5 PC6/AN6 PC7/AN7 VSS VCC3IO P80/SEG0 P81/SEG1 P82/SEG2 P83/SEG3 P84/SEG4 P85/SEG5 P86/SEG6 P87/SEG7 P90/SEG8 P91/SEG9 P92/SEG10 P93/SEG11 P26/SCK2 P27/SIN3 P30/SOT3 P31/SCK3 P32/AIN0 P33/BIN0 P34/ZIN0 P35/AIN1 P36/BIN1 P37/ZIN1 P40/PPG0 P41/PPG1 X0A X1A VCC3B VSS VCC3 P42/PPG2 P43/PPG3 P44/TOT0 P45/TOT1 P46/TOT2 P47/CKOT P50/INT8 P51/INT9 P52/INT10 P53/INT11/PPG4 P54/INT12/PPG5 P55/INT13/TIN2 P56/INT14/TIN1 * : Open-drain (FPT-120P-M05) (Continued) 3 MB91230 Series (Continued) • MB91F233L M M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 L L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 K K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 J J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 H H1 H2 H3 H4 H9 H10 H11 H12 G G1 G2 G3 G4 G9 G10 G11 G12 TOP VIEW F F1 F2 F3 F4 F9 F10 F11 F12 E E1 E2 E3 E4 E9 E10 E11 E12 D D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 C C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 B B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 A A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 1 2 3 4 5 6 7 8 9 10 11 12 INDEX (LGA-128P-M01) 4 MB91230 Series Pin correspondence table of LQFP-120 and FLGA-128 in MB91230 series (LGA-128P-M01) FLGA-128 FLGA-128 FLGA-128 LQFP-120 No. Signal LQFP-120 No. Signal LQFP-120 No. No. (JEDEC name No. (JEDEC name No. (JEDEC No.) No.) No.) Signal name 1 A1 P26/SCK2 98 C9 P03/SIN1 18 G1 P42/PPG2 120 A2 P25/SOT2 93 C10 V2 15 G2 VCC3B 117 A3 P22/PWI0/ OP2 85 C11 P72/COM2 *2 G3*4 VCC3*4 114 A4 P17/INT7 87 C12 MD2 17 G4 VCC3 A5 *5 10 D1 P37/ZIN1 71 G9 PA6/ SEG22 109 A6 P12/INT2 6 D2 P33/BIN0 75 G10 VCC 107 A7 X1 8 D3 P35/AIN1 74 G11 PB1/ SEG25 103 A8 P10/INT0 119 D4 P24/SIN2 77 G12 PB2/ SEG26 100 A9 P05/SCK1 111 D5 P14/INT4 21 H1 P45/TOT1 97 A10 P02/SCK0 D6 *5 19 H2 P43/PPG3 94 A11 V3 101 D7 P06/IC0 23 H3 P47/CKOT 91 A12 V0 95 D8 P00/SIN0 20 H4 P44/TOT0 4 B1 P31/SCK3 89 D9 MD0 65 H9 PA0/ SEG16 118 B2 P23/PWI1/ OP3 86 D10 P73/COM3 72 H10 PA7/ SEG23 115 B3 P20/CKI0/ OP0 82 D11 P67/ SEG31*1 69 H11 PA4/ SEG20 112 B4 P15/INT5 84 D12 P71/COM1 73 H12 PB0/ SEG24 110 B5 P13/INT3 13 E1 X0A 24 J1 P50/INT8 106 B6 VSS 9 E2 P36/BIN1 22 J2 P46/TOT2 104 B7 P11/INT1 12 E3 P41/PPG1 26 J3 P52/INT10 99 B8 P04/SOT1 5 E4 P32/AIN0 29 J4 P55/INT13/ TIN2 96 B9 P01/SOT0 81 E9 P66/ SEG30*1 35 J5 PD1/DA1 92 B10 V1 83 E10 P70/COM0 40 J6 PC1/AN1 88 B11 MD1 80 E11 P65/ SEG29*1 47 J7 VSS 90 B12 INIT E12 *5 50 J8 P81/SEG1 (Continued) 5 MB91230 Series (Continued) LQFP-120 No. FLGA-128 No. (JEDEC No.) Signal name LQFP-120 No. FLGA-128 No. (JEDEC No.) Signal name LQFP-120 No. FLGA-128 No. (JEDEC No.) Signal name 7 C1 P34/ZIN0 16 F1 VSS 59 J9 P92/ SEG10 2 C2 P27/SIN3 F2 *5 68 J10 PA3/ SEG19 3 C3 P30/SOT3 14 F3 X1A 66 J11 PA1/ SEG17 116 C4 P21/CKI1/ OP1 11 F4 P40/PPG0 70 J12 PA5/ SEG21 113 C5 P16/INT6 78 F9 PB3/ SEG27 27 K1 P53/ INT11/ PPG4 108 C6 X0 79 F10 P64/ SEG28*1 25 K2 P51/INT9 105 C7 VCC 76 F11 VSS 33 K3 PF4/TIN3/ ADTG1 102 C8 P07/IC1 F12 *5 38 K4 AVSS 41 K5 PC2/AN2 36 L4 AVCC 37 M3 AVRH 44 K6 PC5/AN5 *3 L5*4 AVRL*4 39 M4 PC0/AN0 48 K7 VCC3IO 43 L6 PC4/AN4 42 M5 PC3/AN3 53 K8 P84/SEG4 45 L7 PC6/AN6 46 M6 PC7/AN7 56 K9 P87/SEG7 49 L8 P80/SEG0 M7 *5 63 K10 P96/ SEG14 52 L9 P83/SEG3 51 M8 P82/SEG2 62 K11 P95/ SEG13 55 L10 P86/SEG6 54 M9 P85/SEG5 67 K12 PA2/ SEG18 58 L11 P91/SEG9 57 M10 P90/SEG8 30 L1 P56/ INT14/ TIN1 64 L12 P97/ SEG15 60 M11 P93/ SEG11 28 L2 P54/ INT12/ PPG5 31 M1 P57/ INT15/ TIN0/ ADTG0 61 M12 P94/ SEG12 32 L3 PF3/TOT3 34 M2 PD0/DA0 *1 : Open-drain *2 : Connected to pin 17(VCC3) on the LQFP120 version *3 : Connected to pin 38(AVSS) on the LQFP120 version *4 : Signals added to the FLGA version *5 : NC pin on the FLGA version 6 MB91230 Series ■ PIN DESCRIPTION Pin no. LQFP FLGA Pin name Circuit type SCK2 1 2 A1 D General purpose input/output port. This function is valid when corresponding bit of PFR2 register is set to port function. SIN3 UART3 data input. When using this function, corresponding bit of DDR2 register is set to input. C2 D General purpose input/output port. This function is always valid. SOT3 4 5 6 7 8 UART2 clock input/output. This function is valid when corresponding bit of PFR2 register is set to peripheral function. P26 P27 3 Description C3 B UART3 data output. This function is valid when corresponding bit of PFR3 register is set to peripheral function. P30 General purpose input/output port. This function is valid when corresponding bit of PFR3 register is set to port function. SCK3 UART3 clock input/output. This function is valid when corresponding bit of PFR3 register is set to peripheral function. B1 B P31 General purpose input/output port. This function is valid when corresponding bit of PFR3 register is set to port function. AIN0 Up/down counter 0 AIN input. When using this function, corresponding bit of DDR3 register is set to input. E4 B P32 General purpose input/output port. This function is alwais valid. BIN0 Up/down counter 0 BIN input. When using this function, corresponding bit of DDR3 register is set to input. D2 B P33 General purpose input/output port. This function is always valid. ZIN0 Up/down counter 0 ZIN input. When using this function, corresponding bit of DDR3 register is set to input. C1 B P34 General purpose input/output port. This function is always valid. AIN1 Up/down counter 1 AIN input. When using this function, corresponding bit of DDR3 register is set to input. D3 B P35 General purpose input/output port. This function is always valid. (Continued) 7 MB91230 Series Pin no. LQFP FLGA Pin name Circuit type Description B Up/down counter 1 BIN input. When using this function, corresponding bit of DDR3 register is set to input. BIN1 9 10 E2 P36 General purpose input/output port. This function is always valid. ZIN1 Up/down counter 1 ZIN input. When using this function, corresponding bit of DDR3 register is set to input. D1 B General purpose input/output port. This function is always valid. P37 PPG0 11 12 F4 D P40 General purpose input/output port. This function is valid when corresponding bit of PFR4 register is set to port function. PPG1 PPG1 output. This function is valid when corresponding bit of PFR4 register is set to peripheral function. E3 D P41 13 E1 X0A 14 F3 X1A 15 G2 16 17 19 General purpose input/output port. This function is valid when corresponding bit of PFR4 register is set to port function. Sub-clock oscillation pin (32 kHz) VCC3B Power supply pin for backup (RTC) F1 VSS Power supply pin (GND) G4 VCC3 Power supply pin (3.3 V internal logic) PPG2 18 PPG0 output. This function is valid when corresponding bit of PFR4 register is set to peripheral function. G1 D PPG2 output. This function is valid when corresponding bit of PFR4 register is set to peripheral function. P42 General purpose input/output port. This function is valid when corresponding bit of PFR4 register is set to port function. PPG3 PPG3 output. This function is valid when corresponding bit of PFR4 register is set to peripheral function. H2 D P43 General purpose input/output port. This function is valid when corresponding bit of PFR4 register is set to port function. (Continued) 8 MB91230 Series Pin no. LQFP FLGA Pin name Circuit type TOT0 20 21 22 23 24 25 H4 D Reload timer 0 output port. This function is valid when corresponding bit of PFR4 register is set to peripheral function. P44 General purpose input/output port. This function is valid when corresponding bit of PFR4 register is set to port function. TOT1 Reload timer 1 output port. This function is valid when corresponding bit of PFR4 register is set to peripheral function. H1 D P45 General purpose input/output port. This function is valid when corresponding bit of PFR4 register is set to port function. TOT2 Reload timer 2 output port. This function is valid when corresponding bit of PFR4 register is set to peripheral function. J2 D P46 General purpose input/output port. This function is valid when corresponding bit of PFR4 register is set to port function. CKOT Clock monitor function output pin. This function is valid when corresponding bit of PFR4 register is set to peripheral function. H3 D P47 General purpose input/output port. This function is valid when corresponding bit of PFR4 register is set to port function. INT8 External interrupt input. When using this function, corresponding bit of DDR5 register is set to input. J1 C P50 General purpose input/output port. This function is always valid. INT9 External interrupt input. When using this function, corresponding bit of DDR5 register is set to input. K2 C General purpose input/output port. This function is always valid. P51 INT10 26 Description J3 C P52 External interrupt input. When using this function, corresponding bit of DDR5 register is set to input. General purpose input/output port. This function is always valid. (Continued) 9 MB91230 Series Pin no. LQFP 27 28 29 30 FLGA K1 L2 J4 L1 Pin name Circuit type Description PPG4 PPG4 output. This function is valid when corresponding bit of PFR5 register is set to peripheral function. INT11 External interrupt input. This function is enabled when corresponding bit of PFR5 register is set to port function and corresponding bit of DDR5 resister is set to input. C P53 General purpose input/output port. This function is valid when corresponding bit of PFR5 register is set to port function. PPG5 PPG5 output. This function is valid when corresponding bit of PFR5 register is set to peripheral function. INT12 External interrupt input. This function is enabled when corresponding bit of PFR5 register is set to port function and corresponding bit of DDR5 resister is set to input. C P54 General purpose input/output port. This function is valid when corresponding bit of PFR5 register is set to port function. TIN2 Reload timer 2 event input pin. This function is valid when corresponding bit of DDR5 register is set to input. INT13 C External interrupt input. This function is valid when corresponding bit of DDR5 register is set to input. P55 General purpose input/output port. This function is always valid. TIN1 Reload timer 1 event input pin. This function is valid when corresponding bit of DDR5 register is set to input. INT14 P56 C External interrupt input. This function is valid when corresponding bit of DDR5 register is set to input. General purpose input/output port. This function is always valid. (Continued) 10 MB91230 Series Pin no. LQFP 31 FLGA Pin name Circuit type ADTG0 External trigger input pin of A/D converter 0. This function is valid when corresponding bit of DDR5 register is set to input. TIN0 Reload timer 0 event input pin. This function is valid when corresponding bit of DDR5 register is set to input. M1 C External interrupt input. This function is valid when corresponding bit of DDR5 register is set to input. INT15 General purpose input/output port. This function is always valid. P57 TOT3 32 33 34 35 L3 K3 Description D Reload timer 3 output port. This function is valid when corresponding bit of PFRF register is set to peripheral function. PF3 General purpose input/output port. This function is valid when corresponding bit of PFRF register is set to port function. ADTG1 External trigger input pin of A/D converter 1. This function is valid when corresponding bit of DDRF register is set to input. TIN3 D Reload timer 3 event input pin. This function is valid when corresponding bit of DDRF register is set to input. PF4 General purpose input/output port. This function is always valid. DA0 D/A converter 0 output pin. This function is valid when corresponding bit of PFRD register is set to peripheral function. M2 F PD0 General purpose input/output port. This function is valid when corresponding bit of PFRD register is set to port function. DA1 D/A converter 1 output pin. This function is valid when corresponding bit of PFRD register is set to peripheral function. J5 F PD1 General purpose input/output port. This function is valid when corresponding bit of PFRD register is set to port function. 36 L4 AVCC Analog power supply (for A/D, D/A converter) . 37 M3 AVRH Analog reference power supply (for A/D, D/A converter) . 38 K4 AVSS GND level input for analog circuit (for A/D, D/A converter) . (Continued) 11 MB91230 Series Pin no. LQFP 39 to 46 FLGA M4, J6, K5, M5, L6, K6, L7, M6 Pin name Circuit type AN0 to AN7 E PC0 to PC7 Description Analog input pin for A/D converter. This function is valid when corresponding bit of PFRC register is set to peripheral function. General purpose input/output port. This function is valid when corresponding bit of PFRC register is set to port function. 47 J7 VSS Power supply pin (GND) 48 K7 VCC3IO Power supply pin (analog-shared pin I/O) 49 to 56 57 to 64 65 to 72 73, 74 L8, J8, M8, L9, K8, M9, L10, K9 M10, L11, J9, M11, M12, K11, K10, L12 H9, J11, K12, J10, H11, J12, G9, H10 SEG0 to SEG7 I LCD controller/driver LCD segment output pin. This function is valid when corresponding bit of PFR8 register is set to peripheral function. P80 to P87 General purpose input/output port. This function is valid when corresponding bit of PFR8 register is set to port function. SEG8 to SEG15 LCD controller/driver LCD segment output pin. This function is valid when corresponding bit of PFR9 register is set to peripheral function. I P90 to P97 General purpose input/output port. This function is valid when corresponding bit of PFR9 register is set to port function. SEG16 to SEG23 LCD controller/driver LCD segment output pin. This function is valid when corresponding bit of PFRA register is set to peripheral function. I PA0 to PA7 General purpose input/output port. This function is valid when corresponding bit of PFRA register is set to port function. SEG24, SEG25 LCD controller/driver LCD segment output pin. This function is valid when corresponding bit of PFRB register is set to peripheral function. H12, G11 I PB0, PB1 General purpose input/output port. This function is valid when corresponding bit of PFRB register is set to port function. Power supply pin (5 V I/O MB91V230/F233) 75 G10 VCC 76 F11 VSS SEG26, SEG27 77, 78 I G12, F9 PB2, PB3 Power supply pin (3.3 V internal logic, I/O MB91F233L/ MB91233L) Power supply pin (GND) LCD controller/driver LCD segment output pin. This function is valid when corresponding bit of PFRB register is set to peripheral function. General purpose input/output port. This function is valid when corresponding bit of PFRB register is set to port function. (Continued) 12 MB91230 Series Pin no. LQFP 79 to 82 83 to 86 FLGA F10, E11, E9, D11 E10, D12, C11, D10 Pin name Circuit type SEG28 to SEG31 J Description LCD controller/driver LCD segment output pin. This function is valid when corresponding bit of PFR6 register is set to peripheral function. P64 to P67 General purpose input/output port. (open-drain) This function is valid when corresponding bit of PFR6 register is set to port function. COM0 to COM3 LCD controller/driver common pins. This function is valid when corresponding bit of PFR7 register is set to peripheral function. I P70 to P73 General purpose input/output port. This function is valid when corresponding bit of PFR7 register is set to port function. 87 to 89 C12, B11, D9 MOD2, MOD1, MOD0 H Mode input pin. 90 B12 INIT G External reset input. 91 to 94 A12, B10, C10, A11 V0 to V3 LCD controller/driver reference power supply input pins. SIN0 95 D8 D General purpose input/output port. This function is always valid. P00 SOT0 96 97 98 B9 UART0 data input. When using this function, corresponding bit of DDR0 register is set to input. D UART0 data output. This function is valid when corresponding bit of PFR0 register is set to peripheral function. P01 General purpose input/output port. This function is valid when corresponding bit of PFR0 register is set to port function. SCK0 UART0 clock input/output. This function is valid when corresponding bit of PFR0 register is set to peripheral function. A10 D P02 General purpose input/output port. This function is valid when corresponding bit of PFR0 register is set to port function. SIN1 UART1 data input. This function is valid when corresponding bit of DDR0 register is set to input. C9 D P03 General purpose input/output port. This function is always valid. (Continued) 13 MB91230 Series Pin no. LQFP FLGA Pin name Circuit type SOT1 99 100 101 102 103 104 B8 D Description UART1 data output. This function is valid when corresponding bit of PFR0 register is set to peripheral function. P04 General purpose input/output port. This function is valid when corresponding bit of PFR0 register is set to port function. SCK1 UART1 clock input/output. This function is valid when corresponding bit of PFR0 register is set to peripheral function. A9 D P05 General purpose input/output port. This function is valid when corresponding bit of PFR0 register is set to port function. IC0 Input capture input 0. This function is valid when corresponding bit of DDR0 register is set to input. D7 D P06 General purpose input/output port. This function is always valid. IC1 Input capture input 1. This function is valid when corresponding bit of DDR0 register is set to input. C8 D P07 General purpose input/output port. This function is always valid. INT0 External interrupt input. This function is valid when corresponding bit of DDR1 register is set to input. A8 A P10 General purpose input/output port. This function is always valid. INT1 External interrupt input. This function is valid when corresponding bit of DDR1 register is set to input. B7 A General purpose input/output port. This function is always valid. P11 Power supply pin (5 V I/O MB91V230/F233) 105 C7 VCC 106 B6 VSS 107 A7 X1 108 C6 X0 Power supply pin (3.3 V internal logic, I/O MB91F233L/ MB91233L) Power supply pin (GND) Main-clock oscillation pin (Continued) 14 MB91230 Series Pin no. LQFP FLGA Pin name Circuit type INT2 109 110 111 112 113 114 115 A6 A External interrupt input. This function is valid when corresponding bit of DDR1 register is set to input. P12 General purpose input/output port. This function is always valid. INT3 External interrupt input. This function is valid when corresponding bit of DDR1 register is set to input. B5 A P13 General purpose input/output port. This function is always valid. INT4 External interrupt input. This function is valid when corresponding bit of DDR1 register is set to input. D5 A P14 General purpose input/output port. This function is always valid. INT5 External interrupt input. This function is valid when corresponding bit of DDR1 register is set to input. B4 A P15 General purpose input/output port. This function is always valid. INT6 External interrupt input. This function is valid when corresponding bit of DDR1 register is set to input. C5 A P16 General purpose input/output port. This function is always valid. INT7 External interrupt input. This function is valid when corresponding bit of DDR1 register is set to input. A4 B3 Description A P17 General purpose input/output port. This function is always valid. CKI0 External clock input pin for free-run timer 0. This function is enabled when corresponding bit of PFR2 register is set to port function and corresponding bit of DDR2 register is set to input. OP0 P20 D Output compare 0 output pin. This function is valid when corresponding bit of PFR2 register is set to peripheral function. General purpose input/output port. This function is valid when corresponding bit of PFR2 register is set to port function. (Continued) 15 MB91230 Series (Continued) Pin no. LQFP FLGA Pin name Circuit type External clock input pin for free-run timer 1. This function is enabled when corresponding bit of PFR2 register is set to port function and corresponding bit of DDR2 register is set to input. CKI1 116 C4 OP1 D Pulse width counter 0 input. This function is enabled when corresponding bit of PFR2 register is set to port function and corresponding bit of DDR2 register is set to input. PWI0 A3 OP2 D Pulse width counter 1 input. This function is enabled when corresponding bit of PFR2 register is set to port function and corresponding bit of DDR2 register is set to input. PWI1 119 B2 OP3 D General purpose input/output port. This function is valid when corresponding bit of PFR2 register is set to port function. SIN2 UART2 data input. This function is valid when corresponding bit of DDR2 register is set to input. D4 D General purpose input/output port. This function is always valid. SOT2 A2 D P25 16 Output compare3 output pin. This function is valid when corresponding bit of PFR2 register is set to peripheral function. P23 P24 120 Output compare2 output pin. This function is valid when corresponding bit of PFR2 register is set to peripheral function. General purpose input/output port. This function is valid when corresponding bit of PFR2 register is set to port function. P22 118 Output compare1 output pin. This function is valid when corresponding bit of PFR2 register is set to peripheral function. General purpose input/output port. This function is valid when corresponding bit of PFR2 register is set to port function. P21 117 Description UART2 data output. This function is valid when corresponding bit of PFR2 register is set to peripheral function. General purpose input/output port. This function is valid when corresponding bit of PFR2 register is set to port function. (38) L5 AVRL Analog reference power supply (for A/D converter) A5, D6, E12, F2, F12, M7 NC Unconnected pin. MB91230 Series ■ I/O CIRCUIT TYPE Type Circuit type Remarks With Pull-up control (50 kΩ) P A P Pull-up control Output drive Pch N Output drive Nch CMOS level output IOH = 4 mA/IOL = 4 mA CMOS hysteresis input (with standby control) Hysteresis input Standby control With Pull-up control (50 kΩ) P P Pull-up control Output drive Pch N Output drive Nch B CMOS level output IOH = 4 mA/IOL = 4 mA CMOS hysteresis input (with standby control) Test pin for FLASH Hysteresis input Standby control Test pin for FLASH Analog SW control CMOS level output C P Output drive Pch N Output drive Nch CMOS hysteresis input (with standby control) Hysteresis input Standby control D P Output drive Pch N Output drive Nch CMOS level output IOH = 4 mA/IOL = 4 mA CMOS hysteresis input (with standby control) Test pin for FLASH Hysteresis input Standby control Test pin for FLASH Analog SW control (Continued) 17 MB91230 Series Type Circuit type P Output drive Pch N Output drive Nch E Remarks CMOS level output IOH = 4 mA/IOL = 4 mA CMOS hysteresis input (with standby control) Also serving as an analog input Hysteresis input Standby control Analog input Analog SW control P Output drive Pch N Output drive Nch F CMOS level output IOH = 4 mA/IOL = 4 mA CMOS hysteresis input (with standby control) Also serving as an analog input Hysteresis input Standby control Analog input Analog SW control With Pull-up control (50 kΩ) CMOS hysteresis input P G P N Hysteresis input High withstand-voltage input CMOS input (hysteresis level) N Low impedance input High impedance input N H N N High voltage detection output (Continued) 18 MB91230 Series (Continued) Type Circuit type Remarks P Output drive Pch N Output drive Nch CMOS level output IOH = 4 mA/IOL = 4 mA CMOS hysteresis input (with standby control) LCDC output I Hysteresis input Standby control LCDC output CMOS level output (open-drain) IOL = 20 mA CMOS hysteresis input (with standby control) LCDC output P N Output drive Nch J Hysteresis input Standby control LCDC output Oscillation circuit X1 Oscillation output K X0 Standby control 19 MB91230 Series ■ HANDLING DEVICES Preventing Latchup Latch-up may occur in a CMOS IC if a voltage greater than VCC or less than VSS is applied to an input or output pin or if an above-rating voltage is applied between VCC and VSS. A latchup, if it occurs, significantly increases the power supply current and may cause thermal destruction of an element. When you use a CMOS IC, be very careful not to exceed the absolute maximum rating. Treatment of Unused Pins Do not leave an unused input pin open, since it may cause a malfunction. Handle by, for example, using a pullup or pull-down resistor. About Power Supply Pins In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance. It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 µF between VCC and VSS near this device. About Crystal Oscillator Circuit Noise near the X0 and X1 pins may cause the device to malfunction. Design the printed circuit board so that X0, X1, the crystal oscillator (or ceramic oscillator) , and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended to design the PC board artwork with the X0 and X1 pins surrounded by ground plane because stable operation can be expected with such a layout. Treatment of NC and OPEN Pins Pins marked as NC and OPEN must be left open-circuit. About Mode Pins (MD0 to MD2) These pins should be connected directly to VCC or VSS. To prevent the device erroneously switching to test mode due to noise, design the printed circuit board such that the distance between the mode pins and VCC or VSS is as short as possible and the connection impedance is low. Operation at Start-up Be sure to execute setting initialized reset (INIT) with INIT pin immediately after start-up. Also, in order to provide the oscillation stabilization wait time for the oscillation circuit immediately after start-up, hold the “L” level input to the INIT pin for the required stabilization wait time. (For INIT via the INIT pin, the oscillation stabilization wait time setting is initialized to the minimum value) . About Oscillation Input at Power On When turning the power on, maintain clock input untill the device is released from the oscillation stabilization wait state. 20 MB91230 Series Clock Control Block Input the “L” signal to the INIT pin to assure the clock oscillation stabilization wait time. Switch Shared Port Function To switch between the use as a port and the use as a dedicated pin, use the port function register (PFR) . Low Power Consumption Mode To enter the standby mode, use the synchronous standby mode (set with the SYNCS bit as bit 8 in the TBCR : timebse counter control register) and be sure to use the following sequence (LDI #value_of_standby, R0) : value_of_standby is write data to STCR. (LDI #_STCR, R12) : _STCR is address (481H) of STCR. STB R0, @R12 : Writing to standby control register (STCR) LDUB @R12, R0 : STCR read for synchronous standby LDUB @R12, R0 : Dummy re-read of STCR NOP : NOP × 5 for arrangement of timing NOP NOP NOP NOP In addition, please set I flag, ILM, and ICR to diverge to the interruption handler that is the return factor after the standby returns. • Please do not do the following when the monitor debugger is used. • Break point setting for above instruction lines • Step execution for above instruction lines Power-on sequence for dual-power-supply model • Notes on the power-on and power-off sequences Power-on sequence : Vcc3B, Vcc3→Vcc→Vcc3IO, AVRH, V0-V3 Power-off sequence : Vcc3IO, AVRH, V0-V3 Vcc3→Vcc→Vcc3B, Vcc3 When VCC is turned on earlier, a potential difference between VCC and VCC3 must fall within 3.6 V. • The LCD power supply V3 must not exceed VCC in voltage. Apply V3 after turning on VCC3. • Turn on VCC3 before applying the analog power supply AVCC or an analog signal. 21 MB91230 Series Notes on the PS register As the PS register is processed by some instructions in advance, exception handling below may cause the interrupt handling routine to break when the debugger is used or the display contents of flags in the PS register to be updated. As the microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event, it performs operations before and after the EIT as specified in either case. • The following operations may be performed when the instruction immediately followed by a DIVOU/DIVOS instruction is (a) acceptance of a user interrupt, (b) single-stepped, or (c) breaks in response to a data event or emulator menu : 1) The D0 and D1 flags are updated in advance. 2) An EIT handling routine (user interrupt or emulator) is executed. 3) Upon returning from the EIT, the DIVOU/DIVOS instruction is executed, and the D0 and D1 flags are updated to the same values as in 1). • The following operations are performed when the ORCCR/STILM/MOVRi and PS instructions are executed to allow the interrupt. 1) The PS register is updated in advance. 2) An EIT handling routine (user interrupt) is executed. 3) Upon returning from the EIT, the above instructions are executed, and the PS register is updated to the same value as in 1). Watchdog Timer The watchdog timer built in this model monitors a program that it defers a reset within a certain period of time. The watchdog timer resets the CPU if the program runs out of controls, preventing the reset defer function from being executed. Once the function of the watchdog timer is enabled, therefore, the watchdog timer keeps on operating programs until it resets the CPU. As an exception, the watchdog timer defers a reset automatically under the condition in which the CPU stops program execution. For those conditions to which this exception applies, see the function description of watchdog timer. Step execution of RETI instruction If an interrupt occurs frequently during step execution, the corresponding interrupt handling routine is executed repeatedly after step execution. This will prevent the main routine and low-interrupt-level programs from being executed. Do not execute step of RETI instruction for escape. Disable the corresponding interrupt and execute debugger when the corresponding interrupt routine no longer needs debugging. Operand Break Do not apply a data event break to access to the area containing the address of a system stack pointer. 22 MB91230 Series ■ BLOCK DIAGRAM FR60Lite CPU Core 32 32 Bit Search Bus Converter ROM/FLASH RAM X0, X1 MD0 to MD2 INIT X0A, X1A Clock Control (Clock, Standby, Reset, Watchdog, TBT, Main-ClockStabilizationTimer) 32 16 32 Adapter 16 Watch Timer VCC3B Real Time Clock Interruption Controller INT0 to INT15 SIN0 to SIN3 SOT0 to SOT3 SCK0 to SCK3 External interrupt 0 to 15 UART 0 to 3 External Memory I/F (MB91230 is not supported) PORT I/F Clock Monitor LCDC, Driver, Internal Reference Voltage VCC PORTs CKOT COM0 to COM3 SEG0 to SEG31 V0 to V3 Up/Down Counter 0, 1 AIN0, AIN1 BIN0, BIN1 ZIN0, ZIN1 Reload Timer 0 to 3 TO0 to TO3 PPG 0 to 5 PPG0 to PPG5 U-TIMER 0 to 3 AN0 to AN3 ADTG AVRH AN4 to AN7 ADTG AVCC DA0, DA1 4 ch Input 10/8-bit A/D 0 4 ch Input 10/8-bit A/D 1 2 ch Output 8-bit D/A 0, 1 Input Capture 0, 1 Free Run Timer 0 Output Compare 0, 1 Free Run Timer 1 Output Compare 2, 3 8-bit PWC 0, 1 IC0, IC1 CKI0 OP0, OP1 CKI1 OP2, OP3 PWI0, PWI1 : Trriger signal 23 MB91230 Series ■ MEMORY SPACE 1. Memory space The FR60 Lite family has 4 gigabytes of logical address space (232 addresses) available to the CPU by linear access. • Direct Addressing Areas The following address space areas are used as I/O areas. These areas are called direct addressing areas, in which the address of an operand can be specified directly during an instruction. The size of directly addressable areas depends on the length of the data being accessed as shown below. • byte data access : 0 to 0FFH • half word data access : 0 to 1FFH • word data access : 0 to 3FFH 2. Memory Map MB91V230 0000 0000H 0000 0400H 0001 0000H 0003 A000H 0004 0000H 0008 0000H MB91F233/L, MB91233L I/O Direct Addressing Areas I/O I/O Refer to I/O Map I/O Access disallowed Built-in RAM 24 KB Access disallowed Emulation SRAM area 512 KB 0010 0000H 0001 0000H Access disallowed 0003 C000H Built-in RAM 16 KB 0004 0000H 000C 0000H Built-in FLASH ROM 256 KB 0010 0000H Access disallowed FFFF FFFFH Access disallowed Access disallowed FFFF FFFFH Note : Do not set the external bus mode in which the MB91230 series cannot operate. 24 MB91230 Series ■ MODE SETTINGS The FR family uses mode pins (MD2 to MD0) and a mode data to set the operation mode. • Mode Pins The MD2, MD1, and MD0 pins specify how the mode vector fetch and reset vector fetch is performed. Setting is prohibited other than that shown in the following table. Mode Pins Mode name Reset vector access area 0 Internal ROM mode vector Internal 1 External ROM mode vector External MD2 MD1 MD0 0 0 0 0 Remarks Not supported by this model. • Mode data Data written to the internal mode register (MODR) by a mode vector fetch is called mode data. After an operation mode has been set in the mode register, the device operates in the operation mode. The mode data is set by all reset source. User programs cannot set data to the mode register. Details of mode data description bit 31 30 29 28 27 26 25 24 0 0 0 0 0 1 1 1 Operation mode setting bits [bit31 to bit24] Reserved bit Be sure to set this bit to “00000111”. Operation is not guaranteed when any value other than “00000111” is set. Note : Mode data set in the mode vector must be placed as byte data at 0x000FFFF8H. Use the highest byte from bit31 to bit24 for placement as the FR family uses the big endian for byte endian. bit 31 Incorrect 24 23 16 15 87 0 0x000FFFF8H XXXXXXXX XXXXXXXX XXXXXXXX Mode Data 0x000FFFF8H Mode Data XXXXXXXX XXXXXXXX XXXXXXXX Correct 0x000FFFFCH Reset Vector 25 MB91230 Series ■ I/O Map [How to read the table] Address 000000H Register +0 +1 +2 +3 PDR0 [R/W] B PDR1 [R/W] B PDR2 [R/W] B PDR3 [R/W] B XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Block T-unit Port data register Read/write attribute Access unit (B : byte, H : half word, W : word) Initial value of register after reset Register name (column 1 of the register is at address 4n, column 2 is at address 4n + 1...) Leftmost register address (For word-length access, column 1 of the register becomes the MSB of the data.) Note : Initial values of register bits are represented as follows : “ 1 ” : Initial Value “ 1 ” “ 0 ” : Initial Value “ 0 ” “ X ” : Initial Value “ undefined” “ - ” : No physical register at this location Access is barred with an undefined data access attribute. 26 MB91230 Series Address Register +0 +1 +2 +3 000000H PDR0 [R/W] B XXXXXXXX PDR1 [R/W] B XXXXXXXX PDR2 [R/W] B XXXXXXXX PDR3 [R/W] B XXXXXXXX 000004H PDR4 [R/W] B XXXXXXXX PDR5 [R/W] B XXXXXXXX PDR6 [R/W] B XXXX---- PDR7 [R/W] B ----XXXX 000008H PDR8 [R/W] B XXXXXXXX PDR9 [R/W] B XXXXXXXX PDRA [R/W] B XXXXXXXX PDRB [R/W] B ----XXXX 00000CH PDRC [R/W] B XXXXXXXX PDRD [R/W] B ------XX PDRF [R/W] ---XX--- 000010H to 00003CH 000040H EIRR0 [R/W] B, H, W 00000000 ENIR0 [R/W] B, H, W 00000000 ELVR0 [R/W] B, H, W 00000000 00000000 000044H DICR [R/W] B, H, W -------0 TMRLR0 [W] H, W XXXXXXXX XXXXXXXX TMR0 [R] H, W XXXXXXXX XXXXXXXX 00004CH TMCSR0 [R/W] B, H, W ----0000 00000000 000050H TMRLR1 [W] H, W XXXXXXXX XXXXXXXX TMR1 [R] H, W XXXXXXXX XXXXXXXX 000054H TMCSR1 [R/W] B, H, W ----0000 00000000 000058H TMRLR2 [W] H, W XXXXXXXX XXXXXXXX TMR2 [R] H, W XXXXXXXX XXXXXXXX 00005CH TMCSR2 [R/W] B, H, W ----0000 00000000 000060H 000064H 000068H 00006CH SIDR0 [R] B, H, W SODR0 [W] B, H, W XXXXXXXX UTIM0 [R] H (UTIMR0 [W] H) 00000000 00000000 SSR1 [R/W] B, H, W 00001000 SIDR1 [R] B, H, W SODR1 [W] B, H, W XXXXXXXX UTIM1 [R] H (UTIMR1 [W] H) 00000000 00000000 SCR0 [R/W] B, H, W 00000100 SCR1 [R/W] B, H, W 00000100 Port data register Unused External interrupt (INT0 to 7) Delay interrupt 000048H SSR0 [R/W] B, H, W 00001000 Block SMR0 [R/W] B, H, W 00--0-0- Reload timer 0 Reload timer 1 Reload timer 2 UART0 UTIMC0 [R/W] B U-TIMER0 0--00001 SMR1 [R/W] B, H, W 00--0-0- UART1 UTIMC1 [R/W] B U-TIMER1 0--00001 (Continued) 27 MB91230 Series Address 000070H Register +0 +1 +2 +3 SSR2 [R/W] B, H, W 00001000 SIDR2 [R] B, H, W SODR2 [W] B, H, W XXXXXXXX SCR2 [R/W] B, H, W 00000100 SMR2 [R/W] B, H, W 00--0-0- 000074H UTIM2 [R] H (UTIMR1 [W] H) 00000000 00000000 000078H ADCS0 [R/W] H, W XXXXXXXX XXXXXXXX ADCT0 [R/W] H, W 000-0000 -000--00 00007CH ADT00 (ADTH0/ADTL0) [R] H, W 000000XX XXXXXXXX ADT01 (ADTH1/ADTL1) [R] H, W 000000XX XXXXXXXX 000080H ADT02 (ADTH2/ADTL2) [R] H, W 000000XX XXXXXXXX ADT03 (ADTH3/ADTL3) [R] H, W 000000XX XXXXXXXX 000084H ADCS1 [R/W] H, W XXXXXXXX XXXXXXXX ADCT1 [R/W] H, W 000-0000 --000--00 000088H ADT10 (ADTH0/ADTL0) [R] H, W 000000XX XXXXXXXX ADT11 (ADTH1/ADTL1) [R] H, W 000000XX XXXXXXXX 00008CH ADT12 (ADTH2/ADTL2) [R] H, W 000000XX XXXXXXXX ADT13 (ADTH3/ADTL3) [R] H, W 000000XX XXXXXXXX 000090H Block UART2 UTIMC2 [R/W] B U-TIMER2 0--00001 DACR1 [R/W] B, H, W -------0 DACR0 [R/W] B, H, W -------0 DADR0 [R/W] B, H, W XXXXXXXX 000094H DADR1 [R/W] B, H, W XXXXXXXX 000098H LCDCMR [R/W] B, H, W ----0000 LCR0 [R/W] B, H, W 00010000 LCR1 [R/W] B, H, W 00000000 00009CH VRAM0 [R/W] B, H, W XXXXXXXX VRAM1 [R/W] B, H, W XXXXXXXX VRAM2 [R/W] B, H, W XXXXXXXX VRAM3 [R/W] B, H, W XXXXXXXX 0000A0H VRAM4 [R/W] B, H, W XXXXXXXX VRAM5 [R/W] B, H, W XXXXXXXX VRAM6 [R/W] B, H, W XXXXXXXX VRAM7 [R/W] B, H, W XXXXXXXX 0000A4H VRAM8 [R/W] B, H, W XXXXXXXX VRAM9 [R/W] B, H, W XXXXXXXX VRAM10 [R/W] B, H, W XXXXXXXX VRAM11 [R/W] B, H, W XXXXXXXX 0000A8H VRAM12 [R/W] B, H, W XXXXXXXX VRAM13 [R/W] B, H, W XXXXXXXX VRAM14 [R/W] B, H, W XXXXXXXX VRAM15 [R/W] B, H, W XXXXXXXX 0000ACH CKR [R/W] B, H, W ----0000 A/D converter 0 (series-parallel type) A/D converter 1 (series-parallel type) D/A converter LCD controller/driver Clock monitor (Continued) 28 MB91230 Series Address Register Block +0 +1 +2 +3 0000B0H RCR1 [W] B, H, W 00000000 RCR0 [W] B, H, W 00000000 UDCR1 [R] B, H, W 00000000 UDCR0 [R] B, H, W 00000000 0000B4H CCRH0 [R/W] B, H, W 00000000 CCRL0 [R/W] B, H, W 00001000 CSR0 [R/W] B, H, W 00000000 0000B8H CCRH1 [R/W] B, H, W 00000000 CCRL1 [R/W] B, H, W 00001000 CSR1 [R/W] B, H, W 00000000 0000BCH unused 0000C0H SSR [R/W] B, H, W 00001000 SIDR 3 [R] B, H, W SODR 3 [W] B, H, W XXXXXXXX SCR [R/W] B, H, W 00000100 SMR [R/W] B, H, W 00--0-0- UART3 UTIMC [R/W] B 0--00001 0000C4H UTIM [R] H (UTIMR [W] H) 00000000 00000000 0000C8H TMRLR3 [W] H, W XXXXXXXX XXXXXXXX TMR3 [R] H, W XXXXXXXX XXXXXXXX TMCSR3 [R/W] B, H, W ---00000 00000000 0000CCH 0000D0H EIRR1 [R/W] B, H, W 00000000 ENIR1 [R/W] B, H, W 00000000 ELVR1 [R/W] B, H, W 00000000 00000000 Up/down counter0, 1 U-TIMER3 Reload timer 3 External interrupt (INT8 to 16) 0000D4H TCDT0 [R/W] H, W 00000000 00000000 TCCS0 [R/W] B, H, W 00000000 Free-run timer 0 0000D8H TCDT1 [R/W] H, W 00000000 00000000 TCCS1 [R/W] B, H, W 00000000 Free-run timer 1 0000DCH IPCP1 [R] H, W XXXXXXXX XXXXXXXX 0000E0H IPCP0 [R] H, W XXXXXXXX XXXXXXXX ICS01 [R/W] B, H, W 00000000 0000E4H OCCP1 [R/W] H, W XXXXXXXX XXXXXXXX OCCP0 [R/W] H, W XXXXXXXX XXXXXXXX 0000E8H OCCP3 [R/W] H, W XXXXXXXX XXXXXXXX OCCP2 [R/W] H, W XXXXXXXX XXXXXXXX 0000ECH OCS23 [R/W] B, H, W ---0--00 0000--00 OCS01 [R/W] B, H, W ---0-00 0000--00 Input capture Output compare (Continued) 29 MB91230 Series Address Register +0 +1 +2 +3 0000F0H PWCC0 [R/W] B, H, W 0---00-0 PWCD0 [R] B, H, W XXXXXXXX PWCC1 [R/W] B, H, W 0---00-0 PWCD1 [R] B, H, W XXXXXXXX 0000F4H WTDBL [R/W] B -------0 0000F8H WTBR0 [R/W] B ---XXXXX WTBR1 [R/W] B XXXXXXXX 0000FCH WTHR [R/W] B, H ---XXXXX WTMR [R/W] B, H --XXXXXX WTSR [R/W] B --XXXXXX 000100H to 000114H 000118H GCN10 [R/W] H 00110010 00010000 GCN20 [R/W] B 00000000 00011CH 000120H PTMR0 [R] H, W 11111111 11111111 PCSR0 [W] H, W XXXXXXXX XXXXXXXX 000124H PDUT0 [W] H, W XXXXXXXX XXXXXXXX 000128H PTMR1 [R] H, W 11111111 11111111 00012CH PDUT1 [W] H, W XXXXXXXX XXXXXXXX 000130H PTMR2 [R] H, W 11111111 11111111 000134H PDUT2 [W] H, W XXXXXXXX XXXXXXXX 000138H PTMR3 [R] H, W 11111111 11111111 00013CH PDUT3 [W] H, W XXXXXXXX XXXXXXXX 000140H PTMR4 [R] H, W 11111111 11111111 000144H PDUT4 [W] H, W XXXXXXXX XXXXXXXX Block PWC0, 1 WTCR [R/W] B, H 00000000 000-00-X PCNH0 [R/W] B, H, W 00000000 WTBR2 [R/W] B Real-time clock XXXXXXXX Unused PPG Unused PCNL0 [R/W] B, H, W 00000000 PPG0 PCSR1 [W] H, W XXXXXXXX XXXXXXXX PCNH1 [R/W] B, H, W 00000000 PCNL1 [R/W] B, H, W 00000000 PPG1 PCSR2 [W] H, W XXXXXXXX XXXXXXXX PCNH2 [R/W] B, H, W 00000000 PCNL2 [R/W] B, H, W 00000000 PPG2 PCSR3 [W] H, W XXXXXXXX XXXXXXXX PCNH3 [R/W] B, H, W 00000000 PCNL3 [R/W] B, H, W 00000000 PPG3 PCSR4 [W] H, W XXXXXXXX XXXXXXXX PCNH4 [R/W] B, H, W 00000000 PCNL4 [R/W] B, H, W 00000000 PPG4 (Continued) 30 MB91230 Series Address Register +0 +1 000148H PTMR5 [R] H, W 11111111 11111111 00014CH PDUT5 [W] H, W XXXXXXXX XXXXXXXX +2 Block +3 PCSR5 [W] H, W XXXXXXXX XXXXXXXX PCNH5 [R/W] B, H, W 00000000 PCNL5 [R/W] B, H, W 00000000 PPG5 000150H to 0001FCH Unused 000200H to 0003ECH Unused 0003F0H BSD0 [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003F4H BSD1 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003F8H BSDC [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003FCH BSRR [R] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Bit search 000400H DDR0 [R/W] B 00000000 DDR1 [R/W] B 00000000 DDR2 [R/W] B 00000000 DDR3 [R/W] B00000000 000404H DDR4 [R/W] B 00000000 DDR5 [R/W] B 00000000 DDR6 [R/W] B 0000---- DDR7 [R/W] B ----0000 000408H DDR8 [R/W] B 00000000 DDR9 [R/W] B 00000000 DDRA [R/W] B 00000000 DDRB [R/W] B ----0000 00040CH DDRC [R/W] B 00000000 DDRD [R/W] B ------00 DDRF [R/W] B ---00--- 000410H to 00041CH 000420H PFR0 [R/W] B --00-00- PFR1 [R/W] B -------- PFR2 [R/W] B -00-0000 PFR3 [R/W] B ------00 000424H PFR4 [R/W] B 00000000 PFR5 [R/W] B ---00--- PFR6 [R/W] B 0000---- PFR7 [R/W] B ----0000 000428H PFR8 [R/W] B 00000000 PFR9 [R/W] B 00000000 PFRA [R/W] B 00000000 PFRB [R/W] B ----0000 00042CH PFRC [R/W] B -------- PFRD [R/W] B ------00 PFRF [R/W] B ----0--- 000430H to 00043CH Data direction register Unused Port function register Unused (Continued) 31 MB91230 Series Address Register +0 +1 +2 +3 000440H ICR00 [R/W] B, H, W ---11111 ICR01 [R/W] B, H, W ---11111 ICR02 [R/W] B, H, W ---11111 ICR03 [R/W] B, H, W ---11111 000444H ICR04 [R/W] B, H, W ---11111 ICR05 [R/W] B, H, W ---11111 ICR06 [R/W] B, H, W ---11111 ICR07 [R/W] B, H, W ---11111 000448H ICR08 [R/W] B, H, W ---11111 ICR09 [R/W] B, H, W ---11111 ICR10 [R/W] B, H, W ---11111 ICR11 [R/W] B, H, W ---11111 00044CH ICR12 [R/W] B, H, W ---11111 ICR13 [R/W] B, H, W ---11111 ICR14 [R/W] B, H, W ---11111 ICR15 [R/W] B, H, W ---11111 000450H ICR16 [R/W] B, H, W ---11111 ICR17 [R/W] B, H, W ---11111 ICR18 [R/W] B, H, W ---11111 ICR19 [R/W] B, H, W ---11111 000454H ICR20 [R/W] B, H, W ---11111 ICR21 [R/W] B, H, W ---11111 ICR22 [R/W] B, H, W ---11111 ICR23 [R/W] B, H, W ---11111 000458H ICR24 [R/W] B, H, W ---11111 ICR25 [R/W] B, H, W ---11111 ICR26 [R/W] B, H, W ---11111 ICR27 [R/W] B, H, W ---11111 00045CH ICR28 [R/W] B, H, W ---11111 ICR29 [R/W] B, H, W ---11111 ICR30 [R/W] B, H, W ---11111 ICR31 [R/W] B, H, W ---11111 000460H ICR32 [R/W] B, H, W ---11111 ICR33 [R/W] B, H, W ---11111 ICR34 [R/W] B, H, W ---11111 ICR35 [R/W] B, H, W ---11111 000464H ICR36 [R/W] B, H, W ---11111 ICR37 [R/W] B, H, W ---11111 ICR38 [R/W] B, H, W ---11111 ICR39 [R/W] B, H, W ---11111 000468H ICR40 [R/W] B, H, W ---11111 ICR41 [R/W] B, H, W ---11111 ICR42 [R/W] B, H, W ---11111 ICR43 [R/W] B, H, W ---11111 00046CH ICR44 [R/W] B, H, W ---11111 ICR45 [R/W] B, H, W ---11111 ICR46 [R/W] B, H, W ---11111 ICR47 [R/W] B, H, W ---11111 000470H to 00047CH Block Interrupt control unit Unused (Continued) 32 MB91230 Series (Continued) Address Register Block +0 +1 +2 +3 000480H RSRR [R/W] B, H, W 10000000 STCR [R/W] B, H, W 00110011 TBCR [R/W] B, H, W 00XXXX00 CTBR [W] B, H, W XXXXXXXX 000484H CLKR [R/W] B, H, W 00000000 WPR [R/W] B, H, W XXXXXXXX DIVR0 [R/W] B, H, W 00000011 DIVR1 [R/W] B, H, W 00000000 000488H OSCCR [R/W] B XXXXXXX0 00048CH WPCR [R/W] B 00---000 Watch timer 000490H OSCR [R/W] B 00---000 Main clock oscillation stabilization wait timer 000494H to 0004FCH Unused 000500H PCR1 [R/W] B 00000000 PCR3 [R/W] B 00000000 000504H to 00051CH Unused 000520H to 0007F8H Unused 0007FCH MODR* XXXXXXXX Operation mode 000800H to 000AFCH Unused 000B00H to 000FFCH Unused 001000H to 001FFCH Unused Clock control Pull-up control register * : This register is set when the mode vector is fetched. Not user-accessible. 33 MB91230 Series ■ INTERRUPT VECTOR Interrupt source Interrupt number Interrupt level Offset TBR default address 10 16 Reset 0 00 3FCH 000FFFFCH Mode vector 1 01 3F8H 000FFFF8H System reserved 2 02 3F4H 000FFFF4H System reserved 3 03 3F0H 000FFFF0H System reserved 4 04 3ECH 000FFFECH System reserved 5 05 3E8H 000FFFE8H System reserved 6 06 3E4H 000FFFE4H Coprocessor absent trap 7 07 3E0H 000FFFE0H Coprocessor error trap 8 08 3DCH 000FFFDCH INTE instruction 9 09 3D8H 000FFFD8H Instruction break exception 10 0A 3D4H 000FFFD4H Operand break trap 11 0B 3C0H 000FFFD0H Step trace trap 12 0C 3CCH 000FFFCCH NMI request (tool) 13 0D 3C8H 000FFFC8H Undefined instruction exception 14 0E 3C4H 000FFFC4H NMI request (This model has no NMI request) 15 0F 15 (FH) fixed 3C0H 000FFFC0H External interrupt 0 16 10 ICR00 3BCH 000FFFBCH External interrupt 1 17 11 ICR01 3B8H 000FFFB8H External interrupt 2 18 12 ICR02 3B4H 000FFFB4H External interrupt 3 19 13 ICR03 3B0H 000FFFB0H External interrupt 4 20 14 ICR04 3ACH 000FFFACH External interrupt 5 21 15 ICR05 3A8H 000FFFA8H External interrupt 6 22 16 ICR06 3A4H 000FFFA4H External interrupt 7 23 17 ICR07 3A0H 000FFFA0H Reload timer 0 24 18 ICR08 39CH 000FFF9CH Reload timer 1 25 19 ICR09 398H 000FFF98H Reload timer 2 26 1A ICR10 394H 000FFF94H UART0(Reception completed) 27 1B ICR11 390H 000FFF90H UART0 (Transmission completed) 28 1C ICR12 38CH 000FFF8CH UART1 (Reception completed) 29 1D ICR13 388H 000FFF88H UART1 (Transmission completed) 30 1E ICR14 384H 000FFF84H UART2 (Reception completed) 31 1F ICR15 380H 000FFF80H UART2 (Transmission completed) 32 20 ICR16 37CH 000FFF7CH (Continued) 34 MB91230 Series Interrupt number Interrupt level Offset TBR default address 21 ICR17 378H 000FFF78H 34 22 ICR18 374H 000FFF74H A/D ch0 35 23 ICR19 370H 000FFF70H A/D ch1 36 24 ICR20 36CH 000FFF6CH External interrupt8 37 25 ICR21 368H 000FFF68H External interrupt9 38 26 ICR22 364H 000FFF64H External interrupt 10 39 27 ICR23 360H 000FFF60H External interrupt 11 40 28 ICR24 35CH 000FFF5CH External interrupt 12 41 29 ICR25 358H 000FFF58H External interrupt 13 42 2A ICR26 354H 000FFF54H External interrupt 14 43 2B ICR27 350H 000FFF50H External interrupt 15 44 2C ICR28 34CH 000FFF4CH Real-time clock 45 2D ICR29 348H 000FFF48H Main clock oscillation stabilization wait timer 46 2E ICR30 344H 000FFF44H Timebase timer 0 overflow 47 2F ICR31 340H 000FFF40H Reload timer 3 48 30 ICR32 33CH 000FFF3CH Watch timer 49 31 ICR33 338H 000FFF38H UD Counter 0 50 32 ICR34 334H 000FFF34H UD Counter 1 51 33 ICR35 330H 000FFF30H PPG 0/1 52 34 ICR36 32CH 000FFF2CH PPG 2/3 53 35 ICR37 328H 000FFF28H PPG 4/5 54 36 ICR38 324H 000FFF24H Free-run timer 0 55 37 ICR39 320H 000FFF20H Free-run timer 1 56 38 ICR40 31CH 000FFF1CH ICU 0 (capture) 57 39 ICR41 318H 000FFF18H ICU 1 (capture) 58 3A ICR42 314H 000FFF14H OCU 0 (match) 59 3B ICR43 310H 000FFF10H OCU 1 (match) 60 3C ICR44 30CH 000FFF0CH OCU 2 (match) 61 3D ICR45 308H 000FFF08H OCU 3 (match) 62 3E ICR46 304H 000FFF04H Delay interrupt source bit 63 3F ICR47 300H 000FFF00H System reserved (Used by REALOS) 64 40 2FCH 000FFEFCH System reserved (Used by REALOS) 65 41 2F8H 000FFEF8H System reserved 66 42 2F4H 000FFEF4H Interrupt source 10 16 UART3 (Reception completed) 33 UART3 (Transmission completed) (Continued) 35 MB91230 Series (Continued) 36 Interrupt number Interrupt level Offset TBR default address 43 2F0H 000FFEF0H 68 44 2ECH 000FFEECH System reserved 69 45 2E8H 000FFEE8H System reserved 70 46 2E4H 000FFEE4H System reserved 71 47 2E0H 000FFEE0H System reserved 72 48 2DCH 000FFEDCH System reserved 73 49 2D8H 000FFED8H System reserved 74 4A 2D4H 000FFED4H System reserved 75 4B 2D0H 000FFED0H System reserved 76 4C 2CCH 000FFECCH System reserved 77 4D 2C8H 000FFEC8H System reserved 78 4E 2C4H 000FFEC4H System reserved 79 4F 2C0H 000FFEC0H Used by INT instruction 80 to 255 50 to FF 2BCH to 000H 000FFEBCH to 000FFC00H Interrupt source 10 16 System reserved 67 System reserved MB91230 Series ■ PIN STATUS IN EACH CPU STATE Terms used as the status of pins mean as follows. • Input enabled Indicates that the input function can be used. • Input 0 fixed Indicates that the input level has been internally fixed to be “0” to prevent leakage when the input is released. • Output Hi-Z Means the placing of a pin in a high impedance state by preventing the transistor for driving the pin from driving. • Output is maintained Indicates the output in the output state existing immediately before this mode is established. If the device enters this mode with an internal output peripheral operating or while serving as an output port, the output is performed by the internal peripheral or the port output is maintained, respectively. • State existing immediately before is maintained When the device serves for output or input immediately before entering this mode, the device maintains the output or is ready for the input, respectively. 37 MB91230 Series • Pin Status List Pin Pin no. name Port name 1 P26/ P26 SCK2 2 P27/ SIN3 3 P30/ P30 SOT3 4 P31/ P31 SCK3 5 P32/ AIN0 6 P33/ BIN0 7 P34/ ZIN0 8 P35/ AIN1 9 P36/ BIN1 10 P37/ ZIN1 11 12 P27 P32 P33 P34 P35 P36 Specified function name At initializing Input Output Input/ Function Output name SIN3 AIN0 BIN0 ZIN0 AIN1 BIN1 SOT3 Remarks HIZ = 0 HIZ = 1 SCK2 P26 P27 P30 Pull-up options can be selected SCK3 P31 Pull-up options can be selected P32 Pull-up options can be selected P33 Pull-up options can be selected P34 Output Hi-Z/ Input enabled Retention of the immediately prior state Retention of the immediately prior state Output Hi-Z/ Input 0 fixed Pull-up options can be selected P35 Pull-up options can be selected P36 Pull-up options can be selected Pull-up options can be selected ZIN1 P37 P40/ P40 PPG0 PPG 0 P40 P41/ P41 PPG1 PPG 1 P41 P37 Reset initialization At Stop mode At sleep mode (Continued) 38 MB91230 Series Pin no. Pin name Port name Specified function name Input At initializing Reset Output Input/ Function Output name initialization At sleep mode At Stop mode Remarks HIZ = 0 HIZ = 1 13 X0A 14 X1A 16 VSS 17 VCC3 15 VCC3B/ VCC 18 P42/ PPG2 P42 PPG2 P42 19 P43/ PPG3 P43 PPG3 P43 20 P44/ TOT0 P44 TOT0 P44 21 P45/ TOT1 P45 TOT1 P45 22 P46/ TOT2 P46 TOT2 P46 23 P47/ CKOT P47 CKOT P47 24 P50/ INT8 P50 INT8 P50 25 P51/ INT9 P51 INT9 P51 26 P52/ INT10 P52 INT10 P52 P53/ 27 INT11/ P53 PPG4 INT11 PPG4 P53 P54/ 28 INT12/ P54 PPG5 INT12 PPG5 P54 P55/ 29 INT13/ P55 TIN2 INT13 TIN2 P55 P56/ 30 INT14/ P56 TIN1 INT14 TIN1 P56 Retention of the immediately prior state Output Hi-Z/ Input enabled Output Hi-Z/ Input 0 fixed Retention of the immediately prior state P: Retention P: of the Output immediately Hi-Z prior state F: F: Input Input enabled enabled Note : P : Port selected, F : Specified function selected (Continued) 39 MB91230 Series Pin no. Pin name Port name Specified function name Input P57/ INT15/ 31 P57 TIN0/ ADTG0 32 PF3/ TOT3 PF3 PF4/ 33 TIN3/ PF4 ADTG1 INT15 TIN0 ADTG0 Output At initializing Input/ Function Reset Output name initialization At sleep mode P57 TOT3 PF3 TIN3 ADTG1 PF4 Output Hi-Z/ Input enabled Retention of the immediately prior state At Stop mode HIZ = 0 HIZ = 1 Remarks P: Retention P: of the Output immediately Hi-Z prior state F: F: Input 0 Input enabled enabled Retention of the immediately prior state Output Hi-Z/ Input 0 fixed 34 PD0/ DA0 PD0 DA0 PD0 35 PD1/ DA1 PD1 DA1 PD1 36 AVCC 37 AVRH 38 AVSS 39 PC0/ AN0 PC0 AN0 PC0 40 PC1/ AN1 PC1 AN1 PC1 41 PC2/ AN2 PC2 AN2 PC2 42 PC3/ AN3 PC3 AN3 PC3 43 PC4/ AN4 PC4 AN4 PC4 44 PC5/ AN5 PC5 AN5 PC5 45 PC6/ AN6 PC6 AN6 PC6 46 PC7/ AN7 PC7 AN7 PC7 Output Hi-Z/ Input enabled Retention of the immediately prior state Retention of the immediately prior state Output Hi-Z/ Input 0 fixed Output Hi-Z/ Input enabled Retention of the immediately prior state Retention of the immediately prior state Output Hi-Z/ Input 0 fixed Note : P : Port selected, F : Specified function selected (Continued) 40 MB91230 Series Pin Pin no. name Port name Specified function name Input Output At initializing Input/ Function Reset Output name initialization At sleep mode At Stop mode HIZ = 0 HIZ = 1 47 VSS 48 VCC3IO 49 P80/ SEG0 P80 SEG0 P80 50 P81/ SEG1 P81 SEG1 P81 51 P82/ SEG2 P82 SEG2 P82 52 P83/ SEG3 P83 SEG3 P83 53 P84/ SEG4 P84 SEG4 P84 54 P85/ SEG5 P85 SEG5 P85 55 P86/ SEG6 P86 SEG6 P86 P87/ 56 SEG7 P87 SEG7 P87 57 P90/ SEG8 P90 SEG8 P90 58 P91/ SEG9 P91 SEG9 P91 59 P92/ P92 SEG10 SEG10 P92 60 P93/ P93 SEG11 SEG11 P93 61 P94/ P94 SEG12 SEG12 P94 62 P95/ P95 SEG13 SEG13 P95 63 P96/ P96 SEG14 SEG14 P96 Output Hi-Z/ Input enabled Retention of the immediately prior state Remarks P: Output Hi-Z/ Input 0 fixed Retention of the immediately F: prior state Retention of the immediately prior state Note : P : Port selected, F : Specified function selected (Continued) 41 MB91230 Series Pin Pin Port no. name name Specified function name Input Output At initializing Input/ Function Reset Output name initialization At sleep mode At Stop mode HIZ = 0 HIZ = 1 64 P97/ P97 SEG15 SEG15 P97 65 PA0/ PA0 SEG16 SEG16 PA0 66 PA1/ PA1 SEG17 SEG17 PA1 67 PA2/ PA2 SEG18 SEG18 PA2 68 PA3/ PA3 SEG19 SEG19 PA3 PA4/ 69 PA4 SEG20 SEG20 PA4 70 PA5/ PA5 SEG21 SEG21 PA5 71 PA6/ PA6 SEG22 SEG22 PA6 72 PA7/ PA7 SEG23 SEG23 PA7 73 PB0/ PB0 SEG24 SEG24 PB0 74 PB1/ PB1 SEG25 SEG25 PB1 75 VCC 76 VSS 77 PB2/ PB2 SEG26 SEG26 PB2 78 PB3/ PB3 SEG27 SEG27 PB3 79 P64/ P64 SEG28 SEG28 Output Hi-Z/ Input enabled Output Hi-Z/ Input enabled P64 Retention of the immediately prior state Retention of the immediately prior state Remarks P: Output Hi-Z/ Input 0 fixed Retention of the immediately F : prior state Retention of the immediately prior state P: Output Hi-Z/ Input 0 fixed Retention of the immediately F: prior state Retention of the immediately prior state opendrain pin, IOL = 20 mA Note : P : Port selected, F : Specified function selected (Continued) 42 MB91230 Series Pin Pin Port no. name name Specified function name Input 80 81 P65/ P65 SEG29 P66/ P66 SEG30 Output SEG29 SEG30 At initializing Input/ Function Reset Output name initialization At sleep mode At Stop mode HIZ = 0 HIZ = 1 Remarks P65 opendrain pin, IOL = 20 mA P66 opendrain pin, IOL = 20 mA Output Hi-Z/ Input enabled P: Output Hi-Z/ Retention Retention Input 0 fixed openof the of the drain immediately immediately F : pin, prior state prior state Retention IOL = of the 20 mA immediately prior state 82 P67/ P67 SEG31 SEG31 P67 83 P70/ P70 COM0 COM0 P70 84 P71/ P71 COM1 COM1 P71 85 P72/ P72 COM2 COM2 P72 86 P73/ P73 COM3 COM3 P73 87 MOD2 88 MOD1 89 MOD0 90 INIT 91 V0 92 V1 93 V2 94 V3 Note : P : Port selected, F : Specified function selected (Continued) 43 MB91230 Series Pin Pin no. name Port name Specified function name At initializing Reset Input Output Input/ Function Output name initialization 95 P00/ SIN0 P00 SIN0 P00 96 P01/ SOT0 P01 SOT0 P01 97 P02/ SCK0 P02 98 P03/ SIN1 P03 SIN1 P03 99 P04/ SOT1 P04 SOT1 P04 100 P05/ SCK1 P05 101 P06/ IC0 P06 IC0 P06 102 P07/ IC1 P07 IC1 P07 P10/ 103 INT0 P11/ 104 INT1 P10 P11 INT0 At sleep mode At Stop mode Remarks HIZ = 0 HIZ = 1 SCK0 P02 SCK1 P05 INT1 Retention of the immediately prior state Output Hi-Z/ Input enabled Output Hi-Z/ Input 0 fixed Retention of the immediately prior state P: Retention P : Output of the Hi-Z immediately prior state F : Input enabled F : Input enabled P10 P11 105 VCC 106 VSS 107 X1 108 X0 Pull-up options can be selected Pull-up options can be selected Note : P : Port selected, F : Specified function selected (Continued) 44 MB91230 Series (Continued) Pin Pin Port no. name name Specified function name Input P12/ 109 INT2 P13/ 110 INT3 P14/ 111 INT4 P15/ 112 INT5 P16/ 113 INT6 P17/ 114 INT7 P12 P13 P14 P15 P16 INT2 INT3 INT4 INT5 INT6 At initializing Input/ Function Reset Output Output name initialization P15 P20 P21/ 116 CKI1/ P21 OP1 CKI1 OP1 P21 P22/ 117 PWI0/ P22 OP2 PWI0 OP2 P22 P23/ 118 PWI1/ P23 OP3 PWI1 OP3 P23 SIN2 P24 SOT2 P25 P25/ P25 SOT2 Output Hi-Z/ Input enabled Pull-up options can be selected Pull-up options can be selected Pull-up options can be selected P16 120 P: Retention P: of the Output immediately Hi-Z prior state F: F: Input Input enabled enabled P14 CKI0 OP0 P24 HIZ = 1 P13 P20/ 115 CKI0/ P20 OP0 P24/ SIN2 HIZ = 0 Pull-up options can be selected P17 119 Remarks P12 INT7 At Stop mode Pull-up options can be selected P17 At sleep mode Retention of the immediately prior state Pull-up options can be selected Retention of the immediately prior state Output Hi-Z/ Input 0 fixed Note : P : Port selected, F : Specified function selected 45 MB91230 Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings MB91F233, MB91V230 Parameter Symbol Rating Unit Min Max VCC VSS−0.5 VSS + 6.0 V VCC3 VSS−0.5 VSS + 4.0 V VCC3IO VSS−0.5 VSS + 4.0 V AVCC VSS−0.5 VSS + 4.0 V VI VSS−0.5 VCC + 0.5 V VIND VSS−0.5 VCC + 0.5 V Analog pin input voltage* VIA VSS−0.5 AVCC + 0.5 V Output voltage* VO VSS−0.5 VCC + 0.5 V Operating ambient temperature Ta −40 + 85 °C Tstg −55 + 125 °C Power supply voltage* Analog power supply voltage* Input voltage* Input voltage* (open-drain) Storage temperature Remarks * : This parameter is based on VSS = AVSS = 0.0 V. MB91F233L, MB91233L Parameter Symbol Rating Unit Min Max VCC VSS−0.5 VSS + 4.0 V VCC3 VSS−0.5 VSS + 4.0 V VCC3IO VSS−0.5 VSS + 4.0 V AVCC VSS−0.5 VSS + 4.0 V VI VSS−0.5 VCC + 0.5 V VIND VSS−0.5 VCC + 0.5 V Analog pin input voltage* VIA VSS−0.5 AVCC + 0.5 V Output voltage* VO VSS−0.5 VCC + 0.5 V Operating ambient temperature Ta −40 + 85 °C Tstg −55 + 125 °C Power supply voltage* Analog power supply voltage* Input voltage* Input voltage* (open-drain) Storage temperature Remarks * : This parameter is based on VSS = AVSS = 0.0 V. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 46 MB91230 Series 2. Recommended Operating Conditions MB91F233, MB91V230 (VSS = AVSS = 0.0 V) Parameter Symbol Operating ambient temperature Power supply voltage Analog power supply voltage LCD reference voltage Value Ta −40 + 85 °C VCC 4.00 5.25 V *1 VCC3 3.00 3.60 V *4 3.00 3.60 V 2.20 3.60 V VCC3IO 3.00 3.60 V AVCC 3.00 3.60 V V3 5.25 V VCC3B Symbol Operating ambient temperature LCD reference voltage *2 *3 (VSS = AVSS = 0.0 V) Parameter Analog power supply voltage Remarks Max MB91F233L, MB91233L Power supply voltage Unit Min Value Unit Remarks Min Max Ta −40 + 85 °C VCC 3.00 3.60 V *1 VCC3 3.00 3.60 V *4 3.00 3.60 V 2.20 3.60 V VCC3IO 3.00 3.60 V AVCC 3.00 3.60 V V3 3.60 V VCC3B *2 *3 *1 : The standard power-supply voltage varies with the model of product. *2 : Only for backup. Set VCC3 = AVCC = VCC3IO. *3 : V3 must not exceed VCC. *4 : For the relationships between VCC3 and operating frequencies, see section “4. AC Characteristics (4) Operation Assurance Range”. For the MB91V230, please inquire separately. Note : For normal use, set VCC3 = VCC3B = AVCC = VCC3IO. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 47 MB91230 Series 3. DC Characteristics MB91V230, MB91F233 (VCC = 4.0 V to 5.25 V, VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = −40 °C to +85 °C) Parameter Symbol Pin name ICC Power supply current ICCT VCC3 ICCH ICCS "H" level input voltage VIL "H" level output voltage VOH "L" level output voltage VOL Open-drain output leakage current Value Unit Min Typ Max FLASH model normal operation, Ta = +25 °C, FCP = 33 MHz, FCPP = 16.5 MHz 65 75 mA FLASH model normal operation, Ta = +25 °C, FCP = 33 MHz, FCPP = 33 MHz 73 83 mA RTC mode, @Ta = +25 °C, FCP = 32 kHz 20 50 µA STOP mode, @Ta = +25 °C, FCP = 0 kHz 5 50 µA SLEEP mode FCP = 33 MHz, FCPP = 16.5 MHz 21 25 mA SLEEP mode FCP = 33 MHz, FCPP = 33 MHz 30 35 mA VCC × 0.8 VCC V X0A VCC3B = 2.2 V to 3.6 V VCC3B × 0.8 VCC3B V VSS VCC × 0.2 V X0A VCC3B = 2.2 V to 3.6 V VSS VSS + 0.4 V IOH = −4 mA VCC −0.5 VCC V IOL = 4 mA VSS 0.4 V VIH “L” level input voltage Input leakage current Conditions P64 to 67 IOL = 20 mA IIL −5 5 µA Ileak −10 10 µA Remarks Watch timer, RTC, LCDC VCC3 = VCC3B = 2.4 V When external clock is used When external clock is used (Continued) 48 MB91230 Series (Continued) (VCC = 4.0 V to 5.25 V, VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = −40 °C to +85 °C) Parameter Symbol Pin name RLCD V0 - V1, V1 - V2, V2 - V3 COM0 to COM3 output impedance RVCOM COM0 to COM3 SEG00 to SEG31 output impedance RVSEG SEG00 to SEG31 ILCDC V0 to V3, COM0 to COM3, SEG00 to SEG31 LCD division resistance LCDC leakage current Conditions Value Unit Min Typ Max 50 100 200 kΩ 2.5 kΩ 15 kΩ −5 5 µA Remarks V1 to V3 = 5.0 V 49 MB91230 Series MB91F233L, MB91233L (VCC = VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = −40 °C to +85 °C) Parameter Symbol Pin name ICC ICC Power supply current Vcc3 Value Unit Min Typ Max FLASH model normal operation, Ta = +25 °C, FCP = 33 MHz, FCPP = 16.5 MHz 65 75 mA FLASH model normal operation, Ta = +25 °C, FCP = 33 MHz, FCPP = 33 MHz 73 83 mA ROM model normal operation, Ta = +25 °C, FCP = 33 MHz, FCPP = 16.5 MHz 45 55 mA ROM model normal operation, Ta = +25 °C, FCP = 33 MHz, FCPP = 33 MHz 55 65 mA ICCT RTC mode, @Ta = +25 °C, FCP = 32 kHz 20 50 µA ICCH STOP mode, @Ta = +25 °C, FCP = 0 MHz 5 50 µA SLEEP mode FCP = 33 MHz, FCPP = 16.5 MHz 21 25 mA SLEEP mode FCP = 33 MHz, FCPP = 33 MHz 30 35 mA ICCS "H" level input voltage Conditions VCC × 0.8 VCC V X0A VCC3B = 2.2 V to 3.6 V VCC3B × 0.8 VCC3B V VSS VCC × 0.15 V X0A VCC3B = 2.2 V to 3.6 V VSS VSS + 0.4 V VCC = 3.3 V, IOH = −2 mA VCC −0.5 VCC V VIH "L" level input voltag VIL "H" level output voltage VOH Remarks Watch timer, RTC, LCDC VCC3 = VCC3B = 2.4 V When external clock is used When external clock is used (Continued) 50 MB91230 Series (Continued) (VCC = VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = −40 °C to +85 °C) Parameter "L" level output voltage Input leakage current Symbol VOL Pin name Conditions IOL = 2 mA P64 to 67 IOL = 10 mA Value Unit Min Typ Max VSS 0.4 V IIL −5 5 µA Open-drain output leakage current Ileak −10 10 µA LCD division resistance RLCD V0 - V1, V1 - V2, V2 - V3 50 100 200 kΩ COM0 to COM3 output impedance RVCOM COM0 to COM3 2.5 kΩ SEG00 to SEG31 output impedance RVSEG SEG00 to SEG31 15 kΩ ILCDC V0 to V3, COM0 to COM3, SEG00 to SEG31 −5 −5 µA LCDC leakage current Remarks V1 to V3 = 5.0 V 51 MB91230 Series 4. AC Characteristics (1) Main clock input standard (MB91V230, MB91F233 : VCC = 4.0 V to 5.25 V, VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = −40 °C to +85 °C) (MB91F233L, MB91233L : VCC = VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = −40 °C to +85 °C) Symbol Parameter Pin name Value Conditions Min Typ Max Unit Input frequency FC 3.6 4 4.2 MHz Input clock cycle tCYL 250 ns Input clock pulse width PWH/tCYL PWL/tCYL 40 60 % Input clock rise time and fall time tCR tCF 5 ns Internal operating clock frequency FCP 33.6 MHz Internal operating clock cycle time tCP 29.7 ns Peripheral clock frequency FCPP 33.6 MHz Peripheral clock cycle time tCYCP 29.7 ns X0 Remarks At external clock Peripheral clock is derived from internal operating clock divided by 1/1 to 1/16. tCYL 0.8 × VCC3 0.8 × VCC3 X0 VSS + 0.4 PWH VSS + 0.4 PWL tCF 52 0.8 × VCC3 tCR MB91230 Series (2) Subclock input standard (MB91V230, MB91F233 : VCC = 4.0 V to 5.25 V, VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = −40 °C to +85 °C) (MB91F233L, MB91233L : VCC = VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = −40 °C to +85 °C) Symbol Parameter Input frequency FCL Input clock cycle tLCYL Pin name Value Conditions Remarks kHz At external clock Typ Max 32.768 28.571 32.768 35.714 28.0 35.0 µs X0A Unit Min Input clock pulse width PWLH/tLCYL PWLL/tLCYL 45 55 % Input clock rise time and fall time tCR/tLCYL tCF/tLCYL 5 % At external clock tLCYL 0.8 × VCC3B 0.8 × VCC3B X0A 0.8 × VCC3B VSS + 0.4 PWLH VSS + 0.4 PWLL tCF tCR 53 MB91230 Series (3) Operation Assurance Range 4.0 Internal power supply voltage VCC3 [V] 3.8 33.6 MHz@ 3.6 V 3.6 3.4 33.6 MHz@ 3.3 V 8 MHz 3.2 3.0 PLL OFF 32 MHz@ 3.0 V PLL ON 33.6 MHz@ 3.0 V 2.8 2.6 28 MHz@ 2.7 V 2.4 MB91F233 MB91F233L 2.2 MB91233L 2.0 1.8 32 kHz 5 10 15 20 25 Internal operation frequency [MHz] 54 30 35 40 MB91230 Series (4) PLL oscillation stabilization time (LOCK UP time) (MB91V230, MB91F233 : VCC = 4.0 V to 5.25 V, VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = −40 °C to + 85 °C) (MB91F233L, MB91233L : VCC = VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = −40 °C to + 85 °C) Parameter PLL oscillation stabilization (LOCK UP time) Symbol tLOCK value Min Max 500 Unit Remarks µs Time from when the PLL starts operating to when its oscillation becomes stable (5) Reset input standards (MB91V230, MB91F233 : VCC = 4.0 V to 5.25 V, VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = −40 °C to + 85 °C) (MB91F233L, MB91233L : VCC = VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = −40 °C to + 85 °C) Parameter Reset input time (at power-on) Reset input time (other than at power-on) Symbol Pin name Conditions tINITX INIT Value Unit Remarks ns *1 ns *2 Min Max tCP × 10 *1 : When turning the power on, keep INIT input until the oscillation circuit provides stable oscillation. *2 : tCP indicates cycle time of CPU operating clock. tINITX INIT VIL VIL 55 MB91230 Series (6)UART timing (MB91V230, MB91F233 : VCC = 4.0 V to 5.25 V, VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = −40 °C to +85 °C) (MB91F233L, MB91233L : VCC = VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = −40 °C to +85 °C) Parameter Symbol Pin name Serial clock cycle time tSCYC SCK ↓ → SOT delay time tSLOV Valid SIN → SCK ↑ tIVSH SCK ↑ → Valid SIN hold time Conditions Unit Remarks Min Max SCK0 to SCK2 8 tCYCP * ns SCK0 to SCK2, SOT0 to SOT2 −80 80 ns Internal shift clock SCK0 to SCK2, operation SIN0 to SIN2 100 ns tSHIX SCK0 to SCK2, SIN0 to SIN2 60 ns Serial clock “H” pulse width tSHSL SCK0 to SCK2 4 tCYCP * ns Serial clock “L” pulse width tSLSH SCK0 to SCK2 4 tCYCP* ns SCK ↓ → SOT delay time tSLOV 150 ns Valid SIN → SCK ↑ tIVSH 60 ns SCK ↑ → Valid SIN hold time tSHIX 60 ns SCK0 to SCK2, SOT0 to SOT2 External shift clock operation SCK0 to SCK2, SIN0 to SIN2 SCK0 to SCK2, SIN0 to SIN2 * : tCYCP represents the cycle time of peripheral operating clock. Note : This specification applies to clock synchronous mode operation. 56 Value MB91230 Series • Internal shift clock mode tSCYC VOH SCK0 to SCK2 VOL VOL tSLOV VOH SOT0 to SOT2 VOL tIVSH SIN0 to SIN2 tSHIX VOH VOH VOL VOL • External shift clock mode tSLSH SCK0 to SCK2 tSHSL VOH VOL VOH VOL tSLOV VOH SOT0 to SOT2 VOL tIVSH SIN0 to SIN2 tSHIX VOH VOH VOL VOL 57 MB91230 Series (7) Free-run timer clock, Reload timer event input, Up/down counter input, Input capture input, Interrupt input timing (MB91V230, MB91F233 : VCC = 4.0 V to 5.25 V, VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = −40 °C to + 85 °C) (MB91F233L, MB91233L : VCC = VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = −40 °C to + 85 °C) Parameter Input pulth width Symbol tTIWH tTIWL Pin name CKI0, CKI1 TIN0, TIN1, TIN2 IC0, IC1 AIN0, AIN1 BIN0, BIN1 ZIN0, ZIN1 Value Conditions INT0 to INT15 Unit Remarks Min Max tCYCP × 2 ns * tCYCP × 3 ns * * : tCYCP indicates peripheral clock cycle time. tTIWH tTIWL VIH VIL VIH VIL (8) A/D trigger, PWI (PWC) input timing (MB91V230, MB91F233 : VCC = 4.0 V to 5.25 V, VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = −40 °C to + 85 °C) (MB91F233L, MB91233L : VCC = VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = −40 °C to + 85 °C) Value CondiParameter Symbol Pin name Unit Remarks tions Min Max A/D trigger input (falling) tTADTG ADTG0 ADTG1 tCYCP × 2 ns * PWI (PWC) input (rising) tPWI PWI0, PWI1 tCYCP × 2 ns * * : tCYCP indicates peripheral clock cycle time. tTADTG tTPWI VIH VIL 58 VIL VIH MB91230 Series 5. Electrical Characteristics for the A/D Converter (VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, AVRH = 3.0 V to 3.6 V, Ta = 0 °C to +85 °C) Value Parameter Unit Remarks Min Typ Max 10 bit −5.0 +5.0 LSB −3.5 +3.5 LSB Differential linear error*1 −2.5 +2.5 LSB 1 −2.0 +1.0 +6.0 LSB AVRH−5.5 AVRH−1.0 AVRH+3.0 LSB 1.69*2 µs 3.6 mA 5 µA 470 µA AVRH = 3.0 V, At AVRL = 0.0 V*3 10 µA At power-down*4 Analog input capacitance 40 pF Inter-channel disparity 4 LSB Resolution Total error* 1 Nonlinear error* 1 Zero transition voltage* Full transition voltage* 1 Conversion time Power supply voltage (analog+digital) Reference power supply current (between AVRH and AVRL) AVCC = 3.3 V, At AVRH = 3.3 V At CPU sleep mode *1 : Measured in the CPU sleep state *2 : It depends on the clock cycle supplied to peripheral resources. *3 : AVRL pin is only for FLGA package product. AVRL pin is connected to AVSS inside the IC on QFP package product. *4 : The current when the CPU is in stop mode and the A/D converter is not operaring. 59 MB91230 Series • About the external impedance of the analog input and its sampling time • A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sampling and hold capacitor is insufficient, adversely affecting A/D conversion precision. • Analog input circuit model R Analog input Comparator C During sampling : ON R C MB91233L 0.18 kΩ (Max) 63.0 pF (Max) MB91F233 0.18 kΩ (Max) 39.0 pF (Max) MB91F233L 0.18 kΩ (Max) 39.0 pF (Max) Note : The values are reference values. • To satisfy the A/D conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the resistor value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. • The relationship between the external impedance and minimum sampling time (External impedance = 0 kΩ to 20 kΩ) MB91F233 MB91F233L 100 90 80 70 60 50 40 30 20 10 0 External impedance (kΩ) External impedance (kΩ) (External impedance = 0 kΩ to 100 kΩ) MB91233L 0 5 10 15 20 25 30 Minimum sampling time (µs) 35 MB91F233 MB91F233L 20 18 16 14 12 10 8 6 4 2 0 MB91233L 0 1 2 3 4 5 6 7 8 Minimum sampling time (µs) • If the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin. • About errors As |AVRH − AVSS| becomes smaller, values of relative errors grow larger. 60 MB91230 Series 6. Electrical Characteristics for the D/A Converter (VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = 0 °C to +85 °C) Parameter Value Unit Remarks Min Typ Max 8 bit Nonlinear error −2.0 +2.0 LSB When the output is unloaded Differential linear error −1.0 +1.0 LSB When the output is unloaded 0.6 µs When load capacitance (CL) = 20 pF 3.0 µs When load capacitance (CL) = 100 pF 2.0 2.9 3.8 kΩ 40 µA 10 µs conversion, when the output is unloaded 460* µA When the input digital code is fixed at 7AH or 85H 0.1 µA At power-down Resolution Conversion speed Output impedance Analog current * : The current consumption by this D/A converter varies with input digital code. This standard value indicates the current consumed when the digital code that maximizes the current consumption is input. 7. Flash Memory Write/Erase Characteristics Parameter Conditions Value Min Typ Max Unit Remarks Sector erase time Ta = + 25 °C, Vcc = 5.0 V 1 15 s Excludes 00H programming prior erasure Chip erase time Ta = + 25 °C, Vcc = 5.0 V 10 s Excludes 00H programming prior erasure Byte write time Ta = + 25 °C, Vcc = 5.0 V 8 3,600 µs Not including system-level overhead time. Chip write time Ta = + 25 °C, Vcc = 5.0 V 2.1 s Not including system-level overhead time. 10,000 cycle 20 year Erase/write cycle Flash data retention time Average Ta = + 85 °C * * : This value comes from the technology qualification (using Arrhenius equation to translate high temperature measurements into normalized value at + 85 °C). 61 MB91230 Series ■ ORDERING INFORMATION Part number 62 Package MB91V230CR-ES 401-pin ceramic PGA (PGA-401C-A02) MB91F233PFF-GE1 120-pin plastic LQFP (FPT-120P-M05) MB91F233LPFF-GE1 120-pin plastic LQFP (FPT-120P-M05) MB91F233LLGA-GE1 128-pin plastic FLGA (LGA-128P-M01) MB91233LPFF-G-xxx-BNDE1 120-pin plastic LQFP (FPT-120P-M05) MB91233LLGA-Gxxx-BNDE1 128-pin plastic FLGA (LGA-128P-M01) Remarks MB91230 Series ■ PACKAGE DIMENSIONS 401-pin Ceramic PGA (PGA-401C-A02) 48.26 ± 0.55 SQ (1.900 ± .022) 2.54 (.100) TYP 0.40 ± 0.10 DIA (.016 ± .004) 1.00 (.039) DIA TYP (4 PLCS) 45.72 (1.800) REF INDEX AREA 1.02 (.040) C TYP (4 PLCS) 1.20 ± 0.25 (.047 ± .010) EXTRA INDEX PIN 3.40 ± 0.40 (.134 ± .016) 5.27 (.207) MAX C 1994 FUJITSU LIMITED R401002SC-2-2 Dimensions in mm (inches) . Note : The values in parentheses are reference values. (Continued) 63 MB91230 Series Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 120-pin Plastic LQFP (FPT-120P-M05) 16.00±0.20(.630±.008)SQ * 14.00±0.10(.551±.004)SQ 90 61 91 60 0.08(.003) Details of "A" part +0.20 1.50 –0.10 +.008 (Mounting height) .059 –.004 INDEX 120 31 "A" 0~8˚ LEAD No. 1 0.40(.016) 30 0.16±0.03 (.006±.001) 0.07(.003) M 0.145±0.055 (.006±.002) 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) C 0.10±0.10 (.004±.004) (Stand off) 0.25(.010) 2003 FUJITSU LIMITED F120006S-c-4-5 Dimensions in mm (inches) . Note : The values in parentheses are reference values. (Continued) 64 MB91230 Series (Continued) 128-pin plastic FLGA (LGA-128P-M01) 8.30(.327) REF 7.15(.282) REF 9.00±0.10(.354±.004)SQ 0.65(.026) TYP 12 11 10 9 8 7 6 5 4 3 2 1 8.30(.327) REF 7.15(.282) REF 0.65(.026) TYP (0.50) ((.020)) M L K J H G F E D C B A INDEX AREA 1.00(.040)MAX (Seated Height) 3-ø0.50 (3-ø.020) (0.50) ((.020)) Index 128-ø0.35±0.05 (128-ø.014±.002) ø0.08(ø.003) M 0.08(.003) C 2004 FUJITSU LIMITED L128001S-c-1-1 Dimensions in mm (inches) . Note : The values in parentheses are reference values. 65 MB91230 Series FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F0410 2004 FUJITSU LIMITED Printed in Japan