HD74ACT161/HD74ACT163 Synchronous Presettable Binary Counter Description The HD74ACT161 and HD74ACT163 are high-speed synchronous modulo-16 binary counters. They are synchronously presettable for application in programmable dividers and have two types of Count Enable inputs plus a Terminal Count output for versatility in forming synchronous multistage counters. The HD74ACT161 have an asynchronous Master Reset input that overrides all other inputs and forces the outputs Low. The HD74ACT163 has a Synchronous Reset input that overrides counting and parallel loading and allows the outputs to be simultaneously reset on the rising edge of the clock. Features • • • • • Synchronous Counting and Loading High-Speed Synchronous Expansion Typical Count Rate of 125 MHz Outputs Source/Sink 24 mA HD74ACT161 and HD74ACT163 have TTL-Compatible Inputs HD74ACT161/HD74ACT163 Pin Arrangement *R 1 16 VCC CP 2 15 TC P0 3 14 Q0 P1 4 13 Q1 P2 5 12 Q2 P3 6 11 Q3 CEP 7 10 CET GND 8 9 PE (Top view) Logic Symbol PE P0 P1 P2 P3 CEP CET TC CP *R Q0 Q1 Q2 Q3 * • MR for HD74ACT161 • SR for HD74AC163/HD74ACT163 2 HD74ACT161/HD74ACT163 Pin Names CEP CET CP MR (HD74ACT161) SR (HD74ACT163/HD74ACT163) P 0 to P3 PE Q0 to Q3 TC Count Enable Parallel Input Count Enable Trickle Input Clock Pulse Input Asynchronous Master Reset Input Synchronous Reset Input Parallel Data Inputs Parallel Enable Input Flip-Flop Outputs Terminal Count Output Functional Description The HD74ACT161 and HD74ACT163 count in modulo-16 binary sequence. From state 15 (HHHH) they increment to state 0 (LLLL). The clock inputs of all flip-flops are driven in parallel through a clock buffer. Thus all changes of the Q outputs (except due to Master Reset of the HD74ACT161) occur as a reset of, and synchronous with, the Low-to-High transition of the CP input signal. The circuits have four fundamental modes of operation, in order of precedence: asynchronous reset (HD74ACT161), synchronous reset (HD74ACT163), parallel load, countup and hold. Five control inputs – Master Reste (MR, HD74ACT161), Synchronous Reset (SR, HD74ACT163), Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable Trickle (CET) – determine the mode of operation, as shown in the Mode Select Table. A Low signal on MR overrides all other inputs and asynchronously forces all outputs Low. A Low signal on SR overrides counting and parallel loading and allows all outputs to go Low on the next rising edge of CP. A Low signal on PE overrides counting and allows information on the Parallel Data (Pn) inputs to be loaded into the flip-flops on the next rising edge of CP. With PE and MR (HD74ACT161) or SR (HD74ACT163) High, CEP and CET permit counting when both are High. Conversely, a Low signal on either CEP or CET inhibits counting. The HD74ACT161 and HD74ACT163 use D-type edge-triggered flip-flops and changing the SR, PE, CEP and CET inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising edge of CP, are observed. The Terminal Count (TC) output is High when CET is High and counter is in state 15. To implement synchronous multistage counters, the TC outputs can be used with the CEP and CET inputs in two different ways. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, counters or registers. Logic Equations: Count Enable = CEP•CET•PE TC = Q 0•Q1•Q2•Q3•CET 3 HD74ACT161/HD74ACT163 Mode Select Table SR* 1 PE CET CEP Action on the Rising Clock Edge ( L X X X Reset (Clear) H L X X Load (Pn → Qn) H H H H Count (Increment) H H L X No change (Hold) H H X L No change (Hold) Note: 1. For HD74AC163/HD74ACT163 H : High Voltage Level L : Low Voltage Level X : Immaterial State Diagram 0 2 3 4 15 5 14 6 13 7 12 4 1 11 10 9 8 ) HD74ACT161/HD74ACT163 Block Diagram P1 P0 P2 P3 PE ’161 ’163 CEP CET ’163 ONRY CP TC CP ’161 ONRY CP D CP D CD O O Q0 Q0 DETAIL A DETAIL A DETAIL A Q1 Q2 Q3 DETAIL A MR ’161 SR ’163 Q0 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. DC Characteristics (unless otherwise specified) Item Symbol Max Unit Condition Maximum quiescent supply current I CC 80 µA VIN = VCC or ground, VCC = 5.5 V, Ta = Worst case Maximum quiescent supply current I CC 8.0 µA VIN = VCC or ground, VCC = 5.5 V, Ta = 25°C Maximum additional ICC/input (HD74ACT161/HD74ACT163) I CCT 1.5 mA VIN = VCC – 2.1 V, VCC = 5.5 V, Ta = Worst case 5 HD74ACT161/HD74ACT163 AC Characteristics: HD74ACT161 Ta = +25°C CL = 50 pF Ta = –40°C to +85°C CL = 50 pF Item Symbol VCC (V)*1 Min Typ Max Min Max Unit Maximum count frequency f max 5.0 115 125 — 100 — MHz Propagation delay CP to Qn (PE Input HIGH or LOW) t PLH 5.0 1.0 5.5 9.5 1.0 10.5 ns Propagation delay CP to Qn (PE Input HIGH or LOW) t PLH 5.0 1.0 6.0 10.5 1.0 11.5 ns Propagation delay CP to TC t PLH 5.0 1.0 7.0 11.0 1.0 12.5 ns Propagation delay CP to TC t PHL 5.0 1.0 8.0 12.5 1.0 13.5 ns Propagation delay CET to TC t PLH 5.0 1.0 5.5 8.5 1.0 10.0 ns Propagation delay CET to TC t PHL 5.0 1.0 6.0 9.5 1.0 10.5 ns Propagation delay MR to Q n t PHL 5.0 1.0 6.0 10.0 1.0 11.0 ns Propagation delay MR to TC t PHL 5.0 1.0 8.0 13.5 1.0 14.5 ns Note: 6 1. Voltage Range 5.0 is 5.0 V ± 0.5 V HD74ACT161/HD74ACT163 AC Operating Requirements: HD74ACT161 Ta = –40°C to +85°C CL = 50 pF Ta = +25°C CL = 50 pF Item Symbol VCC (V)*1 Typ Guaranteed Minimum Unit Set-up time, HIGH or LOW Pn to CP t su 5.0 4.0 9.5 11.5 ns Hold time, HIGH or LOW Pn to CP th 5.0 –5.0 0 0 ns Setup time, HIGH or LOW MR to CP t su 5.0 4.0 8.5 9.5 ns Hold time, HIGH or LOW MR to CP th 5.0 –5.5 –0.5 –0.5 ns Setup time, HIGH or LOW PE to CP t su 5.0 4.0 8.5 9.5 ns Hold time, HIGH or LOW PE to CP th 5.0 –5.5 –0.5 –0.5 ns Setup time, HIGH or LOW CEP or CET to CP t su 5.0 2.5 5.5 6.5 ns Hold time, HIGH or LOW CEP or CET to CP th 5.0 –3.0 0 0 ns Clock pulse width (Load) HIGH or LOW tw 5.0 2.0 3.0 3.5 ns Clock pulse width (Count) HIGH or LOW tw 5.0 2.0 3.0 3.5 ns MR pulse width, LOW tw 5.0 3.0 3.0 7.5 ns Recovery time MR to CP t rec 5.0 0 0 0.5 ns Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V Capacitance Item Symbol Typ Unit Condition Input capacitance CIN 4.5 pF VCC = 5.5 V Power dissipation capacitance CPD 45.0 pF VCC = 5.0 V 7 HD74ACT161/HD74ACT163 AC Characteristics: HD74ACT163 Ta = +25°C CL = 50 pF Ta = –40°C to +85°C CL = 50 pF Item Symbol VCC (V)*1 Min Typ Max Min Max Unit Maximum count frequency f max 5.0 120 128 — 105 — MHz Propagation delay CP to Qn (PE Input HIGH or LOW) t PLH 5.0 1.0 5.5 10.0 1.0 11.0 ns Propagation delay CP to Qn (PE Input HIGH or LOW) t PHL 5.0 1.0 6.0 11.0 1.0 12.0 ns Propagation delay CP to TC t PLH 5.0 1.0 7.0 11.5 1.0 13.5 ns Propagation delay CP to TC t PHL 5.0 1.0 8.0 13.5 1.0 15.0 ns Propagation delay CET to TC t PLH 5.0 1.0 5.5 9.0 1.0 10.5 ns Propagation delay CET to TC t PHL 5.0 1.0 6.0 10.0 1.0 11.0 ns Note: 8 1. Voltage Range 5.0 is 5.0 V ± 0.5 V HD74ACT161/HD74ACT163 AC Operating Requirements: HD74ACT163 Ta = –40°C to +85°C CL = 50 pF Ta = +25°C CL = 50 pF Item Symbol VCC (V)*1 Typ Guaranteed Minimum Unit Set-up time, HIGH or LOW Pn to CP t su 5.0 4.0 10.0 12.0 ns Hold time, HIGH or LOW Pn to CP th 5.0 –5.0 0.5 0.5 ns Setup time, HIGH or LOW SR to CP t su 5.0 4.0 10.0 11.5 ns Hold time, HIGH or LOW SR to CP th 5.0 –5.5 –0.5 –0.5 ns Setup time, HIGH or LOW PE to CP t su 5.0 4.0 8.5 10.5 ns Hold time, HIGH or LOW PE to CP th 5.0 –5.5 –0.5 0 ns Setup time, HIGH or LOW CEP or CET to CP t su 5.0 2.5 5.5 6.5 ns Hold time, HIGH or LOW CEP or CET to CP th 5.0 –3.0 0 0.5 ns Clock pulse width (Load) HIGH or LOW tw 5.0 2.0 3.5 3.5 ns Clock pulse width (Count) HIGH or LOW tw 5.0 2.0 3.5 3.5 ns Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V Capacitance Item Symbol Typ Unit Condition Input capacitance CIN 4.5 pF VCC = 5.5 V Power dissipation capacitance CPD 45.0 pF VCC = 5.0 V 9 Unit: mm 19.20 20.00 Max 1 7.40 Max 9 6.30 16 8 1.3 0.48 ± 0.10 2.54 Min 5.06 Max 2.54 ± 0.25 0.51 Min 1.11 Max 7.62 + 0.13 0.25 – 0.05 0° – 15° Hitachi Code JEDEC EIAJ Weight (reference value) DP-16 Conforms Conforms 1.07 g Unit: mm 10.06 10.5 Max 9 1 8 1.27 *0.42 ± 0.08 0.40 ± 0.06 0.10 ± 0.10 0.80 Max *0.22 ± 0.05 0.20 ± 0.04 2.20 Max 5.5 16 0.20 7.80 +– 0.30 1.15 0° – 8° 0.70 ± 0.20 0.15 0.12 M *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) FP-16DA — Conforms 0.24 g Unit: mm 9.9 10.3 Max 9 1 8 0.635 Max *0.42 ± 0.08 0.40 ± 0.06 0.15 *0.22 ± 0.03 0.20 ± 0.03 1.27 0.11 0.14 +– 0.04 1.75 Max 3.95 16 0.10 6.10 +– 0.30 1.08 0° – 8° 0.67 0.60 +– 0.20 0.25 M *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) FP-16DN Conforms Conforms 0.15 g Unit: mm 4.40 5.00 5.30 Max 16 9 1 8 0.65 0.13 M 1.10 Max 0.65 Max 0.10 *Dimension including the plating thickness Base material dimension 6.40 ± 0.20 0.07 +0.03 –0.04 0.20 ± 0.06 1.0 *0.17 ± 0.05 0.15 ± 0.04 0.08 *0.22 +– 0.07 0° – 8° 0.50 ± 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) TTP-16DA — — 0.05 g Cautions 1. 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