HD74AC165/HD74ACT165 Parallel-Load 8-bit Shift Register Description This 8-bit serial shift register shifts data from Q A to QH when clocked, Parallel inputs to each stage are enabled by a low level at the Shift/Load Input. Also included is a gated clock input and a complementary output from the eighth bit. Clocking is accomplished through a 2-input NOR gate permitting one input to be used as a clock inhibit function. Holding either of the clock inputs high inhibits clocking, and holding either clock input low with the Shift/Load input high enables the other clock input. Data transfer occurs on the positive going edge of the clock. Parallel loading is inhibited as long as the Shift/Load input is high. When taken low, data at the parallel inputs is loaded directly into the register independent of the state of the clock. Features • Outputs Source/Sink 24 mA • HD74ACT165 has TTL-Compatible Inputs HD74AC165/HD74ACT165 Pin Arrangement SL 1 16 VCC CP 2 Clock 15 Inhibit E 3 14 D F 4 13 C G 5 12 B H 6 11 A QH 7 10 SI Parallel Inputs GND 8 Parallel Inputs 9 QH (Top view) Logic Symbol 15 1 Clock Inhibit SL 2 CP 10 SI Pin Names A to H SI CP SL Clock Inhibit QH, QH 2 Parallel Inputs Serial Input Clock Input Shift Load Clock Inhibit Outputs 11 12 13 14 3 4 5 A F G H B C D E QH QH 9 7 6 HD74AC165/HD74ACT165 Truth Table Inputs Clock Parallel Internal Outputs Outputs SL Inhibit CP SI A ······ H QA QB QH L X X X a ······ h a b h H L L X X QAD QBO QHO H L H X H QAn QGn H L L X L QAn QCn X X QAD QBO QHO H H H : L : X : : X High Voltage Level Low Voltage Level Immaterial Low-to-High Clock Transition 3 HD74AC165/HD74ACT165 Logic Diagram Parallel Inputs A B Preset QA S Clock QA R Clear SI Preset QB S Clock QB R Clear SL CP C D Preset QC S Clock QC R Clear E Preset QD S Clock QD R Clear F Preset QE S Clock QE R Clear G Preset QF S Clock QF R Clear Preset QG S Clock QG R Clear H Preset QH S Clock QH R Clear Output QH Output QH Clock Inhibit DC Characteristics (unless otherwise specified) Item Symbol Max Unit Condition Maximum quiescent supply current I CC 80 µA VIN = VCC or ground, VCC = 5.5 V, Ta = Worst case Maximum quiescent supply current I CC 8.0 µA VIN = VCC or ground, VCC = 5.5 V, Ta = 25°C Maximum additional ICC/input (HD74ACT165) I CCT 1.5 mA VIN = VCC – 2.1 V, VCC = 5.5 V, Ta = Worst case 4 HD74AC165/HD74ACT165 AC Characteristics: HD74AC165 Ta = +25°C CL = 50 pF Ta = –40°C to +85°C CL = 50 pF Item Symbol VCC (V)*1 Min Typ Max Min Max Unit Maximum count f max 3.3 85 — — 70 — MHz 5.0 100 — — 90 — 3.3 1.0 11.0 17.5 1.0 20.5 5.0 1.0 8.0 11.5 1.0 13.5 3.3 1.0 12.0 18.0 1.0 21.5 5.0 1.0 8.5 12.5 1.0 14.5 3.3 1.0 13.5 19.5 1.0 22.5 5.0 1.0 9.5 13.5 1.0 15.5 3.3 1.0 9.0 14.0 1.0 16.5 5.0 1.0 6.5 9.5 1.0 11.0 3.3 1.0 11.5 20.5 1.0 23.5 5.0 1.0 8.5 14.0 1.0 16.0 3.3 1.0 10.0 16.5 1.0 19.5 5.0 1.0 7.5 11.0 1.0 12.5 frequency Propagation delay t PLH CP to QH or QH Propagation delay t PHL CP to QH or QH Propagation delay t PLH H to QH or QH Propagation delay t PHL H to QH or QH Propagation delay t PLH SL to Q H or QH Propagation delay SL to Q H or QH Note: t PHL ns ns ns ns ns ns 1. Voltage Range 3.3 is 3.3 V ± 0.3 V Voltage Range 5.0 is 5.0 V ± 0.5 V 5 HD74AC165/HD74ACT165 AC Operating Requirements: HD74AC165 Ta = –40°C to +85°C CL = 50 pF Ta = +25°C CL = 50 pF Item Symbol VCC (V)*1 Typ Guaranteed Minimum Unit Setup time, HIGH or LOW t su 3.3 3.5 5.0 6.0 ns 5.0 2.5 4.0 4.5 3.3 –1.0 0.5 0.5 5.0 –0.5 0.5 0.5 3.3 1.0 3.5 4.0 5.0 0.5 3.0 3.5 3.3 1.5 2.0 2.0 5.0 1.0 2.0 2.0 3.3 3.0 5.0 6.0 5.0 2.0 4.0 4.5 3.3 –2.0 0.0 0.0 5.0 –1.0 0.0 0.0 3.3 2.5 3.5 3.5 5.0 2.0 3.0 3.0 3.3 3.0 5.5 7.0 5.0 3.0 4.5 5.0 H to SL Hold time, HIGH or LOW th H to SL Setup time, HIGH or LOW t su Sin to CP Hold time, HIGH or LOW th Sin to CP Setup time, HIGH or LOW t su SL to CP Hold time, HIGH or LOW th SL to CP Recovery time clock inhibit t rec to CP Clock pulse width Note: 6 tw 1. Voltage Range 3.3 is 3.3 V ± 0.3 V Voltage Range 5.0 is 5.0 V ± 0.5 V ns ns ns ns ns ns ns HD74AC165/HD74ACT165 AC Characteristics: HD74ACT165 Ta = +25°C CL = 50 pF Ta = –40°C to +85°C CL = 50 pF Item Symbol VCC (V)*1 Min Typ Max Min Max Unit Maximum count frequency f max 5.0 7.0 — — 60 — MHz Propagation delay CP to QH or QH t PLH 5.0 1.0 8.5 13.5 1.0 15.5 ns Propagation delay CP to QH or QH t PHL 5.0 1.0 9.5 14.0 1.0 16.5 ns Propagation delay H to QH or QH t PLH 5.0 1.0 10.5 13.5 1.0 15.5 ns Propagation delay H to QH or QH t PHL 5.0 1.0 7.5 11.0 1.0 12.5 ns Propagation delay SL to Q H or QH t PLH 5.0 1.0 9.5 15.0 1.0 18.0 ns Propagation delay SL to Q H or QH t PHL 5.0 1.0 8.5 13.0 1.0 15.5 ns Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V 7 HD74AC165/HD74ACT165 AC Operating Requirements: HD74ACT165 Ta = –40°C to +85°C CL = 50 pF Ta = +25°C CL = 50 pF Item Symbol VCC (V)*1 Typ Guaranteed Minimum Unit Setup time, HIGH or LOW H to SL t su 5.0 3.0 4.0 4.5 ns Hold time, HIGH or LOW H to SL th 5.0 –1.0 0.0 0.0 ns Setup time, HIGH or LOW Sin to CP t su 5.0 0.5 3.0 3.5 ns Hold time, HIGH or LOW Sin to CP th 5.0 0.5 2.0 2.0 ns Setup time, HIGH or LOW SL to CP t su 5.0 2.0 4.0 4.5 ns Hold time, HIGH or LOW SL to CP th 5.0 –1.5 0.0 0.0 ns Recovery time clock inhibit to CP t rec 5.0 2.0 3.0 3.0 ns Clock pulse width tw 5.0 3.5 7.0 8.0 ns Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V Capacitance Item Symbol Typ Unit Condition Input capacitance CIN 4.5 pF VCC = 5.5 V Power dissipation capacitance CPD 5.0 pF VCC = 5.0 V 8 Unit: mm 19.20 20.00 Max 1 7.40 Max 9 6.30 16 8 1.3 0.48 ± 0.10 2.54 Min 5.06 Max 2.54 ± 0.25 0.51 Min 1.11 Max 7.62 + 0.13 0.25 – 0.05 0° – 15° Hitachi Code JEDEC EIAJ Weight (reference value) DP-16 Conforms Conforms 1.07 g Unit: mm 10.06 10.5 Max 9 1 8 1.27 *0.42 ± 0.08 0.40 ± 0.06 0.10 ± 0.10 0.80 Max *0.22 ± 0.05 0.20 ± 0.04 2.20 Max 5.5 16 0.20 7.80 +– 0.30 1.15 0° – 8° 0.70 ± 0.20 0.15 0.12 M *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) FP-16DA — Conforms 0.24 g Unit: mm 9.9 10.3 Max 9 1 8 0.635 Max *0.42 ± 0.08 0.40 ± 0.06 0.15 *0.22 ± 0.03 0.20 ± 0.03 1.27 0.11 0.14 +– 0.04 1.75 Max 3.95 16 0.10 6.10 +– 0.30 1.08 0° – 8° 0.67 0.60 +– 0.20 0.25 M *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) FP-16DN Conforms Conforms 0.15 g Unit: mm 4.40 5.00 5.30 Max 16 9 1 8 0.65 0.13 M 1.10 Max 0.65 Max 0.10 *Dimension including the plating thickness Base material dimension 6.40 ± 0.20 0.07 +0.03 –0.04 0.20 ± 0.06 1.0 *0.17 ± 0.05 0.15 ± 0.04 0.08 *0.22 +– 0.07 0° – 8° 0.50 ± 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) TTP-16DA — — 0.05 g Cautions 1. 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