HM5164160A Series HM5165160A Series 64M FP DRAM (4-Mword × 16-bit) 8k refresh/4k refresh ADE-203-596B (Z) Rev. 2.0 Nov. 25, 1997 Description The Hitachi HM5164160A Series, HM5165160A Series are CMOS dynamic RAMs organized as 4,194,304-word × 16-bit. They employ the most advanced CMOS technology for high performance and low power. The HM5164160A Series, HM5165160A Series offer Fast Page Mode as a high speed access mode. They have the package variations of standard 400-mil 50-pin plastic SOJ and standard 400-mil 50pin plastic TSOPII. Features • Single 3.3 V (±0.3 V) • Access time: 60 ns/70 ns (max) • Power dissipation Active mode : 432 mW/360 mW (max) (HM5164160A Series) : 630 mW/540 mW (max) (HM5165160A Series) Standby mode : 7.2 mW (max) : 1.08 mW (L-version) • Fast page mode capability • Refresh cycles RAS-only refresh 8192 cycles /64 ms (HM5164160A) 4096 cycles /64 ms (HM5165160A) /128 ms (HM5165160AL) (L-version) CBR/Hidden refresh 4096 cycles /64 ms (HM5164160A, HM5165160A) /128 ms (HM5165160AL) (L-version) • 4 variations of refresh RAS-only refresh CAS-before-RAS refresh Hidden refresh Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5164160A Series, HM5165160A Series Self refresh (L-version) • 2CAS-byte control • Battery backup operation (L-version) Ordering Information Type No. Access time Package HM5164160AJ-6 HM5164160AJ-7 60 ns 70 ns 400-mil 50-pin plastic SOJ (CP-50DA) HM5165160AJ-6 HM5165160AJ-7 60 ns 70 ns HM5164160ATT-6 HM5164160ATT-7 60 ns 70 ns HM5165160ATT-6 HM5165160ATT-7 60 ns 70 ns HM5165160ALTT-6 60 ns 2 Powered by ICminer.com Electronic-Library Service CopyRight 2003 400-mil 50-pin plastic TSOP II (TTP-50DB) HM5164160A Series, HM5165160A Series Pin Arrangement HM5164160AJ Series VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC VCC WE RAS NC NC NC NC A0 A1 A2 A3 A4 A5 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 HM5164160ATT Series VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC VSS LCAS UCAS OE NC NC A12 A11 A10 A9 A8 A7 A6 VSS (Top view) VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC VCC WE RAS NC NC NC NC A0 A1 A2 A3 A4 A5 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC VSS LCAS UCAS OE NC NC A12 A11 A10 A9 A8 A7 A6 VSS (Top view) Pin Description Pin name Function A0 to A12 Address input — Row/Refresh address A0 to A12 — Column address A0 to A8 I/O0 to I/O15 Data input/Data output RAS Row address strobe UCAS, LCAS Column address strobe WE Read/Write enable OE Output enable VCC Power supply VSS Ground NC No connection 3 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5164160A Series, HM5165160A Series Pin Arrangement HM5165160AJ Series VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC VCC WE RAS NC NC NC NC A0 A1 A2 A3 A4 A5 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 HM5165160ATT/ALTT Series VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC VSS LCAS UCAS OE NC NC NC A11 A10 A9 A8 A7 A6 VSS (Top view) Pin Description Pin name Function A0 to A11 Address input — Row/Refresh address A0 to A11 — Column address A0 to A9 I/O0 to I/O15 Data input/Data output RAS Row address strobe UCAS, LCAS Column address strobe WE Read/Write enable OE Output enable VCC Power supply VSS Ground NC No connection 4 Powered by ICminer.com Electronic-Library Service CopyRight 2003 VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC VCC WE RAS NC NC NC NC A0 A1 A2 A3 A4 A5 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 (Top view) 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC VSS LCAS UCAS OE NC NC NC A11 A10 A9 A8 A7 A6 VSS HM5164160A Series, HM5165160A Series Block Diagram (HM5164160A Series) RAS UCAS LCAS WE OE Timing and control A0 Column decoder A1 to Column • • • address buffers • • • Row address buffers A9 to A12 Row decoder A8 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array I/O buffers I/O0 to I/O15 5 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5164160A Series, HM5165160A Series Block Diagram (HM5165160A Series) RAS UCAS LCAS WE OE Timing and control Column decoder A0 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array Column A1 • • • to address buffers • • • Row decoder A9 Row address buffers A10 I/O buffers A11 Truth Table RAS LCAS UCAS WE OE Output Operation H D D D D Open Standby L L H H L Valid Lower byte Read cycle L H L H L Valid Upper byte L L L H L L L L L L H L L H H L L H L L Valid Word L* 2 D Open Lower byte Early write cycle L* 2 D Open Upper byte L* 2 D Open Word L* 2 H Undefined Lower byte Delayed write cycle L* 2 H Undefined Upper byte 2 H Undefined Word L L L L* L L H H to L L to H Valid Lower byte Read-modify-write cycle L H L H to L L to H Valid Upper byte L L L H to L L to H Valid Word 6 Powered by ICminer.com Electronic-Library Service CopyRight 2003 I/O0 to I/O15 HM5164160A Series, HM5165160A Series L H H D D Open Word RAS-only refresh cycle H to L H L H D Open Word CAS-before-RAS refresh cycle or H to L L H H D Open Word Self refresh cycle (L-version) H to L L L H D Open Word L L L H H Open Read cycle (Output disabled) Notes: 1. H: High (inactive) L: Low (active) D: H or L 2. t WCS ≥ 0 ns: Early write cycle t WCS < 0 ns: Delayed write cycle 3. Mode is determined by the OR function of the UCAS and LCAS. (Mode is set by the earliest of UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.) However write OPERATION and output High-Z control are done independently by each UCAS, LCAS. ex. if RAS = H to L, UCAS = H, LCAS = L, then CAS-before-RAS refresh cycle is selected. Absolute Maximum Ratings Parameter Symbol Value Unit Voltage on any pin relative to V SS VT –0.5 to VCC + 0.5 (≤ 4.6 V (max)) V Supply voltage relative to VSS VCC –0.5 to +4.6 V Short circuit output current Iout 50 mA Power dissipation PT 1.0 W Operating temperature Topr 0 to +70 °C Storage temperature Tstg –55 to +125 °C Recommended DC Operating Conditions (Ta = 0 to +70°C) Parameter Symbol Min Typ Max Unit Notes Supply voltage VCC 3.0 3.3 3.6 V 1, 2 Input high voltage VIH 2.0 — VCC + 0.3 V 1 Input low voltage VIL –0.3 — 0.8 V 1 Notes: 1. All voltage referred to VSS 2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. 7 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5164160A Series, HM5165160A Series DC Characteristics (Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) (HM5164160A Series) HM5164160A -6 Parameter -7 Symbol Min Max Min Max Unit Test conditions I CC1 — 120 — 100 mA t RC = min I CC2 — 2 — 2 mA TTL interface RAS, UCAS, LCAS = VIH Dout = High-Z — 1 — 1 mA CMOS interface RAS, UCAS, LCAS ≥ VCC – 0.2 V Dout = High-Z I CC2 — TBD — TBD µA CMOS interface RAS, UCAS, LCAS ≥ VCC – 0.2 V Dout = High-Z I CC3 — 120 — 100 mA t RC = min Standby current* I CC5 — 5 — 5 mA RAS = VIH UCAS, LCAS = VIL Dout = enable CAS-before-RAS refresh current I CC6 — 140 — 120 mA t RC = min Fast page mode current*1, * 3 I CC7 — 100 — 90 mA t PC = min Battery backup current* (Standby with CBR refresh) (L-version) I CC10 — TBD — TBD µA CMOS interface Dout = High-Z CBR refresh: tRC = 31.3 µs t RAS ≤ 0.3 µs Self refresh mode current (L-version) I CC11 — TBD — TBD µA CMOS interface RAS, UCAS, LCAS ≤ 0.2 V Dout = High-Z Input leakage current I LI –10 10 –10 10 µA 0 V ≤ Vin ≤ VCC + 0.3 V Output leakage current I LO –10 10 –10 10 µA 0 V ≤ Vout ≤ VCC Dout = disable Output high voltage VOH 2.4 VCC 2.4 VCC V High Iout = –2 mA Output low voltage VOL 0 0.4 0 0.4 V Low Iout = 2 mA 1, Operating current* * 2 Standby current Standby current (L-version) RAS-only refresh current*2 1 4 Notes: 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less within one page mode cycle tPC. 4. VIH ≥ VCC – 0.2 V, 0 V ≤ VIL ≤ 0.2 V. 8 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5164160A Series, HM5165160A Series DC Characteristics (Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) (HM5165160A Series) HM5165160A -6 Parameter -7 Symbol Min Max Min Max Unit Test conditions I CC1 — 175 — 150 mA t RC = min I CC2 — 2 — 2 mA TTL interface RAS, UCAS, LCAS = VIH Dout = High-Z — 1 — 1 mA CMOS interface RAS, UCAS, LCAS ≥ VCC – 0.2 V Dout = High-Z I CC2 — 300 — 300 µA CMOS interface RAS, UCAS, LCAS ≥ VCC – 0.2 V Dout = High-Z I CC3 — 175 — 150 mA t RC = min Standby current* I CC5 — 5 — 5 mA RAS = VIH UCAS, LCAS = VIL Dout = enable CAS-before-RAS refresh current I CC6 — 140 — 120 mA t RC = min Fast page mode current*1, * 3 I CC7 — 120 — 110 mA t PC = min Battery backup current* (Standby with CBR refresh) (L-version) I CC10 — 650 — 650 µA CMOS interface Dout = High-Z CBR refresh: tRC = 31.3 µs t RAS ≤ 0.3 µs Self refresh mode current (L-version) I CC11 — 500 — 500 µA CMOS interface RAS, UCAS, LCAS ≤ 0.2 V Dout = High-Z Input leakage current I LI –10 10 –10 10 µA 0 V ≤ Vin ≤ VCC + 0.3 V Output leakage current I LO –10 10 –10 10 µA 0 V ≤ Vout ≤ VCC Dout = disable Output high voltage VOH 2.4 VCC 2.4 VCC V High Iout = –2 mA Output low voltage VOL 0 0.4 0 0.4 V Low Iout = 2 mA 1, Operating current* * 2 Standby current Standby current (L-version) RAS-only refresh current*2 1 4 Notes: 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less within one page mode cycle tPC. 4. VIH ≥ VCC – 0.2 V, 0 V ≤ VIL ≤ 0.2 V. 9 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5164160A Series, HM5165160A Series Capacitance (Ta = 25°C, VCC = 3.3 V ± 0.3 V) Parameter Symbol Typ Max Unit Notes Input capacitance (Address) CI1 — 5 pF 1 Input capacitance (Clocks) CI2 — 7 pF 1 Output capacitance (Data-in, Data-out) CI/O — 7 pF 1, 2 Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. RAS, UCAS and LCAS = VIH to disable Dout. AC Characteristics (Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) *1, *2, *18, *19 Test Conditions • • • • Input rise and fall time: 5 ns Input timing reference levels: 0.8 V, 2.0 V Output timing reference levels: 0.8 V, 2.0 V Output load: 1 TTL gate + C L (100 pF) (Including scope and jig) 10 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5164160A Series, HM5165160A Series Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters) HM5164160A/HM5165160A -6 -7 Parameter Symbol Min Max Min Max Unit Notes Random read or write cycle time t RC 110 — 130 — ns RAS precharge time t RP 40 — 50 — ns CAS precharge time t CP 10 — 10 — ns RAS pulse width t RAS 60 10000 70 10000 ns CAS pulse width t CAS 15 10000 18 10000 ns Row address setup time t ASR 0 — 0 — ns Row address hold time t RAH 10 — 10 — ns Column address setup time t ASC 0 — 0 — ns 21 Column address hold time t CAH 10 — 15 — ns 21 RAS to CAS delay time t RCD 20 45 20 52 ns 3 RAS to column address delay time t RAD 15 30 15 35 ns 4 RAS hold time t RSH 15 — 18 — ns CAS hold time t CSH 60 — 70 — ns CAS to RAS precharge time t CRP 5 — 5 — ns 22 OE to Din delay time t OED 15 — 18 — ns 5 OE delay time from Din t DZO 0 — 0 — ns 6 CAS delay time from Din t DZC 0 — 0 — ns 6 Transition time (rise and fall) tT 3 50 3 50 ns 7 11 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5164160A Series, HM5165160A Series Read Cycle HM5164160A/HM5165160A -6 -7 Parameter Symbol Min Max Min Max Unit Notes Access time from RAS t RAC — 60 — 70 ns 8, 9 Access time from CAS t CAC — 15 — 18 ns 9, 10, 17 Access time from address t AA — 30 — 35 ns 9, 11, 17 Access time from OE t OEA — 15 — 18 ns 9, 25 Read command setup time t RCS 0 — 0 — ns 21 Read command hold time to CAS t RCH 0 — 0 – ns 12, 22 Read command hold time to RAS t RRH 5 — 5 — ns 12 Column address to RAS lead time t RAL 30 — 35 — ns Column address to CAS lead time t CAL 30 — 35 — ns CAS to output in low-Z t CLZ 0 — 0 — ns Output data hold time t OH 3 — 3 — ns Output data hold time from OE t OHO 3 — 3 — ns Output buffer turn-off time t OFF — 15 — 15 ns 13 Output buffer turn-off to OE t OEZ — 15 — 15 ns 13 CAS to Din delay time t CDD 15 — 18 — ns 5 Write Cycle HM5164160A/HM5165160A -6 -7 Parameter Symbol Min Max Min Max Unit Notes Write command setup time t WCS 0 — 0 — ns 14, 21 Write command hold time t WCH 10 — 15 — ns 21 Write command pulse width t WP 10 — 10 — ns Write command to RAS lead time t RWL 15 — 18 — ns Write command to CAS lead time t CWL 15 — 18 — ns 23 Data-in setup time t DS 0 — 0 — ns 15, 23 Data-in hold time t DH 10 — 15 — ns 15, 23 12 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5164160A Series, HM5165160A Series Read-Modify-Write Cycle HM5164160A/HM5165160A -6 -7 Parameter Symbol Min Max Min Max Unit Notes Read-modify-write cycle time t RWC 155 — 181 — ns RAS to WE delay time t RWD 85 — 98 — ns 14 CAS to WE delay time t CWD 40 — 46 — ns 14 Column address to WE delay time t AWD 55 — 63 — ns 14 OE hold time from WE t OEH 15 — 18 — ns Refresh Cycle HM5164160A/HM5165160A -6 Parameter Symbol -7 Min Max Min Max Unit Notes CAS setup time (CBR refresh cycle) t CSR 5 — 5 — ns 21 CAS hold time (CBR refresh cycle) t CHR 10 — 10 — ns 22 WE setup time (CBR refresh cycle) t WRP 0 — 0 — ns WE hold time (CBR refresh cycle) t WRH 10 — 10 — ns RAS precharge to CAS hold time t RPC 0 — 0 — ns 21 Notes Fast Page Mode Cycle HM5164160A/HM5165160A -6 -7 Parameter Symbol Min Max Min Max Unit Fast page mode cycle time t PC 40 — 45 — ns Fast page mode RAS pulse width t RASP — 100000 — 100000 ns 16 Access time from CAS precharge t CPA — 35 — 40 ns 9, 17, 22 35 — 40 — ns RAS hold time from CAS precharge t CPRH 13 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5164160A Series, HM5165160A Series Fast Page Mode Read-Modify-Write Cycle HM5164160A/HM5165160A -6 -7 Parameter Symbol Min Max Min Max Unit Fast page mode read-modify-write cycle time t PRWC 85 — 96 — ns 60 — 68 — ns WE delay time from CAS precharge t CPW Notes 14, 22 Refresh (HM5164160A Series) Parameter Symbol Max Unit Note Refresh period t REF 64 ms 8192 cycles Refresh period (L-version) t REF TBD ms 8192 cycles Parameter Symbol Max Unit Note Refresh period t REF 64 ms 4096 cycles Refresh period (L-version) t REF 128 ms 4096 cycles Refresh (HM5165160A Series) 14 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5164160A Series, HM5165160A Series Self Refresh Mode (L-version) HM5165160AL -6 -7 Parameter Symbol Min Max Min Max Unit Notes RAS pulse width (Self refresh) t RASS 100 — 100 — µs 26 RAS precharge time (Self refresh) t RPS 110 — 130 — ns CAS hold time (Self refresh) t CHS –50 — –50 — ns 23 Notes: 1. AC measurements assume t T = 5 ns. 2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh). 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if t RCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 5. Either t OED or tCDD must be satisfied. 6. Either t DZO or tDZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 8. Assumes that t RCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. 10. Assumes that t RCD ≥ tRCD (max) and tRCD + tCAC (max) ≥ tRAD + tAA (max). 11. Assumes that t RAD ≥ tRAD (max) and tRCD + tCAC (max) ≤ tRAD + tAA (max). 12. Either t RCH or tRRH must be satisfied for a read cycles. 13. t OFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t WCS , t RWD, t CWD, t AWD and t CPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS ≥ tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD ≥ tRWD (min), tCWD ≥ tCWD (min), and tAWD ≥ tAWD (min), or tCWD ≥ tCWD (min), tAWD ≥ tAWD (min) and tCPW ≥ t CPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. These parameters are referred to UCAS and LCAS leading edge in early write cycles and to WE leading edge in delayed write or read-modify-write cycles. 16. t RASP defines RAS pulse width in fast page mode cycles. 17. Access time is determined by the longest among t AA , t CAC and t CPA. 18. When both UCAS and LCAS go low at the same time, all 16-bit data are written into the device. UCAS and LCAS cannot be staggered within the same write/read cycles. 19. All the V CC and VSS pins shall be supplied with the same voltages. 20. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 21. t ASC, tCAH , t RCS , t WCS , t WCH, t CSR and t RPC are determined by the earlier falling edge of UCAS or LCAS. 22. t CRP , t CHR, t RCH, t CPA and tCPW are determined by the later rising edge of UCAS or LCAS. 23. t CWL, t DH, t DS and t CHS should be satisfied by both UCAS and LCAS. 15 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5164160A Series, HM5165160A Series 24. t CP is determined by the time that both UCAS and LCAS are high. 25. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally it causes large V CC/V SS line noise, which causes to degrade V IH min/VIL max level. 26. Please do not use tRASS timing, 10 µs ≤ tRASS ≤ 100 µs. During this period, the device is in transition state from normal operation mode to self refresh mode. If t RASS ≥ 100 µs, then RAS precharge time should use tRPS instead of tRP. 27. CBR burst refresh or 4096 cycles of distributed CBR refresh with 15.6 µs interval should be executed within 64 ms immediately after exiting from and before entering into the self refresh mode. 28. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self refresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again. 29. XXX: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL. Notes concerning 2CAS control Please do not separate the UCAS/LCAS operation timing intentionally. However skew between UCAS/LCAS are allowed under the following conditions. 1. Each of the UCAS/LCAS should satisfy the timing specifications individually. 2. Different operation mode for upper/lower byte is not allowed; such as following. RAS Delayed write UCAS Early write LCAS WE 3. Closely separated upper/lower byte control is not allowed. However when the condition (tCP ≤ tUL) is satisfied, fast page mode can be performed. 16 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5164160A Series, HM5165160A Series RAS UCAS LCAS t UL 4. Byte control operation by remaining UCAS or LCAS high is guaranteed. 17 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5164160A Series, HM5165160A Series Timing Waveforms*29 Read Cycle tRC tRAS tRP RAS tCSH tCRP tRCD tRSH tCAS tT UCAS LCAS tRAD tASR Address tRAH tRAL tCAL tASC Row tCAH Column tRRH tRCS tRCH WE tDZC tCDD High-Z Din tDZO tOEA tOED OE tOEZ tOHO tCAC tAA tRAC tCLZ Dout 18 Powered by ICminer.com Electronic-Library Service CopyRight 2003 tOFF tOH Dout HM5164160A Series, HM5165160A Series Early Write Cycle tRC tRAS tRP RAS tCSH tCRP tRCD tRSH tCAS tT UCAS LCAS tASR Address tRAH Row tASC tCAH Column tWCS tWCH WE tDS Din Dout tDH Din High-Z* * t WCS t WCS (min) 19 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5164160A Series, HM5165160A Series Delayed Write Cycle*20 tRC tRAS tRP RAS tCSH tCRP tRCD tRSH tCAS tT UCAS LCAS tASR Address tRAH tASC Row tCAH Column tCWL tRWL tWP tRCS WE tDS tDZC High-Z Din Din tOED tDZO tDH tOEH OE tOEZ tCLZ High-Z Dout Invalid Dout 20 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5164160A Series, HM5165160A Series Read-Modify-Write Cycle*20 tRWC tRAS tRP RAS tT tRCD UCAS LCAS tCRP tRAD tASR Address tCAS tASC tRAH Row tCAH Column tCWL tCWD tRCS tRWL tWP tAWD tRWD WE tDZC tDS High-Z Din Din tDH tOED tDZO tOEH tOEA OE tCAC tAA tOEZ tRAC tOHO Dout Dout High-Z tCLZ 21 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5164160A Series, HM5165160A Series RAS-Only Refresh Cycle t RC t RAS t RP RAS tT t RPC t CRP t CRP UCAS LCAS t ASR t RAH Row Address t OFF Dout 22 Powered by ICminer.com Electronic-Library Service CopyRight 2003 High-Z HM5164160A Series, HM5165160A Series CAS-Before-RAS Refresh Cycle t RC t RAS t RP t RP RAS t RPC t CSR t CHR t RPC t CRP tT UCAS LCAS t CP t WRP t WRH t CP WE Address t OFF Dout High-Z 23 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5164160A Series, HM5165160A Series Hidden Refresh Cycle t RC t RC t RP t RAS t RAS t RC t RP t RAS t RP RAS tT t RSH t CHR t CRP t RCD UCAS LCAS t RAD t ASR t RAH Address t RAL t ASC Row t CAH Column t RRH t RCH t RCS WE t DZC t CDD High-Z Din t DZO t OED t OEA OE t CAC t OEZ t OHO t AA t RAC t OFF t OH t CLZ Dout 24 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Dout HM5164160A Series, HM5165160A Series Fast Page Mode Read Cycle t RASP t CPRH t RP RAS tT t CSH t RCD t PC t CAS t CP t RSH t CAS t CP t CRP t CAS UCAS LCAS t RAL t RAD t ASR t RAH Address Row t CAL t ASC t CAH t CAL t ASC t CAH t CAL t ASC t CAH Column 1 Column 2 Column N t RCS t RCS t RCH t RCS t RRH t RCH t RCH WE t DZC Din t DZO t DZC t DZC t CDD t CDD High-Z High-Z t OED t DZO t OED t CDD High-Z t DZO t OED OE t RAC t AA t OH t OEA t OHO t OH t OEA t OFF t CAC t OEZ t CLZ t CAC t CLZ Dout t CPA t AA Dout 1 t CPA t AA t OHO t OFF t OEZ Dout 2 t OH t OHO t OEA t CAC t CLZ t OFF t OEZ Dout N 25 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5164160A Series, HM5165160A Series Fast Page Mode Early Write Cycle t RP t RASP RAS tT t CSH t RCD t CAS t PC t CP t CAS t CP t RSH t CAS t CRP UCAS LCAS t ASR t RAH Address Row t ASC t CAH t ASC t CAH t ASC t CAH Column 1 Column 2 Column N t WCS t WCH t WCS t WCH t WCS t WCH WE t DS Din t DH Din 1 Dout t DS t DH Din 2 t DS t DH Din N High-Z* * t WCS 26 Powered by ICminer.com Electronic-Library Service CopyRight 2003 t WCS (min) HM5164160A Series, HM5165160A Series Fast Page Mode Delayed Write Cycle*20 t RASP t RP RAS tT t CP t CSH t RCD t CRP t CP t PC t CAS t RSH t CAS t CAS UCAS LCAS t RAD t ASR t ASC t RAH Address t ASC t CAH Row t ASC t CAH Column 1 t CAH Column 2 t CWL Column N t CWL t CWL t RWL t RCS t RCS t RCS WE t WP t WP t WP t DZC t DS t DZC t DS t DZC t DS t DH t DH Din 1 Din t DZO t DH Din 2 t DZO t OED Din N t DZO t OED t OED t OEH t OEH t OEH OE t CLZ t CLZ t OEZ t CLZ t OEZ t OEZ High-Z Dout Invalid Dout Invalid Dout Invalid Dout 27 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5164160A Series, HM5165160A Series Fast Page Mode Read-Modify-Write Cycle*20 t RASP t RP RAS tT t PRWC t CP t RCD t RSH t CP t CAS t CAS t CRP t CAS UCAS LCAS t ASR t RAD t ASC t RAH Address t ASC t CAH t CAH Row Column 1 t ASC t CAH Column 2 t RWD t CWL t AWD t CPW t CWL t AWD t RCS t CWD Column N t CPW t AWD t RCS t CWD t CWL t RWL t CWD WE t RCS t WP t WP t DZC t DS t WP t DZC t DS t DZC t DS t DH t DH Din 1 Din t DZO t OED t DH Din 2 t OED t DZO t OED t DZO t OEH t OEH t OEH Din N OE t OHO t OEA t CAC t OHO t OEA t CAC t AA t AA t CPA t RAC t OEZ t CLZ t OHO t OEA t CAC t AA t CPA t OEZ t CLZ t OEZ t CLZ High-Z Dout Dout 1 28 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Dout 2 Dout N HM5164160A Series, HM5165160A Series Self Refresh Cycle (L-version)* 26, 27, 28 t RASS t RP t RPS RAS tT t RPC t CP t CRP t CSR t CHS UCAS LCAS t WRP t WRH WE t OFF Dout High-Z 29 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5164160A Series, HM5165160A Series Package Dimensions HM5164160AJ Series HM5165160AJ Series (CP-50DA) Preliminary Unit: mm 26 10.16 ± 0.13 25 3.50 ± 0.26 0.47 1.09 Max 0.32 ± 0.08 0.30 ± 0.04 0.80 0.10 Dimension including the plating thickness Base material dimension 30 Powered by ICminer.com Electronic-Library Service CopyRight 2003 2.55 ± 0.46 1 0.90 ± 0.26 50 11.18 ± 0.13 20.95 21.38 Max 9.40 ± 0.25 Hitachi Code JEDEC EIAJ Weight (reference value) CP-50DA Conforms — 1.2 g HM5164160A Series, HM5165160A Series HM5164160ATT Series HM5165160ATT/ALTT Series (TTP-50DB) Unit: mm 20.95 21.35 Max 26 10.16 50 1 0.80 0.30 ± 0.10 0.28 ± 0.08 25 0.13 M 0.80 11.76 ± 0.20 1.15 Max Dimension including the plating thickness Base material dimension 0.50 ± 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) 0.68 0.13 ± 0.05 0.10 0.145 ± 0.05 0.125 ± 0.04 1.20 Max 0° – 5° TTP-50DB — — 0.51 g When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi’s permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user’s unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 31 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5164160A Series, HM5165160A Series 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. 32 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5164160A Series, HM5165160A Series Hitachi, Ltd. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207 Hitachi Europe GmbH Continental Europe Dornacher Straße 3 D-85622 Feldkirchen München Tel: 089-9 91 80-0 Fax: 089-9 29 30-00 Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 01628-585000 Fax: 01628-585160 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071 Copyright © Hitachi, Ltd., 1997. All rights reserved. Printed in Japan. Revision Record Rev. Date Contents of Modification Drawn by Approved by 0.0 Jun. 3, 1996 Initial issue S. Ikenaga J. Kitano 0.1 Jan. 22, 1997 Power dissipation J. Kitano J. Kitano TBD/540/468 mW to TBD/432/360 mW (max) (HM5164160A Series) TBD/684/612 mW to TBD/630/540 mW (max) (HM5165160A Series) DC Characteristics (HM5164160A Series) I CC1(max): TBD/140/120 mA to TBD/120/100 mA I CC3(max): TBD/140/120 mA to TBD/120/100 mA I CC6(max): TBD/150/130 mA to TBD/140/120 mA I CC7(max): TBD/130/120 mA to TBD/100/90 mA I LO test conditions: 0 V ≤ Vout ≤ VCC + 0.3 to 0 V ≤ Vout ≤ VCC DC Characteristics (HM5165160A Series) I CC1(max): TBD/190/170 mA to TBD/175/150 mA I CC3(max): TBD/190/170 mA to TBD/175/150 mA I CC6(max): TBD/150/130 mA to TBD/140/120 mA I CC7(max): TBD/130/120 mA to TBD/120/110 mA I LO test conditions: 0 V ≤ Vout ≤ VCC + 0.3 to 0 V ≤ Vout ≤ VCC 1.0 Aug. 22, 1997 Deletion of preliminary M. Tsunozaki M. Saeki Correct errors (HM5164160A Series) t REF (L-version): 128 ms to TBD (for suspension of L-version), 4096 cycles to 8192 cycles 33 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5164160A Series, HM5165160A Series 2.0 Nov. 25, 1997 Deletion of HM5164/65160A/AL-5 Series Deletion of HM5164160AL Series Deletion of HM5165160ALTT-7 Power dissipation Standby mode (L-version): TBD to 1.08 mW DC Characteristics (HM5165160A Series) I CC2 (L-version): TBD/TBD/TBD to 300/300 µA I CC10 (L-version): TBD/TBD/TBD to 650/650 µA I CC11 (L-version): TBD/TBD/TBD to 500/500 µA 34 Powered by ICminer.com Electronic-Library Service CopyRight 2003