Revised February 2005
74VHC4066
Quad Analog Switch
General Description
Features
These devices are digitally controlled analog switches utilizing advanced silicon-gate CMOS technology. These
switches have low “on” resistance and low “off” leakages.
They are bidirectional switches, thus any analog input may
be used as an output and visa-versa. Also the 4066
switches contain linearization circuitry which lowers the
“on” resistance and increases switch linearity. The 4066
devices allow control of up to 12V (peak) analog signals
with digital control signals of the same range. Each switch
has its own control input which disables each switch when
low. All analog inputs and outputs and digital inputs are
protected from electrostatic damage by diodes to VCC and
ground.
■ Typical switch enable time: 15 ns
■ Wide analog input voltage range: 0–12V
■ Low “on” resistance: 30 typ. ('4066)
■ Low quiescent current: 80 PA maximum (74VHC)
■ Matched switch characteristics
■ Individual switch controls
■ Pin and function compatible with the 74HC4066
Ordering Code:
Order Number
Package
Package Description
Number
74VHC4066M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74VHC4066MX_NL
(Note 1)
M14A
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74VHC4066MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC4066MTCX_NL
(Note 1)
MTC14
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74VHC4066N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Note 1: “_NL” indicates Pb-Free package (per JEDEC S-STD-020B). Device available in Tape and Reel only.
Connection Diagram
Schematic Diagram
Truth Table
Top View
© 2005 Fairchild Semiconductor Corporation
DS011677
Input
Switch
CTL
I/O–O/I
L
“OFF”
H
“ON”
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74VHC4066 Quad Analog Switch
April 1994
74VHC4066
Absolute Maximum Ratings(Note 2)
Recommended Operating
Conditions
(Note 3)
Supply Voltage (VCC)
DC Control Input Voltage (VIN)
DC Switch I/O Voltage (VIO)
Clamp Diode Current (IIK, IOK)
DC Output Current, per pin (IOUT)
0.5 to 15V
1.5 to VCC 1.5V
VEE 0.5 to VCC 0.5V
r20 mA
r25 mA
DC VCC or GND Current, per pin
(ICC)
Power Dissipation (PD) (Note 4)
Symbol
260qC
VIH
VIL
RON
Parameter
qC
VCC
2.0V
1000
ns
VCC
4.5V
500
ns
VCC
9.0V
400
ns
(Note 5)
VCC
TA 25qC
Typ
TA 40 to 85qC
Guaranteed Limits
Units
2.0V
1.5
1.5
V
4.5V
3.15
3.15
V
9.0V
6.3
5.3
V
12.0V
8.4
8.4
V
Maximum LOW Level
2.0V
0.5
0.5
V
Input Voltage
4.5V
1.35
1.35
V
9.0V
2.7
2.7
V
12.0V
3.6
3.6
V
4.5V
100
170
200
:
9.0V
50
85
105
:
12.0V
30
70
85
:
2.0V
120
180
215
:
4.5V
50
80
100
:
9.0V
35
60
75
:
(Figure 1)
12.0V
20
40
60
:
Maximum “ON” Resistance
VCTL
4.5V
10
15
20
:
Matching
VIS
9.0V
5
10
15
:
12.0V
5
10
15
:
r0.05
r0.5
PA
Maximum “ON” Resistance
VCTL
See (Note 6)
VIS
Maximum Control
VIH, IS
2.0 mA
V CC to GND
VIN
VIH, IS
2.0 mA
V CC or GND
VIH
V CC to GND
VCC or GND
Input Current
VCC
2 6V
Maximum Switch “OFF”
VOS
V CC or GND
Leakage Current
VIS
Maximum Switch “ON”
Leakage Current
VIS
VCTL
VOS
ICC
85
Input Voltage
VCTL
IIZ
40
(tr, tf)
Minimum HIGH Level
VIS
IIZ
V
Note 4: Power Dissipation temperature derating — plastic “N” package: 12 mW/qC from 65qC to 85qC.
Conditions
VCTL
IIN
VCC
Note 3: Unless otherwise specified all voltages are referenced to ground.
(Figure 1)
RON
0
Note 2: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Lead Temperature (TL)
DC Electrical Characteristics
V
DC Input or Output Voltage
Input Rise or Fall Times
500 mW
(Soldering 10 seconds)
Units
12
Operating Temperature Range (TA)
600 mW
S.O. Package only
Max
2
(VIN, VOUT)
r50 mA
65qC to 150qC
Storage Temperature Range (TSTG)
Min
Supply Voltage (VCC)
Maximum Quiescent
VIN
Supply Current
IOUT
GND or VCC
VIL (Figure 2)
V CC to GND
VIH
OPEN (Figure 3)
VCC or GND
6.0V
10
r60
r600
nA
9.0V
15
r80
r800
nA
12.0V
20
r100
r1000
nA
6.0V
10
r40
r150
nA
9.0V
15
r50
r200
nA
12.0V
20
r60
r300
nA
1.0
10
PA
9.0V
2.0
20
PA
12.0V
4.0
40
PA
6.0V
0 PA
Note 5: For a power supply of 5V r 10% the worst case on resistance (RON) occurs for VHC at 4.5V. Thus the 4.5V values should be used when designing
with this supply. Worst case VIH and VIL occur at VCC 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current occurs
for CMOS at the higher voltage and so the 5.5V values should be used.
Note 6: At supply voltages (VCC – GND) approaching 2V the analog switch on resistance becomes extremely non-linear. Therefore it is recommended that
these devices be used to transmit digital only when using these supply voltages.
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2
VCC
2.0V6.0V VEE
Symbol
tPHL, tPLH
tPZL, tPZH
0V12V, CL 50 pF (unless otherwise specified)
Parameter
VCC
Conditions
TA 40 to 85qC
Units
Guaranteed Limits
Maximum Propagation
3.3V
25
30
20
Delay Switch In to Out
4.5V
5
10
13
ns
9.0V
4
8
10
ns
ns
Maximum Switch Turn
1 k:
RL
“ON” Delay
tPHZ, tPLZ
TA 25qC
Typ
Maximum Switch Turn
1 k:
RL
“OFF” Delay
ns
12.0V
3
7
11
3.3V
30
58
73
ns
4.5V
12
20
25
ns
ns
9.0V
6
12
15
12.0V
5
10
13
ns
3.3V
60
100
125
ns
4.5V
25
36
45
ns
9.0V
20
32
40
ns
12.0V
15
30
38
Minimum Frequency
RL
600:
4.5V
40
MHz
Response (Figure 7)
VIS
2 VPP at (VCC/2)
9.0V
100
MHz
4.5V
52
dB
9.0V
50
dB
4.5V
100
mV
9.0V
250
mV
4.5V
42
dB
9.0V
44
dB
%
3 dB
20 log (VO/VI)
(Note 7)(Note 8)
600:, F
Crosstalk Between
RL
any Two Switches
(Note 8)(Note 9)
1 MHz
(Figure 8)
Peak Control to Switch
RL
600:, F
Feedthrough Noise
CL
50 pF
600:, F
1 MHz
(Figure 9)
Switch OFF Signal
RL
Feedthrough
V(CT) VIL
1 MHz
Isolation
(Note 8)(Note 9)
(Figure 10)
THD
CIN
Total Harmonic
10 k:, CL
RL
50 pF,
Distortion
F
(Figure 11)
VIS
1 kHz
4 VPP
4.5V
.013
VIS
8 VPP
9.0V
.008
Maximum Control
5
%
10
10
pF
Input Capacitance
CIN
Maximum Switch
20
pF
0.5
pF
15
pF
Input Capacitance
CIN
Maximum Feedthrough
VCTL
GND
Capacitance
CPD
Power Dissipation
Capacitance
Note 7: Adjust 0 dBm for F
1 kHz (Null RL/RON Attenuation).
Note 8: VIS is centered at VCC/2.
Note 9: Adjust input for 0 dBm.
3
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74VHC4066
AC Electrical Characteristics
74VHC4066
AC Test Circuits and Switching Time Waveforms
FIGURE 1. “ON” Resistance
FIGURE 2. “OFF” Channel Leakage Current
FIGURE 3. “ON” Channel Leakage Current
FIGURE 4. t PHL, tPLH Propagation Delay Time Signal Input to Signal Output
FIGURE 5. tPZL, tPLZ Propagation Delay Time Control to Signal Output
FIGURE 6. tPZH, tPHZ Propagation Delay Time Control to Signal Output
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4
74VHC4066
AC Test Circuits and Switching Time Waveforms
(Continued)
FIGURE 7. Frequency Response
Crosstalk and Distortion Test Circuits
FIGURE 8. Crosstalk: Control Input to Signal Output
FIGURE 9. Crosstalk Between Any Two Switches
5
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74VHC4066
Crosstalk and Distortion Test Circuits
(Continued)
FIGURE 10. Switch OFF Signal Feedthrough Isolation
FIGURE 11. Sinewave Distortion
Typical Performance Characteristics
Typical “ON” Resistance
Typical Crosstalk Between
Any Two Switches
Typical Frequency Response
Special Considerations
In certain applications the external load-resistor current may include both VCC and signal line components. To avoid drawing VCC current when switch current flows into the analog switch input pins, the voltage drop across the switch must not
exceed 0.6V (calculated from the ON Resistance).
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6
74VHC4066
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M14A
7
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74VHC4066
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
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8
74VHC4066 Quad Analog Switch
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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9
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