MM54HC4016/MM74HC4016 Quad Analog Switch General Description Features These devices are digitally controlled analog switches implemented in advanced silicon-gate CMOS technology. These switches have low ‘‘on’’ resistance and low ‘‘off’’ leakages. They are bidirectional switches, thus any analog input may be used as an output and vice-versa. The ‘4016 devices allow control of up to 12V (peak) analog signals with digital control signals of the same range. Each switch has its own control input which disables each switch when low. All analog inputs and outputs and digital inputs are protected from electrostatic damage by diodes to VCC and ground. Y Connection Diagram Truth Table Y Y Y Y Y Typical switch enable time: 15 ns Wide analog input voltage range: 0 – 12V Low ‘‘on’’ resistance: 50X typ. Low quiescent current: 80 mA maximum (74HC) Matched switch characteristics Individual switch controls Dual-In-Line Package Input Switch CTL I/O-O/I L H ‘‘OFF’’ ‘‘ON’’ TL/F/5350 – 1 Top View Order Number MM54HC4016 or MM74HC4016 Schematic Diagram TL/F/5350 – 2 C1995 National Semiconductor Corporation TL/F/5350 RRD-B30M105/Printed in U. S. A. MM54HC4016/MM74HC4016 Quad Analog Switch August 1989 Absolute Maximum Ratings (Notes 1 & 2) Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VCC) Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT) b 0.5 to a 15V b 1.5 to VCC a 1.5V DC Control Input Voltage (VIN) b 0.5 to VCC a 0.5V DC Switch I/O Voltage (VIO) g 20 mA Clamp Diode Current (IIK, IOK) g 25 mA DC Output Current, per pin (IOUT) g 50 mA DC VCC or GND Current, per pin (ICC) b 65§ C to a 150§ C Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) 600 mW S.O. Package only 500 mW Lead Temp. (TL) (Soldering 10 seconds) 260§ C Operating Temp. Range (TA) MM74HC MM54HC Min 2 Max 12 0 VCC Units V V b 40 b 55 a 85 a 125 §C §C 1000 500 400 ns ns ns Input Rise or Fall Times VCC e 2.0V (tr, tf) VCC e 4.5V VCC e 6.0V DC Electrical Characteristics (Note 4) Symbol Parameter Conditions VCC TA e 25§ C Typ 74HC 54HC TA eb40 to 85§ C TA eb55 to 125§ C Units Guaranteed Limits VIH Minimum High Level Input Voltage 2.0V 4.5V 9.0V 12.0V 1.5 3.15 6.3 8.4 1.5 3.15 6.3 8.4 1.5 3.15 6.3 8.4 V V V V VIL Maximum Low Level Input Voltage** 2.0V 4.5V 9.0V 12.0V 0.5 1.35 2.7 3.6 0.5 1.35 2.7 3.6 0.5 1.35 2.7 3.6 V V V V RON Maximum ‘ON’ Resistance VCTL e VIH, IS e 2.0 mA (See Note 5) VIS e VCC to GND (Figure 1) 4.5V 100 9.0V 50 12.0V 30 170 85 70 200 105 85 220 120 100 X X X VCTL e VIH, IS e 2.0 mA VIS e VCC or GND (Figure 1) 2.0V 100 4.5V 40 9.0V 35 12.0V 20 180 80 60 40 215 100 75 60 240 120 80 70 X X X X 15 10 10 20 15 15 20 15 15 X X X RON Maximum ‘ON’ Resistance VCTL e VIH Matching VIS e VCC to GND 4.5V 9.0V 12.V IIN Maximum Control Input Current VIN e VCC or GND 6.0V g 0.1 g 1.0 g 1.0 mA IIZ Maximum Switch ‘OFF’ Leakage Current VOS e VCC or GND VIS e GND or VCC VCTL e VIL (Figure 2) 6.0V 9.0V 12.0V g 60 g 80 g 100 g 600 g 800 g 1000 g 600 g 800 g 1000 nA nA nA IIZ Maximum Switch ‘ON’ Leakage Current VIS e VCC to GND 6.0V VCTL e VIH, VOH e OPEN 9.0V (Figure 3) 12.0V g 40 g 50 g 60 g 150 g 200 g 300 g 150 g 200 g 300 nA nA nA ICC Maximum Quiescent Supply Current VIN e VCC or GND IOUT e 0 mA 2.0 4.0 8.0 20 40 80 40 80 160 mA mA mA 6.0V 9.0V 12.0V 10 5 5 Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: b 12 mW/§ C from 65§ C to 85§ C; ceramic ‘‘J’’ package: b 12 mW/§ C from 100§ C to 125§ C. Note 4: For a power supply of 5V g 10% the worst case on resistances (RON) occurs for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC e 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current occur for CMOS at the higher voltage and so these values should be used. Note 5: At supply voltages (VCC –GND) approaching 2V the analog switch on resistance becomes extremely non-linear. Therefore it is recommended that these devices be used to transmit digital only when using these supply voltages. **VIL limits are currently tested at 20% of VCC. The above VIL specification (30% of VCC) will be implemented no later than Q1, CY’89. 2 AC Electrical Characteristics Symbol Parameter VCC e 2.0V – 12.0V, CL e 50 pF (unless otherwise specified), (Notes 6 and 7) Conditions VCC TA e 25§ C Typ tPHL, tPLH Maximum Propagation Delay Switch In to Out 74HC 54HC TA eb40 to 85§ C TA eb55 to 125§ C Units Guaranteed Limits 2.0V 4.5V 9.0V 12.0V 25 5 4 3 50 10 8 7 62 13 12 11 75 15 14 13 ns ns ns ns tPZL, tPZH Maximum Switch Turn ‘‘ON’’ Delay RL e 1 kX 2.0V 4.5V 9.0V 12.0V 32 8 6 5 100 20 12 10 125 25 15 13 150 30 18 15 ns ns ns ns tPHZ, tPLZ Maximum Switch Turn ‘‘OFF’’ Delay RL e 1 kX 2.0V 4.5V 9.0V 12.0V 45 15 10 8 168 36 32 30 210 45 40 38 252 54 48 45 ns ns ns ns Minimum Frequency RL e 600X, VIS e 2VPP Response (Figure 7) at (VCC/2) 20 log (VOS/VIS) e b3 dB (Notes 6 & 7) 4.5V 9.0V 40 100 MHz MHz Control to Switch Feedthrough Noise (Figure 8) RL e 600X, F e 1 MHz CL e 50 pF (Notes 7 & 8) 4.5V 9.0V 100 250 mV mV Crosstalk Between any Two Switches (Figure 9) RL e 600X, F e 1 MHz 4.5V 9.0V b 52 b 50 dB dB Switch OFF Signal Feedthrough Isolation (Figure 10) RL e 600X, F e 1 MHz VCTL e VIL (Notes 7 & 8) 4.5V 9.0V b 42 b 44 dB dB Sinewave Harmonic Distortion (Figure 11) RL e 10 kX, CL e 50 pF, F e 1 kHz VIS e 4VPP 4.5V 0.013 VIS e 8VPP 9.0V 0.008 % % THD CIN Maximum Control Input Capacitance 5 CIN Maximum Switch Input Capacitance 15 pF CIN Maximum Feedthrough Capacitance VCTL e GND 5 pF CPD Power Dissipation Capacitance (per switch) 15 pF Note 6: Adjust 0 dBm for F e 1 kHz (Null RL/RON Attenuation) Note 7: VIS is centered at VCC/2 Note 8: Adjust input for 0 dBm 3 10 10 10 pF AC Test Circuits and Switching Time Waveforms TL/F/5350 – 4 FIGURE 2. ‘‘OFF’’ Channel Leakage Current TL/F/5350–3 FIGURE 1. ‘‘ON’’ Resistance TL/F/5350 – 5 FIGURE 3. ‘‘ON’’ Channel Leakage Current TL/F/5350 – 7 TL/F/5350–6 FIGURE 4. tPHL, tPLH Propagation Delay Time Signal Input to Signal Output TL/F/5350 – 9 TL/F/5350–8 FIGURE 5. tPZL, tPLZ Propagation Delay Time Control to Signal Output 4 AC Test Circuits and Switching Time Waveforms (Continued) TL/F/5350 – 11 TL/F/5350–10 FIGURE 6. tPZH, tPHZ Propagation Delay Time Control to Signal Output TL/F/5350 – 20 FIGURE 7. Frequency Response TL/F/5350 – 13 TL/F/5350 – 12 FIGURE 8. Crosstalk: Control Input to Signal Output 5 AC Test Circuits and Switching Time Waveforms (Continued) TL/F/5350–14 TL/F/5350 – 15 TL/F/5350–16 FIGURE 9. Crosstalk Between Any Two Switches TL/F/5350–21 TL/F/5350 – 22 FIGURE 10. Switch OFF Signal Feedthrough Isolation FIGURE 11. Sinewave Distortion 6 Typical Performance Characteristics Typical ‘‘On’’ Resistance Typical Frequency Response TL/F/5350 – 19 TL/F/5350 – 23 Typical Crosstalk Between Any Two Switches TL/F/5350 – 24 Special Considerations In certain applications the external load-resistor current may include both VCC and signal line components. To avoid drawing VCC current when switch current flows into the analog switch input pins, the voltage drop across the switch must not exceed 0.6V (calculated from the ON resistance). 7 MM54HC4016/MM74HC4016 Quad Analog Switch Physical Dimensions inches (millimeters) Ceramic Dual in Line Pkg (J) Order Number MM54HC4016J or MM74HC4016J NS Package Number J14A Molded Dual in Line Package (N) Order Number MM74HC4016N NS Package Number N14A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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