Revised April 1999 74VHC4040 12-Stage Binary Counter General Description The VHC4040 is an advanced high-speed CMOS device fabricated with silicon gate CMOS technology. It achieves the high-speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The VHC4040 is a 12-stage counter which increments on the negative edge of the input clock and all outputs are reset to a low level by applying a logical high on the reset input. An input protection circuit insures that 0V to 7V can be applied to the inputs without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages. Features ■ High speed; fMAX = 210 MHz at VCC = 5V ■ Low power dissipation: ICC = 4 µA (max) at TA = 25°C ■ High noise immunity: VNIH =VNIL = 28% VCC (min) ■ Power down protection is provided on all inputs ■ Wide operating voltage range: VCC (opr) = 2V − 5.5V ■ Low noise: VOLP = 0.8V (max) ■ Pin and function compatible with 74HC4040 Ordering Code: Order Number 74VHC4040M 74VHC4040MTC 74VHC4040N Package Number M16A MTC16 N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names © 1999 Fairchild Semiconductor Corporation DS011641.prf Description Q0–Q11 Flip-Flop Outputs CP Negative Edged Triggered Clock MR Master Reset www.fairchildsemi.com 74VHC4040 12-Stage Binary Counter August 1993 74VHC4040 Logic Symbols IEEE/IEC Logic Diagram Timing Diagram www.fairchildsemi.com 2 Supply Voltage (VCC) −0.5V to +7.0V DC Input Voltage (VIN) −0.5V to +7.0V Recommended Operating Conditions (Note 2) 2.0V to +5.5V Supply Voltage (VCC) −0.5V to VCC + 0.5V DC Output Voltage (VOUT) 0V to +5.5V Input Voltage (VIN) Input Diode Current (IIK) −20 mA Output Voltage (VOUT) Output Diode Current (IOK) ±20 mA Operating Temperature (TOPR) DC Output Current (IOUT) ±25 mA Input Rise and Fall Time (tr, tf) DC VCC /GND Current (ICC ) ±75 mA VCC = 3.3V ± 0.3V 0 ∼ 100 ns/V −65°C to +150°C VCC = 5.0V ± 0.5V 0 ∼ 20 ns/V Storage Temperature (TSTG) Lead Temperature (TL) (Soldering, 10 seconds) 0V to VCC −40°C to +85°C Note 1: Absolute Maximum Ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside databook specifications. 260°C Note 2: Unused inputs must be held HIGH or LOW. They may not float DC Electrical Characteristics Symbol VIH Parameter HIGH Level Input Voltage VIL LOW Level Input Voltage VOH VOL VCC (V) TA = 25°C Min Typ TA = −40°C to +85°C Max Min 2.0 1.50 1.50 3.0 − 5.5 0.7 VCC 0.7 VCC 2.0 0.50 0.50 0.3 VCC 0.3 VCC 2.0 1.9 2.0 1.9 Voltage 3.0 2.9 3.0 2.9 4.5 4.4 4.5 3.0 2.58 2.48 4.5 3.94 3.80 LOW Level Output 2.0 Voltage Input Leakage Current ICC Quiescent Supply Current Units Conditions V 3.0 − 5.5 HIGH Level Output IIN Max V IOH = −50 µA 4.4 V VIN = VIH or VIL IOH = −4 mA IOH = −8 mA 0.0 0.1 3.0 0.0 0.1 0.1 4.5 0.0 0.1 0.1 IOL = 50 µA 0.1 V VIN = VIH or VIL IOL = 4 mA 3.0 0.36 0.44 4.5 0.36 0.44 0 − 5.5 ±0.1 ±1.0 µA VIN = 5.5V or GND 5.5 4.0 40.0 µA VIN = VCC or GND 3 IOL = 8 mA www.fairchildsemi.com 74VHC4040 Absolute Maximum Ratings(Note 1) 74VHC4040 AC Electrical Characteristics Symbol Parameter tPLH Propagation Delay Time tPHL to Q1 VCC (V) TA = +25°C Min 3.3 ± 0.3 5.0 ± 0.5 tPLH Propagation Delay Time tPHL between Stages from Min Max 7.5 11.9 1.0 14.0 10.0 15.4 1.0 17.5 4.8 7.3 1.0 8.5 6.3 9.3 1.0 10.5 2.4 4.4 1.0 5.0 1.6 3.1 1.0 3.5 Units ns ns 3.3 ± 0.3 Propagation Delay Time 3.3 ± 0.3 MR–Qn 5.0 ± 0.5 fMAX Max ns 5.0 ± 0.5 Qn to Qn+1 tPHL TA = −40°C to +85°C Typ 3.3 ± 0.3 Maximum Clock Frequency 5.0 ± 0.5 8.3 12.8 1.0 15.0 10.8 16.3 1.0 18.5 5.6 8.6 1.0 10.0 7.1 10.6 1.0 12.0 90 140 75 55 80 50 150 210 125 95 125 CIN Input Capacitance 4 CPD Power Dissipation Capacitance 21 ns ns MHz MHz 80 10 ns 10 Conditions CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF pF VCC = Open pF (Note 3) Note 3: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr) = CPD * VCC * fN + ICC. AC Operating Requirements Symbol Parameter VCC (V) TA = 25°C Typ TA = −40°C to +85°C Guaranteed Minimum tw(L) Minimum Pulse Width 3.3 ± 0.3 5.0 5.0 tw(H) (CP) 5.0 ± 0.5 5.0 5.0 tw(L) Minimum Pulse Width 3.3 ± 0.3 5.0 5.0 (MR) 5.0 ± 0.5 5.0 5.0 Minimum Removal Time 3.3 ± 0.3 5.0 5.0 (MR) 5.0 ± 0.5 5.0 5.0 tREC www.fairchildsemi.com 4 Units ns ns ns 74VHC4040 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Package Number M16A 5 www.fairchildsemi.com 74VHC4040 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 www.fairchildsemi.com 6 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 74VHC4040 12-Stage Binary Counter Physical Dimensions inches (millimeters) unless otherwise noted (Continued)