FAIRCHILD USB1T1103

Revised May 2005
USB1T1103
Universal Serial Bus Peripheral Transceiver
with Voltage Regulator
General Description
Features
This chip provides a USB Transceiver functionality with a
voltage regulator that is compliant to USB Specification
Rev 2.0. this integrated 5V to 3.3V regulator allows interfacing of USB Application specific devices with supply voltages ranging from 1.65V to 3.6V with the physical layer of
Universal Serial Bus. It is capable of operating at 12Mbits/s
(full speed) data rates and hence is fully compliant to USB
Specification Rev 2.0. The Vbusmon terminal allows for
monitoring the Vbus line.
■ Complies with Universal Serial Bus Specification 2.0
The USB1T1103 also provides exceptional ESD protection
with 15kV contact HBM on D, D terminals.
■ Integrated 5V to 3.3V voltage regulator for powering
VBus
■ Utilizes digital inputs and outputs to transmit and receive
USB cable data
■ Supports full speed (12Mbits/s) data rates
■ Ideal for portable electronic devices
■ MLP technology package (16 terminal) with HBCC
footprint
■ 15kV contact HBM ESD protection on bus terminals
■ Supports disable mode and is functionally equivalent to
Philips ISP1102
Applications
• PDA
• PC Peripherals
• Cellular Phones
• MP3 Players
• Digital Still Camera
• Information Appliance
Ordering Code:
Order Number
Package
Number
USB1T1103MPX
MLP14D
USB1T1103MHX
MLP16HB
Package Description
Pb-Free 14-Terminal Molded Leadless Package (MLP), 2.5mm Square
Pb-Free 16-Terminal Molded Leadless Package (MHBCC), JEDEC MO-217, 3mm Square
Pb-Free package per JEDEC J-STD-020B.
© 2005 Fairchild Semiconductor Corporation
DS500905
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USB1T1103 Universal Serial Bus Peripheral Transceiver with Voltage Regulator
April 2005
USB1T1103
Logic Diagram
Connection Diagrams
MLP16 GND Exposed Diepad
MLP14 GND Exposed Diepad
(Bottom View)
(Bottom View)
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2
Terminal Number
MLP14
MLP16
Terminal
Name
I/O
1
1
OE
I
Output Enable:
Active LOW enables the transceiver to transmit data on the bus. When not
active the transceiver is in the receive mode (CMOS level is relative to VCCIO)
2
2
RCV
O
Receive Data Output:
Non-inverted CMOS level output for USB differential Input (CMOS output level
is relative to VCCIO). Driven LOW when SUSPN is HIGH; RCV output is stable
and preserved during SE0 condition.
3
3
Vp/Vpo
I/O
Single-ended D receiver output VP (CMOS level relative to VCCIO):
Used for external detection of SE0, error conditions, speed of connected device;
Terminal also acts as drive data input Vpo (see Table 1 and Table 2).
Output drive is 4 mA buffer.
4
4
Vm/Vmo
I/O
Single-ended D receiver output Vm (CMOS level relative to VCCIO):
Used for external detection of SE0, error conditions, speed of connected device;
Terminal also acts as drive data input Vmo (see Table 1 and Table 2).
Output drive is 4 mA buffer.
5
5
SUSPND
I
—
6
NC
6
7
VCCIO
7
8
Vbusmon
O
9, 8
10, 9
D, D
AI/O
Terminal Description
Suspend:
Enables a low power state (CMOS level is relative to VCCIO). While the
SUSPND terminal is active (HIGH) it will drive the RCV terminal to logic “0”
state.
No Connect
Supply Voltage for digital I/O terminals (1.65V to 3.6V):
When not connected the D and D terminals are in 3-STATE. This supply bus
is totally independent of VCC (5V) and VREG (3.3V), and must never exceed the
VREG (3.3) voltage. For VCCIO disconnected the O/O terminals are HIGH
Impedance and the VPU (3.3V) is turned off.
Vbus monitor output (CMOS level relative to VCCIO):
When Vbus ! 4.1V then Vbusmon HIGH and when Vbus 3.6V then
Vbusmon LOW. If SUSPND HIGH then Vbusmon is pulled HIGH.
Data , Data :
Differential data bus conforming to the USB standard. Terminals are HIGH
Impedance for bus powered mode when Vbus 3.6V. For ByPass Mode then
HIGH Impedance when VREG/ Vbus VREG minimum.
10
11
NC
No Connect
—
12
NC
No Connect
11
13
VREG (3.3V)
Internal Regulator Option:
Regulated supply output voltage (3.0V to 3.6V) during 5V operation;
decoupling capacitor of at least 0.1 PF is required.
Regulator ByPass Option:
Used as supply voltage input for 3.3V operation.
12
14
VCC (5.0V)
Internal Regulator Option:
Used as supply voltage input (4.0V to 5.5V); can be connected directly to USB
line Vbus.
Regulator ByPass Option:
Connected to VREG (3.3V)
13
15
VPU (3.3V)
Pull-up Supply Voltage (3.3V r 10%):
Connect an external 1.5k: resistor on D (FS data rate);
Terminal function is controlled by Config input terminal:
Config LOW VPU (3.3V) is floating (HIGH Impedance) for zero pull-up current.
Config HIGH VPU (3.3V) 3.3V; internally connected to VREG (3.3V).
VPU is OFF in disable mode.
14
16
Config
I
GND
GND
Exposed Exposed
Diepad Diepad
USB connect or disconnect software control input.
Configures 3.3V to external 1.5k: resistor on D when HIGH.
GND supply down bonded to exposed diepad to be connected to the PCB GND.
3
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USB1T1103
Terminal Descriptions
USB1T1103
Functional Description
rather than discrete input and output terminals. Table 1
describes the specific terminal functionality selection. Table
2 and Table 3 describe the specific Truth Tables for Driver
and Receiver operating functions.
The USB1T1103 transceiver is designed to convert CMOS
data into USB differential bus signal levels and to convert
USB differential bus signal to CMOS data.
To minimize EMI and noise the outputs are edge rate controlled with the rise and fall times controlled and defined for
full speed data rates only (12Mbits/s). The rise, fall times
are balanced between the differential terminals to minimize
skew.
The USB1T1103 also has the capability of various power
supply configurations, including a disable mode for VCCIO
disconnected, to support mixed voltage supply applications
(see Table 4) and Section 2.1 for detailed descriptions.
The USB1T1103 differs from earlier USB Transceiver in
that the Vp/Vm and Vpo/Vmo terminals are now I/O terminals
Functional Tables
TABLE 1. Function Select
SUSPND
OE
D, D
RCV
Vp/Vpo
L
L
Driving &
Receiving
Active
Vpo Input
Vmo Input Normal Driving
(Differential Receiver Active)
L
H
Receiving
(Note 1)
Active
Vp Output
Vm Output Receiving
H
L
Driving
Inactive
(Note 2)
Vpo Input
Vmo Input Driving during Suspend
(Differential Receiver Inactive)
H
H
3-STATE
(Note 1)
Inactive
(Note 2)
Vp Output
Vm Output Low Power State
Vm/Vmo
Function
Note 1: Signal levels is function of connection and/or pull-up/pull-down resistors.
Note 2: For SUSPND HIGH mode the differential receiver is inactive and the output RCV is forced LOW. The out-of-suspend signaling (K) is detected via
the single-ended receivers of the Vp/Vpo and Vm/Vmo terminals.
TABLE 2. Driver Function (OE
Note 3: SE0
L) using Differential Input Interface
Data (D / D)
Vm/Vmo
Vp/Vpo
L
L
SE0 (Note 3)
L
H
Differential Logic 1
H
L
Differential Logic 0
H
H
Illegal State
Single Ended Zero
TABLE 3. Receiver Function (OE
H)
D, D
RCV
Vp/Vpo
Differential Logic 1
H
H
L
Differential Logic 0
L
L
H
SE0
X
L
L
Vm/Vmo
X Don’t Care
RCV(0) denotes the signal level on output RCV just prior to the SE0 or SE1 event. This level is stable during the SE0 or SE1 event period.
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4
signals up to 3.6V to share the D and D bus lines.
Internally the circuitry limits leakage from D and D terminals (maximum 10 PA) and VCCIO such that device is
in low power (suspended) state. Terminals Vbusmon
and RCV are forced LOW as an indication of this mode
with Vbusmon being ignored during this state.
• Disable Mode: VCCIO is not connected. VCC is connected, or VCC and VREG are connected. 0V to 3.3V in
this mode D and D are 3-STATE and VPU is HIGH
Impedance (switch is turned off). The USB1T1103 allows
external signals up to 3.6V to share the D and D bus
lines. Internally the circuitry limits leakage from D and
D pins (maximum 10PA).
The three modes of power supply operation are:
• Normal Mode: Regulated Output and Regulator Bypass
1. Regulated Output: VCCIO is connected and VCC(5.0)
is connected to 5V (4.0V to 5.5V) and the internal
voltage regulator then produces 3.3V for the USB
connections.
2. Internal Regulator Bypass Mode: VCCIO is connected and both VCC(5.0) and VREG(3.3) are connected to a 3.3V source (3.0V to 3.6V).
In both cases for normal mode the VCCIO is an independent voltage source (1.65V to 3.6V) that is a function of
the external circuit configuration.
• Sharing Mode: VCCIO is only supply connected. VCC and
VREG are not connected. In this mode the D and D terminals are 3-STATE and the USB1T1103 allows external
A summary of the Supply Configurations is described in
Table 4.
TABLE 4. Power Supply Configuration Options
Power Supply Mode Configuration
Terminals
Normal (Regulated
Output)
Normal (Regulator
Bypass)
Not Connected
or
3.6V
Connected to 5V
Source
Connected to VREG
(3.3V)
[Max Drop of 0.3V]
(2.7V to 3.6V)
3.3V, 300PA
Regulated Output
Not Connected
3.3V, 300 PA
Regulated Output
Connected to 3.3V
Source
Disable
Sharing
VCC (5V)
Connected to 5V
source
VREG (3.3V)
VCCIO
d0.5V
1.65V to 3.6V Source
1.65V to 3.6V Source
1.65V to 3.6V Source
VPU (3.3V)
3-STATE (off)
3-STATE (Off)
3.3V Available if
Config HIGH
3.3V Available if
Config HIGH
D, D
3-STATE (off)
3-STATE
Function of
Mode Set Up
Function of
Mode Set Up
Vp/Vpo, Vm/Vmo
Invalid [I]
L
Function of
Mode Set Up
Function of
Mode Set Up
RCV
Invalid [I]
L
Function of
Mode Set Up
Function of
Mode Set Up
Vbusmon
Invalid [I]
L
Function of
Mode Set Up
Function of
Mode Set Up
OE, SUSPND, Config
Hi-Z
Hi-Z
Function of
Mode Set Up
Function of
Mode Set Up
Invalid [I] I/O are to be 3-STATE, outputs to be LOW.
5
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USB1T1103
Power Supply Configurations and Options
USB1T1103
ESD Protection
Human Body Model
ESD Performance of the USB1T1103
Figure 1 shows the schematic representation of the Human
Body Model ESD event. Figure 2 is the ideal waveform representation of the Human Body Model.
HBM D/D: 15.0kV
HBM, all other terminals (Mil-Std 883E): 6.5kV
IEC 61000-4-2, IEC 60749-26 and IEC 60749-27
• 15kV using the contact Human Body Model
The IEC 61000-4-2 standard covers ESD testing and performance of finished equipment, and as such evaluates the
equipment in its entirety for ESD immunity. Fairchild
Semiconductor has evaluated this device using the
IEC 6100-4-2 representative system model depicted in Figure 3. Under the additional standards set forth by the IEC,
this device is also compliant with IEC 60749-26 (HBM) and
IEC 60749-27 (MM).
• 8kV using the Contact Discharge method as specified in
IEC 61000-4-2
Additional ESD Test Conditions
ESD Protection: D/D Terminals
Since the differential terminals of a USB transceiver may
be subjected to extreme ESD voltages, additional immunity
has been included in the D and D terminals without compromising performance. The USB1T1103 differential terminals have ESD protection to the following limits:
For additional information regarding our product test methodologies and performance levels, please contact Fairchild
Semiconductor.
FIGURE 1. Human Body ESD Test Model
FIGURE 2. HBM Current Waveform
FIGURE 3. IEC 61000-4-2 ESD Test Model
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6
Recommended Operating
Conditions
0.5V to 6.0V
0.5V to 4.6V
Supply Voltage (VCC)(5V)
I/O Supply Voltage (VCCIO)
DC Supply Voltage VCC (5V)
Latch-up Current (ILU)
VI
4.0V to 5.5V
1.65V to 3.6V
I/O DC Voltage VCCIO
1.8V to 5.4V
150 mA
VI 0
0V to VCCIO 5.5V
DC Input Voltage Range (VI)
DC Input Current (IIK)
DC Input Range for AI/O (VAI/O)
18 mA
0V to VCC
Terminals D and D
DC Input Voltage (VI)
0V to 3.6V
Operating Ambient Temperature
0.5V to VCCIO 0.5V
(Note )
40qC to 85qC
(TAMB)
DC Output Diode Current (IOK)
VO ! VCC or VO 0
r18 mA
DC Output Voltage (VO)
0.5V to VCCIO 0.5V
(Note )
Output Source or Sink Current (IO)
VO
0 to VCC
Current for D, D Terminals
r12 mA
r12 mA
Current for RCV, Vm/Vp
DC VCC or GND Current
r100 mA
(ICC, IGND)
ESD Immunity Voltage (VESD);
Contact HBM [3]
Terminals D, D, ILI 1PA
All Other Terminals [3] ILI 1 PA
Storage Temperature (TSTO)
Note 4: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristic tables are not guaranteed at the absolute maximum rating.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
r15kV
r6.5kV
40qC to 125qC
Power Dissipation (PTOT)
Note 5: IO Absolute Maximum Rating must be observed.
ICC (5V)
Note 6: Per ESD Methodology described in page 5.
48 mW
ICCIO
9 mW
DC Electrical Characteristics (Supply Terminals)
Over recommended range of supply voltage and operating free air temperature (unless otherwise noted).
VCC (5V) 4.0V to 5.5V or VREG (3.3V) 3.0V to 3.6V, VCCIO 1.65V to 3.6V
Limits
Symbol
VREG (3.3V)
Parameter
Regulated Supply Output
Internal Regulator Option;
ILOAD d 300 PA
ICC
Operating Supply Current (VCC5.0)
I/O Operating Supply Current
Transmitting and Receiving at
50 pF (D, D)
Transmitting and Receiving at
12 Mbits/s
ICC (IDLE)
Typ
Max
3.0
3.3
3.6
V
4.0
8.0
(Note 9)
1.0
2.0
(Note 9)
Supply Current during
IDLE: VD t 2.7V, VD d 0.3V;
FS IDLE and SE0 (VCC5.0)
SE0: VD d 0.3V, VD d 0.3V
ICCIO (STATIC)
I/O Static Supply Current
IDLE, SUSPND or SE0
ICC(DISABLE)
Disable Supply Current
VCCIO
0V
VCC Connected
ICC(SUSPND)
Units
Min
(Note 7)
(Note 8)
12 Mbits/s; CLOAD
ICCIO
40qC to 85qC
Conditions
Suspend Supply Current
SUSPND
USB1T1103
OE
HIGH
HIGH
Vm
Vp
300
(Note 10)
mA
mA
PA
20.0
PA
25.0
PA
25.0
(Note 10)
PA
20.0
PA
10.0
PA
10.0
PA
OPEN
ICCIO(SHARING) I/O Sharing Mode Supply Current
VCC (5V) Not Connected
ID (SHARING)
Sharing Mode Load Current on
VCC (5V) Not Connected
ID/
D/D Terminals
Config
ID(DISABLE)
Disable Mode Load Current on
VCCIO Not Connected or 0V
ID/
D/D Terminals
Config
LOW; VDr
VD r
3.6V
3.6V LOW or HIGH
7
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USB1T1103
Absolute Maximum Ratings(Note )
USB1T1103
DC Electrical Characteristics
(Continued)
Limits
Symbol
Parameter
40qC to 85qC
Conditions
Min
VCCTH
VCC Threshold Detection Voltage
Typ
Units
Max
1.65V d VCCIO d 3.6V
Supply Lost
3.6
Supply Present
VCCHYS
VCC Threshold Detection
VCCIO
1.8V
70.0
Hysteresis Voltage
VCCIOTH
VCCIO Threshold Detection Voltage
mV
2.7V d VREG d 3.6V
Supply Lost
0.5
Supply Present
VCCIOHYS
VCCIO Threshold Detection
VREG
3.3V
450
Regulated Supply Threshold
1.65V d VCCIO d VREG
Detection Voltage
2.7V d VREG d 3.6V
mV
Supply Lost
Regulated Supply Threshold
VCCIO
V
0.8
Supply Present
VREGHYS
V
1.4
Hysteresis Voltage
VREGTH
V
4.1
2.4
(Note 12)
1.8V
450
Detection Hysteresis Voltage
mV
Note 7: ILOAD includes the pull-up resistor current via terminal VPU
Note 8: The minimum voltage in Suspend mode is 2.7V.
Note 9: Not tested in production, value based on characterization.
Note 10: Excludes any current from load and VPU current to the 1.5k: resistor.
Note 11: Includes current between Vpu and the 1.5k internal pull-up resistor.
Note 12: When VCCIO 2.7V, minimum value for VREGTH
2.0V for supply present condition.
DC Electrical Characteristics
(Digital Terminals – excludes D, D Terminals)
Over recommended range of supply voltage and operating free air temperature (unless otherwise noted). VCCIO
1.65V to 3.6V
Limits
Symbol
Parameter
Test Conditions
40qC to 85qC
Min
Units
Max
Input Levels
VIL
LOW Level Input Voltage
VIH
HIGH Level Input Voltage
0.3*VCCIO
0.6*VCCIO
V
V
OUTPUT LEVELS:
VOL
VOH
LOW Level Output Voltage
HIGH Level Output Voltage
IOL
2 mA
0.4
IOL
100 PA
0.15
IOH
2 mA
VCCIO - 0.4
IOH
100 PA
VCCIO- 0.15
V
V
Leakage Current
ILI
Input Leakage Current
VCCIO
1.65V to 3.6V
Input Capacitance
Terminal to GND
r1.0
(Note 13)
PA
10.0
pF
Capacitance
CIN, CI/O
Note 13: If VCCIO t VREG then leakage current will be higher than specified.
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Over recommended range of supply voltage and operating free air temperature (unless otherwise noted).
VCC 4.0V to 5.5V or VREG 3.0V to 3.6V
Limits
Symbol
Parameter
40qC to 85qC
Test Condition
Min
Typ
Units
Max
Input Levels – Differential Receiver
VDI
Differential Input Sensitivity
VCM
Differential Common Mode Voltage
| VI(D) - VI(D) |
0.2
V
0.8
2.5
V
INPUT LEVELS – Single-ended Receiver
VIL
LOW Level Input Voltage
VIH
HIGH Level Input Voltage
2.0
VHYS
Hysteresis Voltage
0.30
0.8
V
V
0.7
V
0.3
V
3.6
V
r1.0
PA
20.0
pF
Output Levels
VOL
LOW Level Output Voltage
RL
1.5k: to 3.6V
VOH
HIGH Level Output Voltage
RL
15k: to GND
2.8
(Note 14)
Leakage Current
IOFF
Input Leakage Current Off State
CAPACITANCE
CI/O
I/O Capacitance
Terminal to GND
Resistance
ZDRV
Driver Output Impedance
34.0
ZIN
Driver Input Impedance
10.0
RSW
Switch Resistance
VTERM
Termination Voltage
Note 14: If VOH min.
41.0
(Note 15)
44.0
10.0
RPU Upstream Port
3.0
(Note 16)
(Note 17)
:
M:
:
3.6
V
VREG - 0.2V.
Note 15: Includes external resistors of 27: on both D and D terminals.
Note 16: This voltage is available at terminal VPU and VREG.
Note 17: Minimum voltage is 2.7V in the suspend mode.
9
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USB1T1103
DC Electrical Characteristics (Analog I/O Terminals – D, D Terminals)
USB1T1103
AC Electrical Characteristics (A I/O Terminals Full Speed)
Over recommended range of supply voltage and operating free air temperature (unless otherwise noted).
VCC 4.0V to 5.5V or VREG 3.0V to 3.6V, VCCIO 1.65V to 3.6V, CL 50 pF; RL 1.5K on D to VPU
Limits
Symbol
Parameter
40qC to 85qC
Test Conditions
Min
Typ
Unit
Max
Driver Characteristics
tR
Output Rise Time
CL
50 125 pF
4.0
20.0
4.0
20.0
90.0
111.1
%
1.3
2.0
V
Figures 5, 8
18.0
ns
Figures 7, 8
15.0
ns
Figures 7, 9
15.0
ns
Figures 6, 10
15.0
ns
Figures 6, 10
18.0
ns
10% to 90%
tF
Output Fall Time
tRFM
Rise/Fall Time Match
ns
Figures 4, 8
tF/ tR Excludes First Transition
from Idle State
VCRS
Output Signal Crossover Voltage
(Note 18)
Excludes First Transition from
Idle State see Waveform
Driver Timing
tPLH
Propagation Delay
tPHL
(Vp/Vpo, Vm/Vmo to D/D)
tPHZ
Driver Disable Delay
tPLZ
(OE to D/D)
tPZH
Driver Enable Delay
tPZL
(OE to D/D)
Receiver Timing
tPLH
Propagation Delay (Diff)
tPHL
(D/D to Rev)
tPLH
Single Ended Receiver Propagation Delay
tPHL
(D/D to Vp/ Vpo, Vm/Vmo)
Note 18: Not production tested, limits guaranteed by design.
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10
USB1T1103
Typical Application Configurations
Upstream Connection in Bypass Mode with Differential Outputs
Downstream Connection in Normal Mode with Differential Outputs
11
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USB1T1103
AC Waveforms
FIGURE 4. Rise and Fall Times
FIGURE 5. Vpo, Vmo to D/D
FIGURE 6. D/D to RCV, Vpo/Vp and Vmo/Vm
FIGURE 7. OE to D/D
Test Circuits and Waveforms
CL
CL
V
V
50 pF Full Speed Propagation Delays
125 pF Edge Rates only
FIGURE 8. Load for D/D
0 for tPZH, tPHZ
VREG for tPZL
FIGURE 9. Load for Enable and Disable Times
FIGURE 10. Load for Vm/Vmo, Vp/Vpo and RCV
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Tape Format for MHBCC and MLP
Package
Tape
Designator
MHX/MPX
Number
Cavity
Section
Cavities
Status
Cover Tape
Status
Leader (Start End)
125 (typ)
Empty
Sealed
Carrier
2500/3000
Filled
Sealed
Trailer (Hub End)
75 (typ)
Empty
Sealed
TAPE DIMENSIONS inches (millimeters)
REEL DIMENSIONS inches (millimeters)
Tape Size
12 mm
A
B
C
D
N
W1
W2
13.0
0.059
0.512
0.795
7.008
0.488
0.724
330
(1.50)
(13.00)
(20.20)
(178)
(12.4)
(18.4)
13
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USB1T1103
Tape and Reel Specification
USB1T1103
Physical Dimensions inches (millimeters) unless otherwise noted
Pb-Free 14-Terminal Molded Leadless Package (MLP), 2.5mm Square
Package Number MLP14D
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14
USB1T1103 Universal Serial Bus Peripheral Transceiver with Voltage Regulator
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 16-Terminal Molded Leadless Package (MHBCC), JEDEC MO-217, 3mm Square
Package Number MLP16HB
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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15
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