MITSUBISHI M37733S4LHP

MITSUBISHI MICROCOMPUTERS
M37733S4LHP
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New
16-BIT CMOS MICROCOMPUTER
DESCRIPTION
●Serial I/O (UART or clock synchronous)..................................... 3
●10-bit A-D converter .............................................. 8-channel inputs
●12-bit watchdog timer
●Programmable input/output
(ports P4, P5, P6, P7, P8) ........................................................ 37
●Clock generating circuit ........................................ 2 circuits built-in
●Small package ..................... 80-pin plastic molded fine-pitch QFP
(80P6D-A;0.5 mm lead pitch)
The M37733S4LHP is a microcomputer using the 7700 Family core.
This microcomputer has a CPU and a bus interface unit. The CPU is
a 16-bit parallel processor that can be an 8-bit parallel processor,
and the bus interface unit enhances the memory access efficiency to
execute instructions fast. This microcomputer also includes a 32 kHz
oscillation circuit, in addition to the RAM, multiple-function timers,
serial I/O, A-D converter, and so on.
Its strong points are the low power dissipation, the low supply voltage
and the small package.
APPLICATION
Control devices for general commercial equipment such as office
automation, office equipment, personal information equipment, and
so on.
Control devices for general industrial equipment such as
communication equipment, and so on.
FEATURES
●Number of basic instructions .................................................. 103
●Memory size
RAM ................................................ 2048 bytes
●Instruction execution time
The fastest instruction at 12 MHz frequency ...................... 333 ns
●Single power supply ...................................................... 2.7–5.5 V
●Low power dissipation (At 3 V supply voltage, 12 MHz frequency)
............................................ 10.8 mW (Typ.)
●Interrupts ............................................................ 19 types, 7 levels
●Multiple-function 16-bit timer ................................................. 5 + 3
41
42
43
44
45
47
46
49
48
50
51
52
53
55
54
57
56
58
61
40
62
39
63
38
64
37
65
36
66
35
67
34
68
33
69
32
70
31
M37733S4LHP
71
30
72
29
73
28
74
27
75
26
76
25
77
24
20
19
18
17
16
14
15
13
12
11
10
9
8
7
6
5
21
3
80
4
22
2
23
79
1
78
P6 6/TB1IN
P6 5/TB0IN
P6 4/INT2
P6 3/INT1
P6 2/INT0
P61/TA4 IN
P6 0/TA4 OUT
P5 7/TA3 IN/KI3/RTP1 3
P5 6/TA3 OUT/KI2/RTP1 2
P5 5/TA2 IN/KI1/RTP1 1
P5 4/TA2 OUT/KI0/RTP1 0
P5 3/TA1IN/RTP0 3
P5 2/TA1OUT /RTP0 2
P51/TA0 IN/RTP0 1
P50 /TA0 OUT /RTP0 0
P47
P46
P45
P44
P43
P8 5/C LK 1
P8 4/C TS1/R TS1
P8 3/TXD0
P8 2/RXD0/C LKS 0
P81/C LK 0
P8 0/C TS 0/R TS 0 /CLKS1
VC C
AVC C
VR EF
AVSS
VSS
P7 7/AN 7/XCIN
P76 /AN 6/XCOUT
P75/AN 5/ADTRG /TXD 2
P74/AN 4/RXD 2
P73/AN 3/C LK 2
P72/AN 2/C TS2
P71/AN 1
P70/AN 0
P6 7/TB2 IN/ SU B
59
60
P8 6/RxD1
P8 7/TxD1
P0 0/A0
P0 1/A1
P0 2/A2
P0 3/A3
P0 4/A4
P0 5/A5
P0 6/A6
P0 7/A7
P10/A 8/D8
P11/A 9/D9
P12/A10 /D10
P13/A11 /D11
P14/A12 /D12
P15/A13 /D13
P16/A14 /D14
P17/A15 /D15
P20/A16 /D0
P21/A17 /D1
PIN CONFIGURATION (TOP VIEW)
Outline
l
80P6D -A
P2 2/A18 /D2
P2 3/A 19/D3
P2 4/A20 /D4
P2 5/ A21 /D5
P2 6 /A 22 /D6
P2 7/A 23 /D7
P3 0/R /W
P3 1/BHE
P3 2/ALE
P3 3/HL DA
VSS
E
XOUT
XIN
R ESET
C N V SS
BYTE
HOLD
RDY
P4 2 / 1
2
Arithmetic Logic
Unit(16)
1
RDY HOLD HLDA ALE BHE R/W
Data Bank Register DT(8)
Input/Output
port P4
Program Bank Register PG(8)
Input/Output
port P5
Data Address Register DA(24)
Input/Output
port P6
Program Address Register PA(24)
Instruction Register(8)
Reference
External data bus width
voltage input
selection input
VREF
BYTE
Address bus/Data bus
Address higher middler/data (16)
Address Bus
P4(5)
Program Counter PC(16)
A-D Converter(10)
Incrementer/Decrementer(24)
UART0(9)
Incrementer(24)
P5(8)
Timer TB0(16)
Timer TA0(16)
UART2(9)
UART1(9)
AVCC
Instruction Queue Buffer Q2(8)
P6(8)
Timer TB1(16)
(0V)
AVSS
Address bus
Address lower (8)
Instruction Queue Buffer Q0(8)
Input/Output
port P7
Accumulator B(16)
Timer TB2(16)
CNVss
Data Buffer DBL(8)
Input/Output
port P8
Index Register X(16)
Timer TA1(16)
Stack Pointer S(16)
Watchdog Timer
Direct Page Register DPR(16)
Timer TA2(16)
Processor Status Register PS(11)
Timer TA3(16)
(0V)
VSS
Data Buffer DBH(8)
P7(8)
Index Register Y(16)
Timer TA4(16)
VCC
ro
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duc
P8(8)
XCOUT
XCIN
RESET
Reset input
Input Butter Register IB(16)
2048 bytes
RAM
E
Enable
output
p
New
Clock Generating Circuit
Clock input Clock output
XIN
XOUT
M37733S4LHP BLOCK DIAGRAM
MITSUBISHI MICROCOMPUTERS
M37733S4LHP
16-BIT CMOS MICROCOMPUTER
Data Bus(Even)
Data Bus(Odd)
Instruction Queue Buffer Q1(8)
Accumulator A(16)
XCOUT
XCIN
MITSUBISHI MICROCOMPUTERS
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M37733S4LHP
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16-BIT CMOS MICROCOMPUTER
FUNCTIONS OF M37733S4LHP
Parameter
Number of basic instructions
Instruction execution time
Memory size
Input/Output ports
Multi-function timers
RAM
P5 – P8
P4
TA0, TA1, TA2, TA3, TA4
TB0, TB1, TB2
Serial I/O
A-D converter
Watchdog timer
Interrupts
Clock generating circuit
Supply voltage
Power dissipation
Input/Output characteristic
Memory expansion
Operating temperature range
Device structure
Package
Input/Output voltage
Output current
Functions
103
333 ns (the fastest instruction at external clock 12 MHz frequency)
2048 bytes
8-bit ✕ 4
5-bit ✕ 1
16-bit ✕ 5
16-bit ✕ 3
(UART or clock synchronous serial I/O) ✕ 3
10-bit ✕ 1 (8 channels)
12-bit ✕ 1
3 external types, 16 internal types
Each interrupt can be set to the priority level (0 – 7.)
2 circuits built-in (externally connected to a ceramic resonator or a
quartz-crystal oscillator)
2.7 – 5.5 V
10.8 mW (at 3 V supply voltage, external clock 12 MHz frequency)
27 mW (at 5 V supply voltage, external clock 12 MHz frequency)
5V
5 mA
Maximum 16 Mbytes
–40 to 85 °C
CMOS high-performance silicon gate process
80-pin plastic molded fine-pitch QFP (80P6D-A;0.5 mm lead pitch)
3
MITSUBISHI MICROCOMPUTERS
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M37733S4LHP
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16-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION
Pin
Vcc,
Vss
CNVss
_____
Name
Input/Output
Power source
Apply 2.7 – 5.5 V to Vcc and 0 V to Vss.
RESET
CNVss input
Reset input
Input
Input
XIN
Clock input
Input
XOUT
Clock output
Enable output
Bus width
selection input
_
E
BYTE
AVcc,
AVss
VREF
Analog power
source input
Reference
voltage input
P00/A0 –
Address (lowP07/A7
order) output
P10/A8/D8 – Address (middle
P17/A15/D15 -order)
output/data
(high-order) I/O
P20/A16/D0 – Address (highP27/A23/D7 order)
output/data
(low-order) I/O
_
P30/R/W
Read/Write
output
___
P31/BHE
Byte high
enable output
P32/ALE
Address latch
enable output
____
P33/HLDA Hold acknow-
Output
Output
Input
Input
Output
Low-order data (D0 – D7) is input/output or an address (A16 – A23) is output.
Output
“H” indicates the read status and “L” indicates the write status.
Output
“L” is output when an odd-numbered address is accessed.
Output
This is used to retrieve only the address from address and data multiplex signal.
Output
This outputs “L” level when the microcomputer enters hold state after a hold request is accepted.
Clock output
I/O port P4
P50 – P57
I/O port P5
I/O
P60 – P67
I/O port P6
I/O
P70 – P77
I/O port P7
I/O
P80 – P87
I/O port P8
I/O
4
Address (A0 – A7) is output.
I/O
P42/ 1
P43 – P47
___
This is reference voltage input pin for the A-D converter.
When the BYTE pin is set to “L” and external data bus has a 16-bit width, high-order data
(D8 – D15 ) is input/output or an address (A8 – A15) is output. When the BYTE pin is “H” and an
external data bus has an 8-bit width, only address (A8 – A15 ) is output.
RDY
HOLD
Connect to Vcc.
When “L” level is applied to this pin, the microcomputer enters the reset state.
These are pins of main-clock generating circuit. Connect a ceramic resonator or a quartz crystal
oscillator between XIN and XOUT. When an external clock is used, the clock source should be
connected to the XIN pin,
and the XOUT pin should be left open.
_
When output level of E signal is “L”, data/instruction read or data write is performed.
This pin determines whether the external data bus has an 8-bit width or a 16-bit width.
The data bus has a 16-bit width when “L” signal is input and an 8-bit width when “H” signal
is input.
Power source input pin for the A-D converter. Externally connect AVcc to Vcc and AVss to Vss.
I/O
ledge output
Hold request
input
Ready input
____
Functions
Input
Input
Output
I/O
____
This is an input pin for HOLD request signal. The microcomputer enters into hold state while this
signal is “L”.
___
This is an input pin for RDY signal. The microcomputer enters into ready state while this signal is
“L”.
This pin outputs the clock 1.
These pins become a 5-bit I/O port. An I/O direction register is available so that each pin can be
programmed for input or output. These ports are in the input mode when reset.
In addition to having the same functions as port P4, these
pins also function as I/O pins for timers
__
__
A0 to A3 and input pins for key input interrupt input (KI1 – KI3).
In addition to having the same functions as
port ___
P4, these pins also function as I/O pins for timer
___
A4, input pins for external interrupt input (INT0 – INT2) and input pins for timers B0 to B2. P67 also
functions as sub-clock SUB output pin.
In addition to having the same functions as port P4, these pins function as input pins for A-D
converter. P72 to P75 also function as I/O pins for UART2. Additionally, P76 and P77 have the
function as the output pin (XCOUT) and the input pin (XCIN) of the sub-clock (32 kHz) oscillation
circuit, respectively. When P76 and P77 are used as the XCOUT and XCIN pins, connect a resonator
or an oscillator between the both.
In addition to having the same functions as port P4, these pins also function as I/O pins for UART
0 and UART 1.
MITSUBISHI MICROCOMPUTERS
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M37733S4LHP
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16-BIT CMOS MICROCOMPUTER
BASIC FUNCTION BLOCKS
The M37733S4LHP has the same functions as the
M37733MHBXXXFP except for the following :
(1) The memory map is different.
(2) The processor mode is different.
(3) The reset circuit is different.
(4) Pulse output port mode of timer A is available.
(5) The function of ROM area modification is not available.
MEMORY
The 2048-byte area allocated to addresses from 8016 to 87F16 is the
built-in RAM. In addition to storing data, the RAM is used as stack
during a subroutine call or interrupts.
Peripheral devices such as I/O ports, A-D converter, serial I/O, timer,
and interrupt control registers are allocated to addresses from 016 to
7F16 .
A 256-byte direct page area can be allocated anywhere in bank 016
by using the direct page register (DPR). In the direct page addressing
mode, the memory in the direct page area can be accessed with two
words. Hence program steps can be reduced.
The memory map is shown in Figure 1. The address space has a
capacity of 16 Mbytes and is allocated to addresses from 016 to
FFFFFF16. The address space is divided by 64-Kbyte unit called bank.
The banks are numbered from 016 to FF16.
Built-in RAM and control registers for internal peripheral devices are
assigned to bank 016 .
Addresses FFD616 to FFFF16 are the RESET and interrupt vector
addresses and contain the interrupt vectors. Use ROM for memory
of this address.
00000016
00000016
00007F16
00008016
00000016
Internal peripheral
devices
control registers
Bank 016
refer to Fig. 2 for
detail information
00FFFF16
01000016
Internal RAM
2048 bytes
00007F16
Bank 116
Interrupt vector table
00FFD616
01FFFF16
00087F16
A-D/UART2 trans./rece.
UART1 transmission
UART1 receive
•••••••••••••••••••
UART0 transmission
UART0 receive
Timer B2
Timer B1
Timer B0
Timer A4
Timer A3
Timer A2
FE000016
Timer A1
Timer A0
Bank FE16
INT2/Key input
INT1
INT0
FEFFFF16
FF000016
Watchdog timer
DBC
Bank FF16
00FFD616
BRK instruction
Zero divide
FFFFFF16
00FFFF16
00FFFE16
RESET
: Internal
: External
Fig. 1 Memory map
5
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Address (Hexadecimal notation)
000000
000001
000002 Port P0 register
000003 Port P1 register
000004 Port P0 direction register
000005 Port P1 direction register
000006 Port P2 register
000007 Port P3 register
000008 Port P2 direction register
000009 Port P3 direction register
00000A Port P4 register
00000B Port P5 register
00000C Port P4 direction register
00000D Port P5 direction register
00000E Port P6 register
00000F Port P7 register
000010 Port P6 direction register
000011 Port P7 direction register
000012 Port P8 register
000013
000014 Port P8 direction register
000015
000016
000017
000018
000019
00001A
00001B
00001C Pulse output data register 1
00001D Pulse output data register 0
00001E A-D control register 0
00001F A-D control register 1
000020
A-D register 0
000021
000022
A-D register 1
000023
000024
A-D register 2
000025
000026
A-D register 3
000027
000028
A-D register 4
000029
00002A
A-D register 5
00002B
00002C
A-D register 6
00002D
00002E
A-D register 7
00002F
000030 UART 0 transmit/receive mode register
000031 UART 0 baud rate register (BRG0)
000032 UART 0 transmission buffer register
000033
000034 UART 0 transmit/receive control register 0
000035 UART 0 transmit/receive control register 1
000036
UART 0 receive buffer register
000037
000038 UART 1 transmit/receive mode register
000039 UART 1 baud rate register (BRG1)
00003A
UART 1 transmission buffer register
00003B
00003C UART 1 transmit/receive control register 0
00003D UART 1 transmit/receive control register 1
00003E
UART 1 receive buffer register
00003F
16-BIT CMOS MICROCOMPUTER
Address (Hexadecimal notation)
000040
000041
000042
000043
000044
000045
000046
000047
000048
000049
00004A
00004B
00004C
00004D
00004E
00004F
000050
000051
000052
000053
000054
000055
000056
000057
000058
000059
00005A
00005B
00005C
00005D
00005E
00005F
000060
000061
000062
000063
000064
000065
000066
000067
000068
000069
00006A
00006B
00006C
00006D
00006E
00006F
000070
000071
000072
000073
000074
000075
000076
000077
000078
000079
00007A
00007B
00007C
00007D
00007E
00007F
Count start flag
One-shot start flag
Up-down flag
Timer A0 register
Timer A1 register
Timer A2 register
Timer A3 register
Timer A4 register
Timer B0 register
Timer B1 register
Timer B2 register
Timer A0 mode register
Timer A1 mode register
Timer A2 mode register
Timer A3 mode register
Timer A4 mode register
Timer B0 mode register
Timer B1 mode register
Timer B2 mode register
Processor mode register 0
Processor mode register 1
Watchdog timer register
Watchdog timer frequency selection flag
Waveform output mode register
Reserved area (Note)
UART2 transmit/receive mode register
UART2 baud rate register (BRG2)
UART2 transmission buffer register
UART2 transmit/receive control register 0
UART2 transmit/receive control register 1
UART2 receive buffer register
Oscillation circuit control register 0
Port function control register
Serial transmit control register
Oscillation circuit control register 1
A-D/UART2 trans./rece. interrupt control register
UART 0 transmission interrupt control register
UART 0 receive interrupt control register
UART 1 transmission interrupt control register
UART 1 receive interrupt control register
Timer A0 interrupt control register
Timer A1 interrupt control register
Timer A2 interrupt control register
Timer A3 interrupt control register
Timer A4 interrupt control register
Timer B0 interrupt control register
Timer B1 interrupt control register
Timer B2 interrupt control register
INT0 interrupt control register
INT1 interrupt control register
INT2/Key input interrupt control register
Note . Do not write to this address.
Fig. 2 Location of internal peripheral devices and interrupt control registers
6
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Pulse output port mode
The pulse motor drive waveform can be output by using plural internal
timer A.
Figure 3 shows a block diagram for pulse output port mode. In the
pulse output port mode, two pairs of four-bit pulse output ports are
used. Whether using pulse output port or not can be selected by
waveform output selection bit (bit 0, bit 1) of waveform output mode
register (6216 address) shown in Figure 4. When bit 0 of waveform
output selection bit is set to “1”, RTP10, RTP11, RTP12, and RTP13
are used as pulse output ports, and when bit 1 of waveform output
selection bit is set to “1”, RTP00, RTP0 1, RTP0 2, and RTP03 are
used as pulse output ports. When bits 1 and 0 of waveform output
selection bit are set to “1”, RTP10, RTP11, RTP12, and RTP13, and
RTP00 , RTP01, RTP02, and RTP03 are used as pulse output ports.
The ports not used as pulse output ports can be used as normal
parallel ports, timer input/output or key input interrupt input.
In the pulse output port mode, set timers A0 and A2 to timer mode as
timers A0 and A2 are used. Figure 5 shows the bit configuration of
timer A0, A2 mode registers in pulse output port mode.
Data can be set in each bit of the pulse output data register
corresponding to four ports selected as pulse output ports. Figure 6
4
shows the bit configuration of the pulse output data register. The
contents of the pulse output data register 1 (low-order four bits of
1C16 address) corresponding to RTP1 0, RTP11, RTP1 2, and RTP13
is output to the ports each time the counter of timer A2 becomes
000016. The contents of the pulse output data register 0 (low-order
four bits of 1D16 address) corresponding to RTP00 , RTP01, RTP02,
and RTP03 is output to the ports each time the counter of timer A0
becomes 000016.
Figure 7 shows example of waveforms in pulse output port mode.
When “0” is written to a specified bit of the pulse output data register,
“L” level is output to the corresponding pulse output port when the
counter of corresponding timer becomes 000016, and when “1” is
written, “H” level is output to the pulse output port.
Pulse width modulation can be applied to each pulse output port.
Since pulse width modulation involves the use of timers A1 and A3,
activate these timers in pulse width modulation mode.
5
Pulse width modulation selection bit
(Bit 4, 5 of 6216 address)
Pulse width modulation output
by timer A3
Pulse width modulation output
by timer A1
Timer A2
Data bus (odd)
Data bus (even)
Pulse output data
register 1 (1C16 address)
D3
D T Q
RTP13 (P57)
D2
D
Q
RTP12 (P56)
D1
D
Q
RTP11 (P55)
D0
D
Q
D11
D
Q
RTP03 (P53)
D10
D
Q
RTP02 (P52)
D9
D
Q
RTP01 (P51)
D8
D
Q
RTP00 (P50)
T
RTP10 (P54)
Pulse output data
register 0 (1D16 address)
Timer A0
Polarity selection bit
(Bit 3 of 6216 address)
Fig. 3 Block diagram for pulse output port mode
7
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RTP10, RTP11, RTP12, and RTP13 are applied pulse width modulation
by timer A3 by setting the pulse width modulation selection bit by
timer A3 (bit 5) of the waveform output mode register to “1”.
RTP00, RTP01, RTP02, and RTP03 are applied pulse width modulation
by timer A1 by setting the pulse width modulation selection bit by
timer A1 (bit 4) of the waveform output mode register to “1”.
The contents of the pulse output data register 0 can be reversed and
output to pulse output ports RTP00 , RTP01, RTP0 2, and RTP03 by
the polarity selection bit (bit 3) of the waveform output mode register.
When the polarity selection bit is “0”, the contents of the pulse output
data register 0 is output unchangeably, and when “1”, the contents of
the pulse output data register 0 is reversed and output. When pulse
width modulation is applied, likewise the polarity reverse to pulse
width modulation can be selected by the polarity selection bit.
7 6 5 4 3 2 1 0
0
7 6 5 4 3 2 1 0
0 0 X 1 0 0
Address
Timer A0 mode register 5616
Timer A2 mode register 5816
Always “100” in pulse output
port mode
Not used in pulse output port mode
Always “00” in pulse output port mode
Clock source selection bit
0 0 : Select f2
0 1 : Select f16
1 0 : Select f64
1 1 : Select f512
Fig. 5 Timer A0, A2 mode register bit configuration in pulse output
port mode
Address
Weveform output mode register 6216
Weveform output selection bit
0 0 : Parallel port
0 1 : RTP1 selected
1 0 : RTP0 selected
1 1 : RTP1 and RTP0 selected
7 6 5 4 3 2 1 0
Polarity selection bit
0 : Positive polarity
1 : Negative polarity
Pulse width modulation selection bit
by timer A1
0 : Not modulated
1 : Modulated
Pulse width modulation selection bit
by timer A3
0 : Not modulated
1 : Modulated
Always “0”
Address
Pulse output data register 0 1D16
RTP00 output data
RTP01 output data
RTP02 output data
RTP03 output data
7 6 5 4 3 2 1 0
Address
Pulse output data register 1 1C16
RTP10 output data
Fig. 4 Waveform output mode register bit configuration
RTP11 output data
RTP12 output data
RTP13 output data
Fig. 6 Pulse output data register bit configuration
8
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Example of pulse output port (RTP10 – RTP13)
Output signal at each time
when timer A2 becomes 000016
RTP13 (P57)
RTP12 (P56)
RTP11 (P55)
RTP10 (P54)
Example of pulse output port (RTP10 – RTP13) when pulse width modulation is applied by timer A3.
Output signal at each time
when timer A2 becomes 000016
RTP13 (P57)
RTP12 (P56)
RTP11 (P55)
RTP10 (P54)
Example of pulse output port (RTP00 – RTP03) when pulse width modulation is applied
by timer A1 with polarity selection bit = “1”.
Output signal at each time
when timer A0 becomes 000016
RTP03 (P53)
RTP02 (P52)
RTP01 (P51)
RTP00 (P50)
Fig. 7 Example of waveforms in pulse output port mode
9
MITSUBISHI MICROCOMPUTERS
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16-BIT CMOS MICROCOMPUTER
PROCESSOR MODE
• BYTE pin
The bits 0 of processor mode register 0 as shown in Figure 8 is used
to select which mode of microprocessor mode, and evaluation chip
mode.
Figure 9 shows functions of P00/A 0 to P47 pins in each mode.
The external memory area also changes when the mode changes.
Figure 10 shows the memory map for each mode.
The accessing of the external memory is affected by the BYTE pin,
the bit 2 (wait bit) of processor mode register 0, and bit 0 (wait selection
bit) of processor mode register 1.
When accessing the external memory, the level of the BYTE pin is
used to determine whether to use the data bus as 8-bit width or 16bit width.
The data bus width is 8 bits when the level of the BYTE pin is “H”,
and P20/A16 /D0 to P27/A23/D7 pins become the data I/O pins.
The data bus width is 16 bits when the level of the BYTE pin is “L”,
and both P20/A16 /D0 to P27/A23 /D7 pins and P10/A 8/D 8 to P17/A15 /
D15 pins become the data I/O pins.
When accessing the internal memory, the data bus width is always
16 bits regardless of the BYTE pin level.
7 6 5 4 3 2 1 0
0
1
Address
Processor mode register 0 5E16
7 6 5 4 3 2 1 0
Processor mode bit
0 : Microprocessor mode
1 : Evaluation chip mode
This bit must be “1”
(becomes “1” after reset release)
Wait bit
0 : Wait
1 : No Wait
Software reset bit
Reset occurs when this bit is set to “1”
Interrupt priority detection time selection bit
0 0 : Internal clock ✕ 7
0 1 : Internal clock ✕ 4
1 0 : Internal clock ✕ 2
This bit must be “0”
Not used
Fig. 8 Processor mode register bit configuration
10
Processor mode register 1
Wait selection bit
0 : Wait 0
1 : Wait 1
Address
5F16
MITSUBISHI MICROCOMPUTERS
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16-BIT CMOS MICROCOMPUTER
PM1
1
1
PM0
0
1
Mode
Microprocessor mode
Pin
Evaluation Chip mode
E
P00/A0 - P07/A7
P00/A0
Same as left
–
Address A0-A7
P07/A7
BYTE = “L”
E
A8 to A15
P10/A8/D8
–
Address
Same as left
Data(odd)
P17/A15/D15
P10/A8/D8
–
P17/A15/D15
E
P10/A8/D8
Address A8-A15
P17/A15/D15
–
–
BYTE = “H”
E
P10/A8/D8
A8 to A15
Address
Data(odd)
P17/A15/D15
Ports P4, P5 and their direction registers
are treated as 16-bit wide bus.
BYTE = “L”
E
A16 to A23
P20/A16/D0
Same as left
–
Data(even)
Address
P27/A23/D7
P20/A16/D0
E
–
P27/A23/D7
BYTE = “H”
P20/A16/D0
E
A16 to A23
Data(even, odd)
P27/A23/D7
P20/A16/D0
–
–
Address
A16 to A23
Address
Data(even, odd)
P27/A23/D7
Ports P4, P5 and their direction registers
are treated as 16-bit wide bus.
E
P30/R/W,
P31/BHE,
P32/ALE,
P33/HLDA
P30/R/W
R/W
P31/BHE
BHE
P32/ALE
P33/HLDA
ALE
HLDA
E
E
HOLD,
RDY,
P42/ 1,
Port P43 to P47
Same as left
HOLD
HOLD
RDY
RDY
HOLD
RDY
P42/ 1
P42/ 1
P43
-
P47
I/O Port
P43
MX
P44
QCL
P45
VDA
P46
VPA
P47
DBC
Fig. 9 Relationship between pins P00 /A0 to P47 and processor modes
Note. The signal output disable selection bit (bit 6 of the oscillation circuit
control register 0) can stop the
1 output
_
in the microprocessor mode. In the microprocessor mode, signal E can also be fixed to “H” when the internal
memory area is accessed.
11
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16-BIT CMOS MICROCOMPUTER
• Wait bit
As shown in Figure 11, when the external memory area is accessed
with the processor mode register 0 (address 5E16) bit 2 (wait bit)
cleared to “0”, the access time can be extended compared with no
wait (the wait bit is “1”).
The access time is extended in two ways and this is selected with bit
0 (wait selection bit) of processor mode register 1 (address 5F16).
When this bit is “1”, the access time is 1.5 times compared to that for
no wait. When this bit is “0”, the access time is twice compared to
that for no wait.
At reset, the wait bit and the wait selection bit are “0”.
The accessing of internal memory area is performed in no wait mode
regardless of the wait bit.
The processor modes are described below.
Internal clock
Ai/Dj
Wait bit “1”
(No wait)
0016
SFR
Evaluation chip
mode
216
A16
C16
Data Address Data
E
ALE
Access time
Ai/Dj
Wait bit “0”
(Wait 1)
Address
Data
Address
Data
E
ALE
Access time
Ai/Dj
Microprocessor
mode
Address
Wait bit “0”
(Wait 0)
Address
Data
Address
E
ALE
Access time
Fig. 11 Relationship between wait bit, wait selection bit, and access time
SFR
8016
8016
RAM
(1) Microprocessor mode [10]
RAM
87F16
87F16
FFFFFF16
FFFFFF16
The shaded area is the external memory area.
Fig. 10 External memory area for each processor mode
12
Microprocessor mode is entered by connecting the CNVss pin to Vcc
and starting from reset.
_
_
Signal E is output from pin E and is “L” during the data/instruction
code read or data write term. When the internal memory area is read
_
or written, E can be fixed to “H” by setting the signal output disable
selection bit (bit 6 of oscillation circuit control register 0) to “1”.
P00/A0 to P07/A7 pins become address output pins.
P10/A8/D8 to P17/A15/D 15 pins have two functions depending on the
level of the BYTE pin.
When the BYTE pin level is “L”, P10/A8/D8 to P17/A15/D15 pins function
_
as an address
output pin while E is “H” and as an odd address data
_
I/O pin while E is “L”. However,
if an internal memory is read, external
_
data is ignored while E is “L”.
When the BYTE pin level is “H”, P10/A8/D8 to P17/A15/D15 pins function
as an address output pin.
When the BYTE pin level is “L”, P20/A16/D0 to P2 7/A23/D7 pins function
_
as an address
output pin while E is “H” and as an even address data
_
I/O pin while E is “L”. However,
if an internal memory is read, external
_
data
is
ignored
while
E is “L”.
_
R/W is a read /write signal which indicates a read when it is “H” and a
write when it is “L”.
___
BHE is a byte high enable signal which indicates that an odd address
is accessed when it is “L”.
Therefore, two bytes at even and odd addresses are accessed
___
simultaneously if address A0 is “L” and BHE is “L”.
ALE is an address latch enable signal used to latch the address signal
from a multiplexed signal of address and data. The latch is transparent
while ALE is “H” to let the address signal pass through and held
while ALE is “L”.
MITSUBISHI MICROCOMPUTERS
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____
HLDA is a hold acknowledge signal and is used to notify externally
____
when
the microcomputer receives HOLD input and enters hold state.
____
HOLD is a hold request signal. It is an input signal used to put the
____
microcomputer in hold state. HOLD input is accepted when the internal
clock
falls from “H” level to “L” level while the bus is not used.
P00/A0 to P07/A7 pins, P1
0/A 8/D8 to P17/A 15/D15 pins, P2 0/A16 /D0 to
_
___
P27/A23/D7 pins, P30/R/W pin, and P31/BHE pin are floating while the
microcomputer stays in hold state. These pins are floating after one
____
cycle of the internal clock
later than HLDA signal changes to “L”
level. At the removing of hold state, these ports are removed from
____
floating state after one cycle of internal clock
later than HLDA signal
changes to “H” level.
___
RDY is a ready signal. If this signal goes “L”, the internal clock
___
stops at “L”. RDY is used when slow external memory is attached.
P4 2/
1 pin is an output pin for clock
1 . The
1 output is
___
independent of RDY and does not___
stop even when internal clock
stops because of “L” input to the RDY pin. As shown in Table 2,
1
output can also be stopped with the signal output disable selection
bit “1”. In this case, write “1” to the port P42 direction register.
(2) Evaluation chip mode [11]
Evaluation chip mode is entered by applying voltage twice the VCC
voltage to the CNVSS pin. This mode is normally used for evaluation
tools.
_
_ ___
____
The functions of E, P0 0/A0 to P07/A7 pins, R/W, BHE, ALE, and HLDA
are the same as those in microprocessor mode.
P10/A8/D8 to P17/A15/D15 pins function as address output pins while
_
_
E is “H” and as data I/O pin of odd addresses while E is “L” regardless
of the BYTE pin level. However, if an internal memory is read, external
_
data is ignored while E is “L”. P2
0/A16/D0 to P27/A23/D7 pins function
_
as address output
pins while E is “H” and as data I/O pin of even
_
addresses while E is “L” when the BYTE pin level is “L”. However,
if
_
an internal memory is read, external data is ignored while E is “L”.
When the BYTE pin level is “H” or 2•VCC , port P2 functions as an
_
address output pin_while E is “H” and as data I/O pin of even and odd
addresses while E is “L”. However,
if an internal memory is read,
_
external data is ignored while E is “L”.
Port P4 and its data direction which are located at address 0A16 and
0C16 are treated differently in evaluation chip mode. When these
addresses are accessed, the data bus width is treated as 16 bits
regardless of the BYTE pin level, and the access cycle is treated as
internal memory regardless of the wait bit.
____
___
The functions of HOLD and RDY are the same as those in
microprocessor mode. Clock
1 from P42/
1 pin is always output
regardless of signal output disable selection bit.
Ports P43 to P4 6 become MX, QCL, VDA, and VPA output pins
___
respectively. Port P47 becomes the DBC input pin.
The MX signal normally contents of flag m, but the contents of flag x
is output if the CPU is using flag x.
QCL is the queue buffer clear signal. It becomes “H” when the
instruction queue buffer is cleared, for example, when a jump
instruction is executed.
VDA is the valid data address signal. It becomes “H” while the CPU
is reading data from data buffer or writing data to data buffer. It also
becomes “H” when the first byte of the instruction (operation code) is
read from the instruction queue buffer.
VPA is the valid program address signal. It becomes “H” while the
CPU is reading an instruction code from the instruction queue buffer.
___
DBC is the debug control signal and is used for debugging. Table 1
shows the relationship between the CNVSS pin input levels and
processor modes.
Table 1. Relationship between CNVss pin input levels and processor
modes
CNVss
Mode
Description
•
Microprocessor
Microprocessor
mode upon
Vss
(• Evaluation chip) starting after reset.
• Evaluation chip
Evaluation chip mode only.
2 • Vcc
Table 2. Function of signal output disable selection bit CM6 (bit 6 of oscillation circuit control register 0)
Processor mode
Pin
_
E
Function
CM6 = “0”
_
E is output when the internal/external memory
area is accessed.
After WIT/STP instruction is executed,
“H” is output.
Microprocessor mode
1
Clock
1
is output.
_
CM6 = “1”
E is output only when the external memory
area is accessed.
“L” is output after WIT/STP instruction is
executed.
∗ Standby state selection bit (bit 0 of port
function control register) must be set to “1”.
“H”or “L” is output. (Output the content of
P42 latch.)
∗ Port P42 direction register must be set to
“1”.
Note. Functions shown in Table 2 cannot be emulated in a debugger.
13
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RESET CIRCUIT
_____
The microcomputer is released from the reset state when the RESET
pin is returned to “H” level after holding it at “L” level with the power
source voltage at 2.7 – 5.5 V. Program execution starts at the address
formed by setting address A23 – A16 to 0016, A15 – A8 to the contents
of address FFFF16 , and A7 – A0 to the contents of address FFFE16.
Figure 12 shows the status of the internal registers during reset.
Figure 13 shows an example of a reset circuit. If the stabilized clock
is input from the external to the main-clock oscillation circuit, the reset
input voltage must be 0.55 V or less when the power source voltage
reaches 2.7 V. If a resonator/oscillator is connected to the main-clock
oscillation circuit, change the reset input voltage from “L” to “H” after
the main-clock oscillation is fully stabilized.
Address
Address
Port P0 direction register
(0416)•••
0016
Watchdog timer frequency selection flag
(6116)•••
Port P1 direction register
(0516)•••
0016
Waveform output mode register
(6216)••• 0
Port P2 direction register
(0816)•••
0016
UART2 transmit/receive mode register
(6416)•••
0 0 0 0 0 0 0
Port P3 direction register
(0916)•••
UART2 transmit/receive control register 0
(6816)•••
1 0 0 0
Port P4 direction register
(0C16)•••
0016
UART2 transmit/receive control register 1
(6916)••• 0 0 0 0 0 0 1 0
Port P5 direction register
(0D16)•••
0016
Oscillation circuit control register 0
(6C16)•••
Port P6 direction register
(1016)•••
0016
Port function control register
(6D16)•••
Port P7 direction register
(1116)•••
0016
Serial transmit control register
(6E16)•••
Port P8 direction register
(1416)•••
0016
Oscillation circuit control register 1
(6F16)••• 0
A-D control register 0
(1E16)••• 0 0 0 0 0 ? ? ?
A-D/UART2 trans./rece. interrupt control register
(7016)•••
0 0 0 0
UART 0 transmission interrupt control register (7116)•••
0 0 0 0
0 0 0 0
1 1
0
0 0 0
0 0 0 0 0
0 0
1
0016
0 0
0 0 0 0 0
A-D control register 1
(1F16)•••
0 0 0
UART 0 transmit/receive mode register
(3016)•••
0016
UART 0 receive interruupt control register
(7216)•••
0 0 0 0
UART 1 transmit/receive mode register
(3816)•••
0016
UART 1 transmission interrupt control register (7316)•••
0 0 0 0
UART 0 transmit/receive
control register 0
UART 1 transmit/receive
control register 0
UART 0 transmit/receive
control register 1
UART 1 transmit/receive
control register 1
Count start flag
(3416)••• 0 0 0 0 1 0 0 0
UART 1 receive interruupt control register
(7416)•••
0 0 0 0
(3C16)••• 0 0 0 0 1 0 0 0
Timer A0 interrupt control register
(7516)•••
0 0 0 0
(3516)••• 0 0 0 0 0 0 1 0
Timer A1 interrupt control register
(7616)•••
0 0 0 0
(3D16)••• 0 0 0 0 0 0 1 0
Timer A2 interrupt control register
(7716)•••
0 0 0 0
(4016)•••
0016
Timer A3 interrupt control register
(7816)•••
0 0 0 0
One- shot start flag
(4216)•••
0 0 0 0 0
Timer A4 interrupt control register
(7916)•••
0 0 0 0
Up-down flag
(4416)•••
0016
Timer B0 interrupt control register
(7A16)•••
0 0 0 0
Timer A0 mode register
(5616)•••
0016
Timer B1 interrupt control register
(7B16)•••
0 0 0 0
Timer A1 mode register
(5716)•••
0016
Timer B2 interrupt control register
(7C16)•••
0 0 0 0
Timer A2 mode register
(5816)•••
0016
INT0 interrupt control register
(7D16)•••
0 0 0 0 0 0
Timer A3 mode register
(5916)•••
0016
INT1 interrupt control register
(7E16)•••
0 0 0 0 0 0
Timer A4 mode register
(5A16)•••
0016
INT2/Key input interrupt control register
(7F16)•••
0 0 0 0 0 0
Timer B0 mode register
(5B16)••• 0 0 1 0 0 0 0 0
Processor status register (PS)
Timer B1 mode register
(5C16)••• 0 0 1
Program bank register (PG)
Timer B2 mode register
(5D16)••• 0 0 1
Processor mode register 0
(5E16)•••
Processor mode register 1
(5F16)•••
Watchdog timer register
(6016)•••
0 0 0 0
0 0 0 0
0016
0
FFF16
0 0 0 ? ? 0 0 0 1 ? ?
0016
Program counter (PCH)
Content of FFFF16
Program counter (PCL)
Content of FFFE16
Direct page register (DPR)
Data bank register (DT)
000016
0016
Contents of other registers and RAM are undefined during reset. Initialize them by software.
Fig. 12 Microcomputer internal status during reset
14
MITSUBISHI MICROCOMPUTERS
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Power on
2.7V
VCC
RESET
VCC
0V
RESET
0V
0.55V
Note. In this case, stabilized clock is input from the
external to the main-clock oscillation circuit.
Perform careful evalvation at the system design
level before using.
Fig. 13 Example of a reset circuit
ADDRESSING MODES
The M37733S4LHP has 28 powerful addressing modes. Refer to the
MITSUBISHI SEMICONDUCTORS DATA BOOK SINGLE - CHIP
16-BIT MICROCOMPUTERS for the details of each addressing mode.
MACHINE INSTRUCTION LIST
The M37733S4LHP has 103 machine instructions. Refer to the
MITSUBISHI SEMICONDUCTORS DATA BOOK SINGLE - CHIP
16-BIT MICROCOMPUTERS for details.
15
MITSUBISHI MICROCOMPUTERS
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16-BIT CMOS MICROCOMPUTER
ABSOLUTE MAXIMUM RATINGS
Symbol
Vcc
AVcc
VI
VI
VO
Pd
Topr
Tstg
Parameter
Power source voltage
Analog power____
source voltage
Input voltage RESET, CNVss, BYTE
Input voltage P10 /A8 /D8 – P17/A 15/D15,
P20 /A16/D0 – P27 /A23/D7 , P43 – P47,
P50 – P57 , P60 – P67 ,___
P70 –___
P77 ,
P80 – P87 , VREF, XIN, HOLD, RDY
Output voltage P00 /A0 – P07 /A7 , P10/A 8/D8 – P1_
7 /A15/D15,
P20 /A__
16/D0 – P27 /A23/D7 , P30/R/W,
___
P31 /BHE, P32 /ALE, P33/HLDA , P42 / 1,
P43 – P47 , P50 – P57 , P60 – _
P67 ,
P70 – P77 , P80 – P87 , XOUT, E
Power dissipation
Operating temperature
Storage temperature
Conditions
Ratings
–0.3 to +7
–0.3 to +7
–0.3 to +12
Unit
V
V
V
–0.3 to Vcc + 0.3
V
–0.3 to Vcc + 0.3
V
200
–40 to +85
–65 to +150
mW
°C
°C
Ta = 25 °C
RECOMMENDED OPERATING CONDITIONS (Vcc = 2.7 – 5.5 V, Ta = –40 to +85 °C, unless otherwise noted)
Symbol
Vcc
AVcc
Vss
AVss
VIH
VIH
VIL
VIL
IOH(peak)
IOH(avg)
IOL(peak)
IOL(peak)
IOL(avg)
I OL(avg)
f(X IN)
f(X CIN)
Parameter
f(XIN) : Operating
Power source voltage
f(XIN) : Stopped, f(XCIN) = 32.768 kHz
Analog power source voltage
Power source voltage
Analog power source voltage
___ ___
High-level input voltage HOLD, RDY , P43____
– P47 , P50 – P57, P6 0 – P67, P7 0 – P77,
P80 – P87 , XIN, RESET, CNVss, BYTE, XCIN (Note 3)
High-level input voltage ___
P1 0/A
8/D8 – P17/A15/D15, P2 0/A16/D0 – P27/A23/D7
___
Low-level input voltage HOLD, RDY, P43____
– P47 , P50 – P57 , P60 – P67 , P70 – P77 ,
P80 – P87, XIN, RESET , CNVss, BYTE, XCIN (Note 3)
Low-level input voltage P10/A8/D8 – P17/A15 /D15, P20/A16 /D0 – P27/A23 /D7
High-level peak output current P0 0/A 0 – P0 7/A7, P1 0/A8/D8 – P1_7/A15 /D___
15,
P20/A16/D0 – P2
7/A23/D7, P3 0/R/ W, P31/ BHE,
___
P32/ALE, P33/HLDA, P42/ 1, P43 – P47,
P50 – P57, P60 – P6 7, P7 0 – P77, P80 – P87
High-level average output current P00/A0 – P0 7/A 7, P1 0/A 8/D8 – P1_7/A 15/D___
15,
P20/A16/D0 – P2
7/A23/D7, P3 0/R/ W, P31/BHE,
____
P32/ALE, P33/HLDA , P42/ 1, P4 3 – P4 7,
P50 – P57, P6 0 – P6 7, P7 0 – P77, P80 – P87
Low-level peak output current P00/A0 – P07/A7, P10/A8/D 8 – P1_
7/A15 /D___
15,
P20/A16 /D0 – P2
7/A23 /D7, P3 0/R/W, P3 1/ BHE,
____
P32/ALE, P33/ HLDA, P42/ 1, P43, P54 – P57,
P60 – P6 7, P7 0 – P7 7, P80 – P87
Low-level peak output current P44 – P47, P5 0 – P5 3
Low-level average output current P00/A0 – P07/A7, P10/A8/D8 – P1_
7/A15/D___
15 ,
P20/A16/D0 – P2
7/A23/D7, P3 0/R/ W, P31/BHE,
____
P32/ALE, P33/HLDA , P42/ 1, P4 3, P5 4 – P57,
P60 – P67, P70 – P77, P8 0 – P8 7
Low-level average output current P44 – P47, P5 0 – P5 3
Main-clock oscillation frequency (Note 4)
Sub-clock oscillation frequency
Min.
2.7
2.7
Limits
Typ.
Max.
5.5
5.5
Vcc
0
0
Unit
V
V
V
V
0.8 Vcc
Vcc
V
0.5 Vcc
Vcc
V
0
0.2Vcc
V
0
0.16Vcc
V
–10
mA
–5
mA
10
mA
16
mA
5
mA
12
12
50
mA
MHz
kHz
32.768
Notes 1. Average output current is the average value of a 100 ms interval.
_
___
2. ____
The sum of IOL(peak) for ports P00/A0 – P07/A7, P10/A8/D8 – P17/A15/D15, P2 0/A16 /D0 – P27/A23 /D7, P30/R/W , P31/BHE, P32/ALE, P33/
HLDA and P8 must be 80 mA or less, the sum of IOH(peak) for ports P0 0/A0 – P07/A7, P10/A8/D8 – P17/A15/D15, P2 0/A16 /D0 – P27/A23/
_
___
____
D7, P30/R/W, P3 1/ BHE, P3 2/ALE, P33/HLDA and P8 must be 80 mA or less, the sum of IOL(peak) for ports P4, P5, P6, and P7 must be
100 mA or less, and the sum of I OH(peak) for ports P4, P5, P6, and P7 must be 80 mA or less.
3. Limits VIH and VIL for XCIN are applied when the sub clock external input selection bit = “1”.
4. The maximum value of f(XIN) = 6 MHz when the main clock division selection bit = “1”.
16
MITSUBISHI MICROCOMPUTERS
M37733S4LHP
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16-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = –40 to +85 °C, f(XIN) = 12 MHz, unless otherwise noted)
Symbol
VOH
VOH
VOH
VOH
VOL
VOL
VOL
VOL
VOL
VT+ – VT–
VT+ – VT–
VT+ – VT–
VT+ – V T–
IIH
I IL
IIL
VRAM
Parameter
Test conditions
High-level output voltage P00 /A0 – P07 /A7 , P10/A 8/D8 – P1
7/A15/D15 ,
___
P20/A 16/D0 – P27/A 23/D7, P3 3/HLDA, P4 2/ 1, VCC = 5 V, IOH = –10 mA
P43 – P47, P5 0 – P57, P6 0 – P67, P70 – P77,
VCC = 3 V, IOH = –1 mA
P80 – P87
High-level output voltage P00 /A0 – P07 /A7 , P10/A 8/D8 – P1
7/A15/D15 ,
___
VCC = 5 V, IOH = –400 A
P20/A 16/D0 – P27/A 23/D7, P3 3/HLDA, P4 2/ 1
VCC = 5 V, IOH = –10 mA
_
___
High-level output voltage P30/R/ W, P31/BHE, P3 2/ALE
VCC = 5 V, IOH = –400 A
VCC = 3 V, IOH = –1 mA
VCC = 5 V, IOH = –10 mA
_
High-level output voltage E
VCC = 5 V, IOH = –400 A
VCC = 3 V, IOH = –1 mA
Low-level output voltage P00 /A0 – P07 /A7 , P10 /A8/D 8 – P1
7/A 15/D 15,
___
VCC = 5 V, IOL = 10 mA
P20/A 16/D0 – P27 /A23/D7 , P33/HLDA, P42/ 1,
P43, P5 4 – P57, P6 0 – P67, P7 0 – P77,
VCC = 3 V, IOL = 1 mA
P80 – P87
VCC = 5 V, IOL = 16 mA
Low-level output voltage P44 – P47, P50 – P53
VCC = 3 V, IOL = 10 mA
Low-level output voltage P00 /A0 – P07 /A7 , P10 /A8/D 8 – P1
7/A 15/D 15,
___
VCC = 5 V, IOL = 2 mA
P20/A 16/D0 – P27 /A23/D7 , P33/HLDA, P42 / 1
VCC = 5 V, IOL = 10 mA
_
___
Low-level output voltage P30/R/W, P3 1/ BHE, P32/ALE
VCC = 5 V, IOL = 2 mA
VCC = 3 V, IOL = 1 mA
VCC = 5 V, IOL = 10 mA
_
Low-level output voltage E
VCC = 5 V, IOL = 2 mA
VCC = 3 V, IOL = 1 mA
____ ___
Hysteresis ___
HOLD, ___
RDY , ____
TA0IN ____
– TA4____
IN, TB0
IN – TB2IN,
____
VCC = 5 V
INT0 – INT2 , AD
TRG, CTS0 , CTS1 , CTS2, CLK0 ,
__
__
VCC = 3 V
CLK1, CLK2, KI0 – KI3
_____
VCC = 5 V
Hysteresis RESET
VCC = 3 V
VCC = 5 V
Hysteresis XIN
VCC = 3 V
VCC = 5 V
Hysteresis XCIN (When external clock is input)
VCC = 3 V
High-level input current P10/A 8/D8 – P17 /A15/D15,
VCC = 5 V, VI = 5 V
P20 /A16/D0 – P27 /A23/D7 , P43 – P47 ,
P50 ____
– P57 , P60 – P67 , P70 – P77 , P80 – P87 ,
VCC = 3 V, VI = 3 V
XIN, RESET, CNVss, BYTE
Low-level input current P10/A 8/D8 – P17 /A15/D15,
VCC = 5 V, VI = 0 V
P20 /A16/D0 – P27 /A23/D7 , P43 – P47 ,
P50 – P53, P60 ,____
P61 , P65 – P67 , P70 – P77,
VCC = 3 V, VI = 0 V
P80 – P87, XIN, RESET, CNVss, BYTE
Low-level input current P54 – P57, P6 2 – P6 4
RAM hold voltage
V I = 0 V,
VCC = 5 V
without a pull-up
VCC = 3 V
transistor
V I = 0 V,
VCC = 5 V
with a pull-up
VCC = 3 V
transistor
When clock is stopped
Min.
Limits
Typ.
Max.
Unit
3
V
2.5
4.7
V
3.1
4.8
2.6
3.4
4.8
2.6
V
V
2
V
0.5
1.8
1.5
V
0.45
V
1.9
0.43
0.4
1.6
0.4
0.4
0.4
1
0.1
0.7
0.2
0.1
0.1
0.06
0.1
0.06
0.5
0.4
0.4
0.26
0.4
0.26
V
V
V
V
V
V
5
A
4
–5
A
–4
–5
A
–4
–0.25
–0.5
–1.0
–0.08
–0.18
–0.35
2
mA
V
17
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ELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = –40 to +85 °C, unless otherwise noted)
Symbol
Parameter
Test conditions
Min.
VCC = 5 V,
f(X IN) = 12 MHz (square waveform),
(f(f2) = 6 MHz),
f(X CIN) = 32.768 kHz,
in operating (Note 1)
Power source
current
I CC
VCC = 3 V,
f(X IN) = 12 MHz (square waveform),
(f(f2) = 6 MHz),
f(X CIN) = 32.768 kHz,
in operating (Note 1)
VCC = 3 V,
f(X IN) = 12 MHz (square waveform),
(f(f2) = 0.75 MHz),
When external bus
f(X CIN) = Stopped,
is in use, output
pins are open, and in operating
other pins are VSS. VCC = 3 V,
f(X IN) = 12 MHz (square waveform),
f(X CIN) = 32.768 kHz,
when a WIT instruction is executed (Note 2)
VCC = 3 V,
f(X IN) = Stopped,
f(X CIN) = 32.768 kHz,
in operating (Note 3)
VCC = 3 V,
f(X IN) = Stopped,
f(X CIN) = 32.768 kHz,
when a WIT instruction is executed (Note 4)
Ta = 25 °C,
when clock is stopped
Ta = 85 °C,
when clock is stopped
Limits
Typ.
Max.
Unit
5.4
10.8
mA
3.6
7.2
mA
0.5
1.0
mA
6
12
A
40
80
A
3
6
A
1
A
20
A
Notes 1. This applies when the main clock external input selection bit = “1”, the main clock division selection bit = “0”, and the signal output stop
bit = “1”.
2. This applies when the main clock external input selection bit = “1” and the system clock stop bit at wait state = “1”.
3. This applies when CPU and the clock timer are operating with the sub clock (32.768 kHz) selected as the system clock.
4. This applies when the XCOUT drivability selection bit = “0” and the system clock stop bit at wait state = “1”.
A–D CONVERTER CHARACTERISTICS
(VCC = AVCC = 5 V, VSS = AVSS = 0 V, Ta = –40 to +85 °C, f(X IN) = 12 MHz, unless otherwise noted (Note))
Symbol
—
—
RLADDER
tCONV
VREF
VIA
Parameter
Resolution
Absolute accuracy
Ladder resistance
Conversion time
Reference voltage
Analog input voltage
Test conditions
VREF = VCC
VREF = VCC
VREF = VCC
Note. This applies when the main clock division selection bit = “0” and f(f2) = 6 MHz.
18
Min.
10
19.6
2.7
0
Limits
Typ.
Max.
10
±3
25
VCC
VREF
Unit
Bits
LSB
kΩ
s
V
V
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TIMING REQUIREMENTS (VCC = 2.7 – 5.5 V , VSS = 0 V, Ta = –40 to +85 °C, f(XIN) = 12 MHz, unless otherwise noted (Note 1))
Notes 1. This applies when the main clock division selection bit = “0” and f(f2) = 6 MHZ .
2. Input signal’s rise/fall time must be 100 ns or less, unless otherwise noted.
External clock input
Symbol
tc
tw(H)
tw(L)
tr
tf
Parameter
External clock input cycle time (Note 1)
External clock input high-level pulse width (Note 2)
External clock input low-level pulse width (Note 2)
External clock rise time
External clock fall time
Limits
Min.
83
33
33
Max.
15
15
Unit
ns
ns
ns
ns
ns
Notes 1. When the main clock division selection bit = “1”, the minimum value of tc = 166 ns.
2. When the main clock division selection bit = “1”, values of tw(H) / tc and tw(L) / tc must be set to values from 0.45 through 0.55.
Microprocessor mode
Symbol
tsu(P4D–E)
tsu(P5D–E)
tsu(P6D–E)
tsu(P7D–E)
tsu(P8D–E)
th(E–P4D)
th(E–P5D)
th(E–P6D)
th(E–P7D)
th(E–P8D)
tsu(D–E)
tsu(RDY– 1)
tsu(HOLD– 1)
th(E–D)
th( 1–RDY)
th( 1–HOLD)
Parameter
Port P4 input setup time
Port P5 input setup time
Port P6 input setup time
Port P7 input setup time
Port P8 input setup time
Port P4 input hold time
Port P5 input hold time
Port P6 input hold time
Port P7 input hold time
Port P8 input hold time
Data input setup time
___
RDY input setup time
____
HOLD input setup time
Data input hold time
___
RDY input hold time
____
HOLD input hold time
Limits
Min.
200
200
200
200
200
0
0
0
0
0
80
80
80
0
0
0
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
19
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Timer A input
(Count input in event counter mode)
Symbol
tc(TA)
tw(TAH)
tw(TAL)
parameter
TAiIN input cycle time
TAiIN input high-level pulse width
TAiIN input low-level pulse width
Limits
Min.
250
125
125
Max.
Unit
ns
ns
ns
Timer A input (Gating input in timer mode)
Symbol
tc(TA)
tw(TAH)
tw(TAL)
parameter
TAiIN input cycle time (Note)
TAiIN input high-level pulse width (Note)
TAiIN input low-level pulse width (Note)
Limits
Min.
666
333
333
Max.
Unit
ns
ns
ns
Note. Limits change depending on f(XIN). Refer to “DATA FORMULAS.”
Timer A input (External trigger input in one-shot pulse mode)
Symbol
t c(TA)
tw(TAH)
tw(TAL)
parameter
TAiIN input cycle time (Note)
TAiIN input high-level pulse width
TAiIN input low-level pulse width
Limits
Min.
666
166
166
Max.
Unit
ns
ns
ns
Note. Limits change depending on f(XIN). Refer to “DATA FORMULAS.”
Timer A input (External trigger input in pulse width modulation mode)
Symbol
tw(TAH)
tw(TAL)
parameter
TAiIN input high-level pulse width
TAiIN input low-level pulse width
Limits
Min.
166
166
Max.
Unit
ns
ns
Timer A input (Up-down input in event counter mode)
Symbol
tc(UP)
tw(UPH)
tw(UPL)
tsu(UP–TIN)
th(TIN–UP)
parameter
TAiOUT input cycle time
TAiOUT input high-level pulse width
TAiOUT input low-level pulse width
TAiOUT input setup time
TAiOUT input hold time
Limits
Min.
3333
1666
1666
666
666
Max.
Unit
ns
ns
ns
ns
ns
Timer A input (Two-phase pulse input in event counter mode)
Symbol
tc(TA)
tsu(TAjIN–TAjOUT)
tsu(TAjOUT–TAjIN)
20
parameter
TAjIN input cycle time
TAjIN input setup time
TAjOUT input setup time
Limits
Min.
2000
500
500
Max.
Unit
ns
ns
ns
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Timer B input (Count input in event counter mode)
Symbol
tc(TB)
tw(TBH)
tw(TBL)
tc(TB)
tw(TBH)
tw(TBL)
Limits
Parameter
Min.
250
125
125
500
250
250
TBiIN input cycle time (one edge count)
TBiIN input high-level pulse width (one edge count)
TBiIN input low-level pulse width (one edge count)
TBiIN input cycle time (both edges count)
TBiIN input high-level pulse width (both edges count)
TBiIN input low-level pulse width (both edges count)
Max.
Unit
ns
ns
ns
ns
ns
ns
Timer B input (Pulse period measurement mode)
Symbol
tc(TB)
tw(TBH)
tw(TBL)
Limits
Parameter
Min.
666
333
333
TBiIN input cycle time (Note)
TBiIN input high-level pulse width (Note)
TBiIN input low-level pulse width (Note)
Max.
Unit
ns
ns
ns
Note. Limits change depending on f(XIN). Refer to “DATA FORMULAS.”
Timer B input (Pulse width measurement mode)
Symbol
tc(TB)
tw(TBH)
tw(TBL)
Limits
Parameter
Min.
666
333
333
TBiIN input cycle time (Note)
TBiIN input high-level pulse width (Note)
TBiIN input low-level pulse width (Note)
Max.
Unit
ns
ns
ns
Note. Limits change depending on f(XIN). Refer to “DATA FORMULAS.”
A-D trigger input
Symbol
Limits
Parameter
Min.
1333
166
____
tc(AD)
tw(ADL)
AD
TRG input cycle time (minimum allowable trigger)
____
ADTRG input low-level pulse width
Max.
Unit
ns
ns
Serial I/O
Symbol
tc(CK)
tw(CKH)
tw(CKL)
td(C–Q)
th(C–Q)
tsu(D–C)
th(C–D)
Limits
Parameter
Min.
333
166
166
CLKi input cycle time
CLKi input high-level pulse width
CLKi input low-level pulse width
TXDi output delay time
TXDi hold time
RXDi input setup time
RXDi input hold time
Max.
100
0
65
75
____
Unit
ns
ns
ns
ns
ns
ns
ns
___
External interrupt INT i input, key input interrupt KIi input
Symbol
Parameter
___
tw(INH)
tw(INL)
tw(KIL)
INTi input high-level pulse width
INTi input low-level pulse width
__
KIi input low-level pulse width
___
Limits
Min.
250
250
250
Max.
Unit
ns
ns
ns
21
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DATA FORMULAS
Timer A input (Gating input in timer mode)
Symbol
Parameter
t c(TA)
TAiIN input cycle time
t w(TAH)
TAiIN input high-level pulse width
t w(TAL)
TAiIN input low-level pulse width
Limits
Min.
8 ✕ 109
2 • f(f2)
4 ✕ 109
2 • f(f2)
4 ✕ 109
2 • f(f2)
Max.
Unit
ns
ns
ns
Timer A input (External trigger input in one-shot pulse mode)
Symbol
t c(TA)
Parameter
TAiIN input cycle time
Limits
Min.
8 ✕ 109
2 • f(f2)
Max.
Unit
ns
Timer B input (In pulse period measurement mode or pulse width measurement mode)
Symbol
Parameter
tc(TB)
TBiIN input cycle time
tw(TBH)
TBiIN input high-level pulse width
tw(TBL)
TBiIN input low-level pulse width
Limits
Min.
8 ✕ 109
2 • f(f2)
4 ✕ 109
2 • f(f2)
4 ✕ 109
2 • f(f2)
Note. f(f 2) expresses the clock f 2 frequency.
For the relation to the main clock and sub clock, refer to Table 9 in data sheet “M37733MHBXXXFP”.
22
Max.
Unit
ns
ns
ns
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SWITCHING CHARACTERISTICS
(VCC = 2.7 – 5.5 V, V SS = 0 V, Ta = –40 to +85°C, f(XIN) = 12 MHz, unless otherwise noted (Note))
Microprocessor mode
Symbol
td(E–P4Q)
td(E–P5Q)
td(E–P6Q)
td(E–P7Q)
td(E–P8Q)
Parameter
Test conditions
Port P4 data output delay time
Port P5 data output delay time
Port P6 data output delay time
Port P7 data output delay time
Port P8 data output delay time
Fig. 14
Limits
Min.
Max.
300
300
300
300
300
Unit
ns
ns
ns
ns
ns
Note. This applies when the main clock division selection bit = “0” and f(f2) = 6 MHz.
A0–A7
A 8/D 8 – A 23/D 7
R/W
BHE
50 pF
ALE
HLDA
P4
P5
P6
P7
P8
1
E
Fig. 14 Measuring circuit for each pin
23
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16-BIT CMOS MICROCOMPUTER
Microprocessor mode
(VCC = 2.7 – 5.5 V, V SS = 0 V, Ta = –40 to +85 °C, f(XIN) = 12 MHz, unless otherwise noted (Note 1))
Symbol
td(An–E)
Parameter
Address output delay time
td(A–E)
Address output delay time
th(E–An)
Address hold time
tw(ALE)
ALE pulse width
tsu(A–ALE)
th(ALE–A)
Address output setup time
Address hold time
td(ALE–E)
ALE output delay time
td(E–DQ)
th(E–DQ)
Data output delay time
Data hold time
_
tw(EL)
E pulse width
tpxz(E–DZ)
tpzx(E–DZ)
td(BHE–E)
td(R/W–E)
th(E–BHE)
th(E–R/W)
td(E–
td(
1)
Test
(Note2)
Wait mode conditions
No wait
Wait 1
Wait 0
No wait
Wait 1
Wait 0
No wait
Wait 1
Wait 0
No wait
Wait 1
Wait 0
No wait
Wait 1
Wait 0
No wait
Wait 1
Wait 0
Fig. 14
BHE output delay time
_
R/W output delay time
No wait
Wait 1
Wait 0
No wait
Wait 1
Wait 0
No wait
Wait 1
Wait 0
BHE hold time
_
R/W hold time
output delay time
____
1–HLDA)
HLDA output delay time
Notes 1. This applies when the main clock division selection bit = “0” and f(f 2) = 6 MHz.
2. No wait : Wait bit = “1”.
Wait 1 : The external memory area is accessed with wait bit = “0” and wait selection bit = “1”.
Wait 0 : The external memory area is accessed with wait bit = “0” and wait selection bit = “0”.
24
Unit
20
ns
182
ns
20
ns
162
ns
40
ns
40
ns
123
ns
10
ns
93
ns
9
ns
40
ns
4
ns
40
40
131
ns
ns
ns
ns
298
ns
53
ns
ns
20
ns
182
ns
10
___
1
Max.
90
Floating start delay time
Floating release delay time
___
Limits
Min.
20
ns
182
ns
33
ns
33
ns
0
30
ns
120
ns
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Bus timing data formulas
(VCC = 2.7 – 5.5 V, V SS = 0 V, Ta = –40 to +85 °C, f(XIN) = 12 MHz (Max.), unless otherwise noted (Note 1))
Symbol
td(An–E)
Parameter
Address output delay time
Wait mode
No wait
Wait 1
Wait 0
Address output delay time
td(A–E)
No wait
Wait 1
Wait 0
th(E–An)
Address hold time
tw(ALE)
ALE pulse width
No wait
Wait 1
Wait 0
tsu(A–ALE)
Address output setup time
No wait
Wait 1
Wait 0
th(ALE–A)
Address hold time
No wait
Wait 1
Wait 0
td(ALE–E)
td(E–DQ)
th(E–DQ)
ALE output delay time
tpxz(E–DZ)
tpzx(E–DZ)
td(BHE–E)
1 ✕ 10
2 • f(f2)
No wait
1 ✕ 109
2 • f(f2)
2 ✕ 109
2 • f(f2)
4 ✕ 109
2 • f(f2)
Wait 1
Wait 0
_
R/W output delay time
No wait
Wait 1
No wait
Wait 1
Wait 0
th(E–BHE)
th(E–R/W)
td(E–
1)
___
BHE hold time
_
R/W hold time
1
output delay time
ns
ns
ns
ns
ns
ns
– 43
ns
ns
– 43
ns
1 ✕ 109
2 • f(f2)
1 ✕ 109
2 • f(f2)
3 ✕ 109
2 • f(f2)
1 ✕ 109
2 • f(f2)
3 ✕ 109
2 • f(f2)
1 ✕ 109
2 • f(f2)
1 ✕ 109
2 • f(f2)
ns
– 43
ns
– 35
ns
– 35
ns
10
Wait 0
td(R/W–E)
ns
90
Floating release delay time
BHE output delay time
ns
ns
Floating start delay time
___
ns
4
Wait 0
Unit
9
Data hold time
E pulse width
Max.
9
1 ✕ 109
2 • f(f2)
Data output delay time
_
tw(EL)
No wait
Wait 1
Limits
Min.
1 ✕ 109
– 63
2 • f(f2)
9
3 ✕ 10
– 68
2 • f(f2)
9
1 ✕ 10
– 63
2 • f(f2)
9
3 ✕ 10
– 88
2 • f(f2)
1 ✕ 109
– 43
2 • f(f2)
1 ✕ 109
– 43
2 • f(f2)
9
2 ✕ 10
– 43
2 • f(f2)
9
1 ✕ 10
– 73
2 • f(f2)
9
2 ✕ 10
– 73
2 • f(f2)
ns
– 30
ns
– 63
ns
– 68
ns
– 63
ns
– 68
ns
– 50
ns
– 50
ns
0
30
ns
Notes 1. This applies when the main-clock division selection bit = “0”.
2. f(f2) expresses the clock f2 frequency.
For the relation to the main clock and sub clock, refer to Table 9 in data sheet “M37733MHBXXXFP”.
25
MITSUBISHI MICROCOMPUTERS
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TIMING DIAGRAM
tr
tf
tw(H)
tc
XIN
E
td(E–P4Q)
Port P4 output
tsu(P4D–E)
th(E–P4D)
Port P4 input
td(E–P5Q)
Port P5 output
tsu(P5D–E)
th(E–P5D)
Port P5 input
td(E–P6Q)
Port P6 output
tsu(P6D–E)
th(E–P6D)
Port P6 input
td(E–P7Q)
Port P7 output
tsu(P7D–E)
th(E–P7D)
Port P7 input
td(E–P8Q)
Port P8 output
tsu(P8D–E)
Port P8 input
26
th(E–P8D)
tw(L)
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tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
In event count mode
TAiOUT input
(Up-down input)
TAiIN input
(when count by falling)
TAiIN input
(when count by rising)
th(TIN–UP)
tsu(UP–TIN)
In event counter mode
(When two-phase pulse input is selected)
tc(TA)
TAjIN input
tsu(TAjIN–TAjOUT)
tsu(TAjIN–TAjOUT)
tsu(TAjOUT–TAjIN)
TAjOUT input
tsu(TAjOUT–TAjIN)
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
27
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tc(AD)
tw(ADL)
ADTRG input
tc(CK)
tw(CKH)
CLKi
tw(CKL)
th(C–Q)
TxDi
td(C–Q)
tsu(D–C)
RxDi
tw(INL)
INTi input
Kli input
28
tw(INH)
tw(KNL)
th(C–D)
MITSUBISHI MICROCOMPUTERS
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M37733S4LHP
t
duc
pro
16-BIT CMOS MICROCOMPUTER
Microprocessor mode
(When wait bit = “1”)
1
E
RDY input
tsu(RDY–
1)
th(
1–RDY)
tsu(RDY–
1)
th(
1–RDY)
(When wait bit = “0”)
1
E
RDY input
(When wait bit = “1” or “0” in common)
1
tsu(HOLD–
th(
1)
1–HOLD)
HOLD input
td(
1–HLDA)
td(
1–HLDA)
HLDA output
Test conditions
• VCC = 2.7 – 5.5 V
• Input timing voltage : VIL = 0.2VCC, VIH = 0.8VCC
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
29
MITSUBISHI MICROCOMPUTERS
M37733S4LHP
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duc
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New
16-BIT CMOS MICROCOMPUTER
Microprocessor mode
(No wait : When wait bit = “1”)
tw(L)
tw(H)
tf
tr
tc
XIN
1
td(E–
td(E–
1)
1)
tw(EL)
E
th(E–An)
td(An–E)
An
Address
tw(ALE)
Address
Address
td(ALE–E)
ALE
th(ALE–A)
th(E–DQ)
tsu(A–ALE)
Am/Dm
Address
td(A–E)
Data
tpxz(E–DZ)
tpzx(E–DZ)
Address
Address
td(E–DQ)
th(E–D)
tsu(D–E)
DmIN
Data
td(BHE–E)
th(E–BHE)
BHE
td(R/W–E)
R/W
Test conditions
• Vcc = 2.7 – 5.5 V
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
• Data input DmIN : VIL = 0.16VCC, VIH = 0.5VCC
30
th(E–R/W)
MITSUBISHI MICROCOMPUTERS
M37733S4LHP
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duc
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w
e
N
16-BIT CMOS MICROCOMPUTER
Microprocessor mode
(Wait 1 : The external memory area is accessed when wait bit = “0” and wait selection bit = “1”.)
tw(L)
tw(H)
tf tr
tc
XIN
1
td(E–
td(E–
1)
1)
tw(EL)
E
td(An–E)
th(E-An)
Address
An
tw(ALE)
Address
Address
td(ALE–E)
ALE
th(ALE–A)
th(E–DQ)
tsu(A–ALE)
Am/Dm
Address
td(A–E)
Data
tpzx(E–DZ)
tpxz(E–DZ)
Address
Address
td(E–DQ)
th(E–D)
tsu(D–E)
DmIN
Data
td(BHE–E)
th(E–BHE)
td(R/W–E)
th(E–R/W)
BHE
R/W
Test conditions
• Vcc = 2.7 – 5.5 V
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
• Data input DmIN : VIL = 0.16VCC, VIH = 0.5VCC
31
MITSUBISHI MICROCOMPUTERS
M37733S4LHP
t
duc
ro
p
New
16-BIT CMOS MICROCOMPUTER
Microprocessor mode
(Wait 0 : The external memory area is accessed when wait bit = “0” and wait selection bit = “0”.)
tw(L)
tw(H)
tf tr
tc
XIN
1
td(E–
1)
td(E–
1)
tw(EL)
E
td(An–E)
th(E–An)
Address
An
tw(ALE)
td(ALE–E)
tsu(A–ALE)
th(ALE–A)
Address
Address
ALE
Am/Dm
Address
Data
tpzx(E–DZ)
tpxz(E–DZ)
th(E–DQ)
Address
Address
td(E–DQ)
td(A–E)
tsu(D–E)
Data
DmIN
th(E–BHE)
td(BHE–E)
BHE
td(R/W–E)
R/W
Test conditions
• Vcc = 2.7 – 5.5 V
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
• Data input DmIN : VIL = 0.16VCC, VIH = 0.5VCC
32
th(E–R/W)
th(E–D)
MITSUBISHI MICROCOMPUTERS
New
t
duc
M37733S4LHP
pro
16-BIT CMOS MICROCOMPUTER
PACKAGE OUTLINE
33
MITSUBISHI MICROCOMPUTERS
New
M37733S4LHP
pro
MEMO
34
t
duc
16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
New
t
duc
M37733S4LHP
pro
16-BIT CMOS MICROCOMPUTER
MEMO
35
MITSUBISHI MICROCOMPUTERS
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duc
M37733S4LHP
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New
16-BIT CMOS MICROCOMPUTER
Keep safety first in your circuit designs!
•
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of
substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
•
These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any
intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples
contained in these materials.
All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi
Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor for the latest product information before purchasing a product listed herein.
Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact
Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for
transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.
If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the
approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
Notes regarding these materials
•
•
•
•
•
•
© 1996 MITSUBISHI ELECTRIC CORP.
H-LF434-A KI-9607 Printed in Japan (ROD)
New publication, effective Jul. 1996.
Specifications subject to change without notice.