RENESAS M37735S4BFP

To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
MITSUBISHI MICROCOMPUTERS
RY
M37735S4BFP
A
IMIN
e.
n.
atio chang
cific
o
spe bject t
l
a
fin
su
ot a its are
is n
m
This etric li
:
e
m
ic
Not e para
Som
REL
P
16-BIT CMOS MICROCOMPUTER
DESCRIPTION
●10-bit A-D converter ..............................................8-channel inputs
●12-bit watchdog timer
●Programmable input/output
(ports P4, P5, P6, P7, P8) ..............................................................37
●Clock generating circuit ........................................ 2 circuits built-in
The M37735S4BFP is a microcomputer using the 7700 Family core.
This microcomputer has a CPU and a bus interface unit. The CPU is
a 16-bit parallel processor that can be an 8-bit parallel processor,
and the bus interface unit enhances the memory access efficiency to
execute instructions fast. This microcomputer also includes a 32 kHz
oscillation circuit, in addition to the RAM, multiple-function timers,
serial I/O, A-D converter, and so on.
APPLICATION
Control devices for general commercial equipment such as office
automation, office equipment, and so on.
Control devices for general industrial equipment such as
communication equipment, and so on.
FEATURES
●Number of basic instructions .................................................. 103
●Memory size
RAM ................................................ 2048 bytes
●Instruction execution time
The fastest instruction at 25 MHz frequency ...................... 160 ns
●Single power supply ...................................................... 5 V ± 10%
●Low power dissipation (at 25 MHz frequency)
............................................ 47.5 mW (Typ.)
●Interrupts ............................................................ 19 types, 7 levels
●Multiple-function 16-bit timer ................................................. 5 + 3
●Serial I/O (UART or clock synchronous)..........................................3
42
41
43
44
45
47
46
48
49
51
50
52
54
53
56
55
58
57
59
61
60
62
64
32
P24/A4/D4
P25/A5/D5
P26/A6/D6
P27/A7/D7
P30/WEL
P31/WEH
P32/ALE
P33/HLDA
Vss
74
31
RDE
75
30
76
29
XOUT
XIN
65
40
66
39
67
38
68
37
69
36
70
35
71
34
72
33
M37735S4BFP
73
24
RDY
23
22
21
20
18
19
17
16
15
14
13
12
11
9
10
HOLD
8
25
6
80
7
CNVSS
BYTE
5
26
4
79
3
RESET
27
1
28
2
77
78
P70/AN0
P67/TB2IN/ SUB
P66/TB1IN
P65/TB0IN
P64/INT2
P63/INT1
P62/INT0
P61/TA4IN
P60/TA4OUT
P57/TA3IN/KI3/RTP13
P56/TA3OUT/KI2/RTP12
P55/TA2IN/KI1/RTP11
P54/TA2OUT/KI0/RTP10
P53/TA1IN/RTP03
P52/TA1OUT/RTP02
P51/TA0IN/RTP01
P50/TA0OUT /RTP00
P47
P46
P45
P44
P43
P42/ 1
P83/TXD0
P82/RXD0/CLKS0
P81/CLK0
P80/CTS0/RTS0/CLKS1
VCC
AVCC
VREF
AVSS
VSS
P77/AN7/XcIN
P76/AN6/XcOUT
P75/AN5/ADTRG/TXD2
P74/AN4/RXD2
P73/AN3/CLK2
P72/AN2/CTS2
P71/AN1
63
P84/CTS1/RTS1
P85/CLK1
P86/RXD1
P87/TXD1
P00/CS0
P01/CS1
P02/CS2
P03/CS3
P04/CS4
P05/RSMP
P06/A16
P07/A17
P10/A8/D8
P11/A9/D9
P12/A10/D10
P13/A11/D11
P14/A12/D12
P15/A13/D13
P16/A14/D14
P17/A15/D15
P20/A0/D0
P21/A1/D1
P22/A2/D2
P23/A3/D3
PIN CONFIGURATION (TOP VIEW)
Outline 80P6N-A
MITSUBISHI MICROCOMPUTERS
Y
NAR
M37735S4BFP
MI
I
L
E
.
.
tion hange
c
ifica
pec ject to
s
l
fina
sub
ot a its are
is n
his tric lim
T
:
me
ice
Not e para
Som
PR
CS1 CS2 CS3 CS4 RSMP
16-BIT CMOS MICROCOMPUTER
Data Bus(Odd)
Data Buffer DBH(8)
CS0
Instruction Queue Buffer Q0(8)
Instruction Queue Buffer Q1(8)
Instruction Queue Buffer Q2(8)
Address Bus
(0V)
AVSS
Incrementer(24)
Address (18)/Data (16)
AVCC
Instruction Register(8)
Data Buffer DBL(8)
Address bus/Data bus
Reference
External data bus width
voltage input
selection input
VREF
BYTE
Data Bus(Even)
RDY HOLD HLDA ALE WEH WEL RDE
Program Address Register PA(24)
A-D Converter(10)
CNVss
Data Address Register DA(24)
Incrementer/Decrementer(24)
(0V)
VSS
Program Counter PC(16)
Program Bank Register PG(8)
2
P4(5)
Input/Output
port P4
Input/Output
port P5
Input/Output
port P6
Timer TB0(16)
Timer TA0(16)
P5(8)
Timer TB1(16)
P6(8)
Timer TB2(16)
Timer TA1(16)
UART1(9)
Watchdog Timer
XCOUT
XCIN
Index Register X(16)
Accumulatcr B(16)
Input/Output
port P7
P7(8)
Input/Output
port P8
XCOUT
XCIN
P8(8)
Arithmetic Logic
Unit(16)
2048 bytes
RAM
Clock Generating Circuit
Accumulator A(16)
Clock input Clock output
XIN
XOUT
M37735S4BFP BLOCK DIAGRAM
Index Register Y(16)
Timer TA4(16)
Stack Pointer S(16)
Timer TA2(16)
Direct Page Register DPR(16)
RESET
Reset input
Processor Status Register PS(11)
Timer TA3(16)
Input Butter Register IB(16)
UART0(9)
UART2(9 )
VCC
1
Data Bank Register DT(8)
MITSUBISHI MICROCOMPUTERS
Y
NAR
I
ge.
ion.
icat to chan
ecif
l sp ubject
a
in
af
es
not mits ar
li
is is
: Th metric
e
ic
Not e para
Som
IM
REL
M37735S4BFP
P
16-BIT CMOS MICROCOMPUTER
FUNCTIONS OF M37735S4BFP
Parameter
Number of basic instructions
Instruction execution time
Memory size
Input/Output ports
Multi-function timers
RAM
P5 – P8
P4
TA0, TA1, TA2, TA3, TA4
TB0, TB1, TB2
Serial I/O
A-D converter
Watchdog timer
Interrupts
Clock generating circuit
Supply voltage
Power dissipation
Input/Output characteristic
Memory expansion
Operating temperature range
Device structure
Package
Input/Output voltage
Output current
Functions
103
160ns (the fastest instruction at external clock 25 MHz frequency)
2048 bytes
8-bit ✕ 4
5-bit ✕ 1
16-bit ✕ 5
16-bit ✕ 3
(UART or clock synchronous serial I/O) ✕ 3
10-bit ✕ 1 (8 channels)
12-bit ✕ 1
3 external types, 16 internal types
Each interrupt can be set to the priority level (0 – 7.)
2 circuits built-in (externally connected to a ceramic resonator or a
quartz-crystal oscillator)
5 V ± 10%
47.5 mW (at external clock 25 MHz frequency)
5V
5 mA
Maximum 1 Mbytes
–20 to 85 °C
CMOS high-performance silicon gate process
80-pin plastic molded QFP (80P6N-A)
3
MITSUBISHI MICROCOMPUTERS
Y
NAR
M37735S4BFP
MI
I
L
E
.
.
tion hange
c
ifica
pec ject to
s
l
fina
sub
ot a its are
is n
his tric lim
T
:
me
ice
Not e para
Som
PR
16-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION
Pin
Vcc,
Vss
CNVss
_____
Name
Input/Output
Power source
Apply 5 V ± 10% to Vcc and 0 V to Vss.
RESET
CNVss input
Reset input
XIN
Clock input
XOUT
Clock output
Read enable output
Bus width
selection input
____
RDE
BYTE
AVcc,
AVss
VREF
Analog power
source input
Reference
voltage input
____
P00/____
CS 0 – Chip selection
P04/CS
4
output
_____
P05/RSMP Ready sampling
output
P06/A16,
Address output
P07/A17
P10/A8/D8 – Address output
P17/A15/D15 /data (high
-order) I/O
P20/A0/D0 – Address output
P27/A7/D7
/data (low
-order) I/O
____
P30/WEL
Write enable
output
Input
Input
Input
Output
Output
Input
Input
____
The timing signal to be input to the RDY pin is output.
Output
An address (A16, A17) is output.
____
I/O
I/O
Output
RDY
P42/ 1
P43 – P47
Clock output
I/O port P4
Output
I/O
P50 – P57
I/O port P5
I/O
P60 – P67
I/O port P6
I/O
P70 – P77
I/O port P7
I/O
P80 – P87
I/O port P8
I/O
_____
HOLD
____
4
When the BYTE pin is set to “L” and external data bus has a 16-bit width, high-order data
(D8 – D15 ) is input/output or an address (A8 – A15) is output. When the BYTE pin is “H” and an
external data bus has an 8-bit width, only address (A8 – A15 ) is output.
Low-order data (D0 – D 7) is input/output or an address (A0 – A 7) is output.
____
Output
Hold acknowledge output
Hold request
input
Ready input
_____
____
Output
Output
P33/HLDA
This is reference voltage input pin for the A-D converter.
When the specified external memory area is accessed, CS0 – CS 4 signals are “L”.
Write enable
high output
Address latch
enable output
P32/ALE
Connect to Vcc.
When “L” level is applied to this pin, the microcomputer enters the reset state.
These are pins of main-clock generating circuit. Connect a ceramic resonator or a quartz-crystal
oscillator between XIN and XOUT. When an external clock is used, the clock source should be
connected to the XIN pin, and the XOUT pin should be left____
open.
When data/instruction read is performed, output level of RDE signal is “L”.
This pin determines whether the external data bus has an 8-bit width or a 16-bit width.
The data bus has a 16-bit width when “L” signal is input and an 8-bit width when “H” signal
is input.
Power source input pin for the A-D converter. Externally connect AVcc to Vcc and AVss to Vss.
Output
____
P31/WEH
Functions
Output
When the BYTE pin is “L” and writing to an even address is performed, output level of WEL signal
is “L”. When the
BYTE pin is “H” and writing to an even address or an odd address is performed,
____
output level of WEL signal is “L”.
____
When the BYTE pin is “L” and writing
to an odd address is performed, output level of WEH signal
____
is “L”. When the BYTE pin is “H”, WEH signal is always “H”.
This is used to retrieve only the address from the multiplex signal which consists of address and
data.
This outputs “L” level when the microcomputer enters hold state after a hold request is accepted.
_____
Input
Input
This is an input pin for HOLD request signal. The microcomputer enters hold state while this
signal is “L”.
____
This is an input pin for RDY signal. The microcomputer enters ready state while this signal is “L”.
This pin outputs the clock 1.
These pins become a 5-bit I/O port. An I/O direction register is available so that each pin can be
programmed for input or output. These ports are in the input mode when reset.
In addition to having the same functions as port P4, ___
these___
pins also function as I/O pins for timers
A0 to A3 and input pins for key input interrupt input (KI0 – KI3).
In addition to having the same functions as
port ____
P4, these pins also function as I/O pins for timer
____
A4, input pins for external interrupt input (INT0 – INT2) and input pins for timers B0 to B2. P67 also
functions as sub-clock SUB output pin.
In addition to having the same functions as port P4, these pins function as input pins for A-D
converter. P72 to P75 also function as I/O pins for UART2. Additionally, P76 and P77 have the
function as the output pin (XCOUT) and the input pin (XCIN) of the sub-clock (32 kHz) oscillation
circuit, respectively. When P76 and P77 are used as the XCOUT and XCIN pins, connect a resonator
or an oscillator between the both.
In addition to having the same functions as port P4, these pins also function as I/O pins for UART
0 and UART 1.
MITSUBISHI MICROCOMPUTERS
Y
NAR
M37735S4BFP
I
ge.
ion.
icat to chan
ecif
l sp ubject
a
in
af
es
not mits ar
li
is is
: Th metric
e
ic
Not e para
Som
IM
REL
P
16-BIT CMOS MICROCOMPUTER
BASIC FUNCTION BLOCKS
The M37735S4BFP has the same functions as the
M37735MHBXXXFP except for the following:
(1) The memory map is different.
(2) The processor mode is different.
(3) The reset circuit is different.
(4) Pulse output port mode of timer A is available.
(5) The function of ROM area modification is not available.
Refer to the section on the M37735MHBXXXFP, except for above
(1)–(5).
MEMORY
The memory map is shown in Figure 1. The address space has a
capacity of 16 Mbytes and is allocated to addresses from 016 to
FFFFFF16. The address space is divided by 64-Kbyte unit called bank.
The banks are numbered from 016 to FF16.
However, banks 10 16–FF 16 of the M37735S4BFP cannot be
accessed.
00000016
Built-in RAM and control registers for internal peripheral devices are
assigned to bank 016.
Addresses FFD616 to FFFF 16 are the RESET and interrupt vector
addresses and contain the interrupt vectors. Use ROM for memory
of this address.
The 2048-byte area allocated to addresses from 8016 to 87F16 is the
built-in RAM. In addition to storing data, the RAM is used as stack
during a subroutine call or interrupts.
Peripheral devices such as I/O ports, A-D converter, serial I/O, timer,
and interrupt control registers are allocated to addresses from 016 to
7F16 .
A 256-byte direct page area can be allocated anywhere in bank 016
by using the direct page register (DPR). In the direct page addressing
mode, the memory in the direct page area can be accessed with two
words. Hence program steps can be reduced.
00000016
00007F16
00008016
00000016
Internal peripheral
devices
control registers
Bank 016
refer to Fig. 2 for
detail information
00FFFF16
01000016
Internal RAM
2048 bytes
00007F16
Bank 116
Interrupt vector table
00FFD616
01FFFF16
00087F16
A-D/UART2 trans./rece.
UART1 transmission
UART1 receive
•••••••••••••••••••
UART0 transmission
UART0 receive
Timer B2
Timer B1
Timer B0
Timer A4
Timer A3
Timer A2
FE000016
Timer A1
Timer A0
Bank FE16
INT2/Key input
INT1
INT0
FEFFFF16
FF000016
Watchdog timer
DBC
Bank FF16
00FFD616
BRK instruction
Zero divide
FFFFFF16
00FFFF16
00FFFE16
RESET
: Internal
: External
Note. Banks 1016–FF16 cannot be accessed in the M37735S4BFP.
Fig. 1 Memory map
5
MITSUBISHI MICROCOMPUTERS
Y
NAR
M37735S4BFP
MI
I
L
E
.
.
tion hange
c
ifica
pec ject to
s
l
fina
sub
ot a its are
is n
his tric lim
T
:
me
ice
Not e para
Som
PR
Address (Hexadecimal notation)
000000
000001
000002 Port P0 register
000003 Port P1 register
000004 Port P0 direction register
000005 Port P1 direction register
000006 Port P2 register
000007 Port P3 register
000008 Port P2 direction register
000009 Port P3 direction register
00000A Port P4 register
00000B Port P5 register
00000C Port P4 direction register
00000D Port P5 direction register
00000E Port P6 register
00000F Port P7 register
000010 Port P6 direction register
000011 Port P7 direction register
000012 Port P8 register
000013
000014 Port P8 direction register
000015
000016
000017
000018
000019
00001A
00001B
00001C Pulse output data register 1
00001D Pulse output data register 0
00001E A-D control register 0
00001F A-D control register 1
000020
A-D register 0
000021
000022
A-D register 1
000023
000024
A-D register 2
000025
000026
A-D register 3
000027
000028
A-D register 4
000029
00002A
A-D register 5
00002B
00002C
A-D register 6
00002D
00002E
A-D register 7
00002F
000030 UART 0 transmit/receive mode register
000031 UART 0 baud rate register (BRG0)
000032 UART 0 transmission buffer register
000033
000034 UART 0 transmit/receive control register 0
000035 UART 0 transmit/receive control register 1
000036
UART 0 receive buffer register
000037
000038 UART 1 transmit/receive mode register
000039 UART 1 baud rate register (BRG1)
00003A
UART 1 transmission buffer register
00003B
00003C UART 1 transmit/receive control register 0
00003D UART 1 transmit/receive control register 1
00003E
UART 1 receive buffer register
00003F
16-BIT CMOS MICROCOMPUTER
Address (Hexadecimal notation)
000040
000041
000042
000043
000044
000045
000046
000047
000048
000049
00004A
00004B
00004C
00004D
00004E
00004F
000050
000051
000052
000053
000054
000055
000056
000057
000058
000059
00005A
00005B
00005C
00005D
00005E
00005F
000060
000061
000062
000063
000064
000065
000066
000067
000068
000069
00006A
00006B
00006C
00006D
00006E
00006F
000070
000071
000072
000073
000074
000075
000076
000077
000078
000079
00007A
00007B
00007C
00007D
00007E
00007F
Count start flag
One-shot start flag
Up-down flag
Timer A0 register
Timer A1 register
Timer A2 register
Timer A3 register
Timer A4 register
Timer B0 register
Timer B1 register
Timer B2 register
Timer A0 mode register
Timer A1 mode register
Timer A2 mode register
Timer A3 mode register
Timer A4 mode register
Timer B0 mode register
Timer B1 mode register
Timer B2 mode register
Processor mode register 0
Processor mode register 1
Watchdog timer register
Watchdog timer frequency selection flag
Waveform output mode register
Reserved area (Note)
UART2 transmit/receive mode register
UART2 baud rate register (BRG2)
UART2 transmission buffer register
UART2 transmit/receive control register 0
UART2 transmit/receive control register 1
UART2 receive buffer register
Oscillation circuit control register 0
Port function control register
Serial transmit control register
Oscillation circuit control register 1
A-D/UART2 trans./rece. interrupt control register
UART 0 transmission interrupt control register
UART 0 receive interrupt control register
UART 1 transmission interrupt control register
UART 1 receive interrupt control register
Timer A0 interrupt control register
Timer A1 interrupt control register
Timer A2 interrupt control register
Timer A3 interrupt control register
Timer A4 interrupt control register
Timer B0 interrupt control register
Timer B1 interrupt control register
Timer B2 interrupt control register
INT0 interrupt control register
INT1 interrupt control register
INT2/Key input interrupt control register
Note. Writing to reserved area is disabled.
Fig. 2 Location of internal peripheral devices and interrupt control registers
6
MITSUBISHI MICROCOMPUTERS
Y
NAR
M37735S4BFP
I
ge.
ion.
icat to chan
ecif
l sp ubject
a
in
af
es
not mits ar
li
is is
: Th metric
e
ic
Not e para
Som
IM
REL
P
16-BIT CMOS MICROCOMPUTER
Pulse output port mode
The pulse motor drive waveform can be output by using plural internal
timer A.
Figure 3 shows a block diagram for pulse output port mode. In the
pulse output port mode, two pairs of four-bit pulse output ports are
used. Whether using pulse output port or not can be selected by
waveform output selection bit (bit 0, bit 1) of waveform output mode
register (6216 address) shown in Figure 4. When bit 0 of waveform
output selection bit is set to “1”, RTP10, RTP11, RTP12 , and RTP13
are used as pulse output ports, and when bit 1 of waveform output
selection bit is set to “1”, RTP0 0, RTP0 1, RTP0 2, and RTP03 are
used as pulse output ports. When bits 1 and 0 of waveform output
selection bit are set to“1”, RTP1 0, RTP11, RTP12 , and RTP13, and
RTP00, RTP01, RTP02, and RTP03 are used as pulse output ports.
The ports not used as pulse output ports can be used as normal
parallel ports, timer input/output or key input interruput input.
In the pulse output port mode, set timers A0 and A2 to timer mode as
timers A0 and A2 are used. Figure 5 shows the bit configuration of
timer A0, A2 mode registers in pulse output port mode.
Data can be set in each bit of the pulse output data register
corresponding to four ports selected as pulse output ports. Figure 6
4
shows the bit configuration of the pulse output data register. The
contents of the pulse output data register 1 (low-order four bits of
1C16 address) corresponding to RTP10, RTP1 1, RTP12 , and RTP13
is output to the ports each time the counter of timer A2 becomes
000016. The contents of the pulse output data register 0 (low-order
four bits of 1D16 address) corresponding to RTP00, RTP01, RTP02 ,
and RTP03 is output to the ports each time the counter of timer A0
becomes 000016.
Figure 7 shows example of waveforms in pulse output port mode.
When “0” is written to a specified bit of the pulse output data register,“L”
level is output to the corresponding pulse output port when the counter
of corresponding timer becomes 000016, and when “1” is written, “H”
level is output to the pulse output port.
Pulse width modulation can be applied to each pulse output port.
Since pulse width modulation involves the use of timers A1 and A3,
activate these timers in pulse width modulation mode.
5
Pulse width modulation selection bit
(Bit 4, 5 of 6216 address)
Pulse width modulation output
by timer A3
Pulse width modulation output
by timer A1
Timer A2
Data bus (odd)
Data bus (even)
Pulse output data
register 1 (1C16 address)
D3
D T Q
RTP13 (P57)
D2
D
Q
RTP12 (P56)
D1
D
Q
RTP11 (P55)
D0
D
Q
D11
D
Q
RTP03 (P53)
D10
D
Q
RTP02 (P52)
D9
D
Q
RTP01 (P51)
D8
D
Q
RTP00 (P50)
T
RTP10 (P54)
Pulse output data
register 0 (1D16 address)
Timer A0
Polarity selection bit
(Bit 3 of 6216 address)
Fig. 3 Block diagram for pulse output port mode
7
Y
NAR
MITSUBISHI MICROCOMPUTERS
M37735S4BFP
I
ge.
ion.
icat to chan
ecif
l sp ubject
a
in
af
es
not mits ar
li
is is
: Th metric
e
ic
Not e para
Som
IM
REL
P
RTP10, RTP11, RTP12, and RTP13 are applied pulse width modulation
by timer A3 by setting the pulse width modulation selection bit by
timer A3 (bit 5) of the waveform output mode register to “1”.
RTP00, RTP01, RTP02, and RTP03 are applied pulse width modulation
by timer A1 by setting the pulse width modulation selection bit by
timer A1 (bit 4) of the waveform output mode register to “1”.
The contents of the pulse output data register 0 can be reversed and
output to pulse output ports RTP00 , RTP01, RTP0 2, and RTP03 by
the polarity selection bit (bit 3) of the waveform output mode register.
When the polarity selection bit is “0”, the contents of the pulse output
data register 0 is output unchangeably, and when “1”, the contents of
the pulse output data register 0 is reversed and output. When pulse
width modulation is applied, likewise the polarity reverse to pulse
width modulation can be selected by the polarity selection bit.
7 6 5 4 3 2 1 0
0
16-BIT CMOS MICROCOMPUTER
7 6 5 4 3 2 1 0
0 0 X 1 0 0
Address
Timer A0 mode register 5616
Timer A2 mode register 5816
Always “100” in pulse output
port mode
Not used in pulse output port mode
Always “00” in pulse output port mode
Clock source selection bit
0 0 : Select f2
0 1 : Select f16
1 0 : Select f64
1 1 : Select f512
Fig. 5 Timer A0, A2 mode register bit configuration in pulse output
port mode
Address
Weveform output mode register 6216
Weveform output selection bit
0 0 : Parallel port
0 1 : RTP1 selected
1 0 : RTP0 selected
1 1 : RTP1 and RTP0 selected
7 6 5 4 3 2 1 0
Polarity selection bit
0 : Positive polarity
1 : Negative polarity
Pulse width modulation selection bit
by timer A1
0 : Not modulated
1 : Modulated
Pulse width modulation selection bit
by timer A3
0 : Not modulated
1 : Modulated
Always “0”
Address
Pulse output data register 0 1D16
RTP00 output data
RTP01 output data
RTP02 output data
RTP03 output data
7 6 5 4 3 2 1 0
Address
Pulse output data register 1 1C16
RTP10 output data
Fig. 4 Waveform output mode register bit configuration
RTP11 output data
RTP12 output data
RTP13 output data
Fig. 6 Pulse output data register bit configuration
8
MITSUBISHI MICROCOMPUTERS
Y
NAR
M37735S4BFP
I
ge.
ion.
icat to chan
ecif
l sp ubject
a
in
af
es
not mits ar
li
is is
: Th metric
e
ic
Not e para
Som
IM
REL
P
16-BIT CMOS MICROCOMPUTER
Example of pulse output port (RTP10 – RTP13)
Output signal at each time
when timer A2 becomes 000016
RTP13(P57)
RTP12(P56)
RTP11(P55)
RTP10(P54)
Example of pulse output port (RTP10 – RTP13) when pulse width modulation is applied by timer A3.
Output signal at each time
when timer A2 becomes 000016
RTP13(P57)
RTP12(P56)
RTP11(P55)
RTP10(P54)
Example of pulse output port (RTP00 – RTP03) when pulse width modulation is applied
by timer A1 with polarity selection bit = “1”.
Output signal at each time
when timer A0 becomes 000016
RTP03(P53)
RTP02(P52)
RTP01(P51)
RTP00(P50)
Fig. 7 Example of waveforms in pulse output port mode
9
MITSUBISHI MICROCOMPUTERS
Y
NAR
M37735S4BFP
MI
I
L
E
.
.
tion hange
c
ifica
pec ject to
s
l
fina
sub
ot a its are
is n
his tric lim
T
:
me
ice
Not e para
Som
PR
16-BIT CMOS MICROCOMPUTER
PROCESSOR MODE
Only the microprocessor mode can be selected. ___
Figure 9 shows the functions of pins P0 0 / CS 0 — P47 in the
microprocessor mode.
Figure 10 shows external memory area for the microprocessor mode.
Access to the external memory is affected by the BYTE pin, the wait
bit (bit 2 of the processor mode register 0 at address 5E16 ), and the
wait selection bit (bit 0 of the processor mode register 1 at address
5F16) .
7 6 5 4 3 2 1 0
0
1 0
Processor mode register 0
Address
5E16
• BYTE pin
When accessing the external memory, the level of the BYTE pin is
used to determine whether to use the data bus as 8-bit width or 16bit width.
The data bus has a width of 8 bits when level of the BYTE pin is “H”,
and pins P20/A0/D0 — P27/A 7/D7 are the data I/O pins.
The data bus has a width of 16 bits when the level of the BYTE pin is
“L”, and pins P20/A0/D0 — P27/A7/D7 and pins P10/A8/D8 — P17/A15 /
D15 are the data I/O pins.
When accessing the internal memory, the data bus always has a
width of 16 bits regardless of the BYTE pin level.
7 6 5 4 3 2 1 0
Processor mode register 1
Wait selection bit
0 : Wait 0
1 : Wait 1
Must be “10” (“10” after reset)
Wait bit
0 : Wait
1 : No wait
Software reset bit
Reset occurs when this bit is set to “1”
Interrupt priority detection time selection bit
0 0 : Internal clock ✕ 7 (cycle)
✕ 4 (cycle)
0 1 : Internal clock
1 0 : Internal clock ✕ 2 (cycle)
Must be “0”
Not used
Fig. 8 Processor mode register bit configuration
10
Address
5F16
MITSUBISHI MICROCOMPUTERS
Y
NAR
M37735S4BFP
MI
I
L
E
.
.
tion hange
c
ifica
pec ject to
s
l
fina
sub
ot a its are
is n
his tric lim
T
:
me
ice
Not e para
Som
PR
16-BIT CMOS MICROCOMPUTER
PM1
1
PM0
0
Mode
Microprocessor mode
Pin
RDE
RDE
(Note)
RDE, WEL, WEH
P00/CS0
CS0 to CS4
to
P04/CS4
P05/RSMP
P06/A16
P07/A17
RSMP, A16, A17
CS0 — CS4
RSMP
Address A16, A17
RDE, WEL, WEH
P10/A8/D8
to
P17/A15 /D15
BYTE = “L”
P10/A8/D8
to
P17/A15/D15
RDE, WEL, WEH
P10/A8/D8
to
P17/A15/D15
BYTE = “H”
RDE, WEL, WEH
P20/A0/D0
to
P27/A7/D7
BYTE = “L”
P20/A0/D0
to
P27/A7/D7
A8 to A15
Address
Data(odd)
Address A8 – A15
A0 to A7
Address
Data(even)
RDE, WEL, WEH
BYTE = “H”
P20/A0/D0
to
P27/A7/D7
P30/WEL,
P31/WEH,
P32/ALE,
P33/HLDA
A0 to A7
Address
Data
(odd,even)
P30/WEL
WEL
(Note)
P31/WEH
WEH
(Note)
P32/ALE
ALE
P33/HLDA
HLDA
RDE, WEL, WEH
HOLD,
RDY,
P42/ 1,
HOLD
HOLD
RDY
RDY
P42/
(Note)
1
Ports P43 to P47
P43
to
P47
I/O Port
___
Fig. 9 Functions of pins P00/CS0 to P47 in microprocessor mode
Note. The signal output disable selection bit (bit 6 of the oscillation circuit control register 0) can stop the
1 output in the microprocessor
___ ___ ___
mode. In this mode, signals RDE, WEL, WEH can also be fixed to “H” when the internal memory area is accessed.
11
MITSUBISHI MICROCOMPUTERS
Y
NAR
M37735S4BFP
MI
I
L
E
.
.
tion hange
c
ifica
pec ject to
s
l
fina
sub
ot a its are
is n
his tric lim
T
:
me
ice
Not e para
Som
PR
16-BIT CMOS MICROCOMPUTER
• Wait bit
As shown in Figure 11, when the external memory area is accessed
with the wait bit (bit 2 of the processor mode register 0 at address
5E16 ) cleared to “0”, the access time can be extended compared with
no wait (the wait bit is “1”).
The access time is extended in two ways and this is selected with the
wait selection bit (bit 0 of the processor mode register 1 at address
5F16).
When this bit is “1”, the access time is 1.5 times compared to that for
no wait. When this bit is “0”, the access time is twice compared to
that for no wait.
At reset, the wait bit and the wait selection bit are “0”.
Access to internal memory area is always performed in the no wait
mode regardless of the wait bit.
The processor modes are described below.
Internal clock
Ai/Di
Wait bit “1”
(No wait)
0016
SFR
Access time
Ai/Di
Wait bit “0”
(Wait 1)
Address
Data
Address
Data
RDE or
WEL, WEH
ALE
Access time
Wait bit “0”
(Wait 0)
Address
Data
Address
RDE or
WEL, WEH
ALE
Access time
Fig. 11 Relationship between wait bit, wait selection bit, and access time
8016
RAM
87F16
The shaded area is the external memory area.
Note that banks 1016 to FF16 cannot be accessed.
Fig. 10 External memory area for microprocessor mode
12
Data Address Data
ALE
Ai/Di
Microprocessor
mode
Address
RDE or
WEL, WEH
(1) Microprocessor mode [10]
The microcomputer enters the microprocessor mode after connecting
the CNVss pin to Vcc and starting from reset.
___
___
Pin RDE is the output pin for the read enable signal (RDE).
___
RDE is “L” during the data read term in the read cycle. When the
___
internal memory area is read, RDE can be fixed to “H” by setting the
signal output disabe selection bit (bit 6 of the oscillation circuit control
register 0) to “1”.
MITSUBISHI MICROCOMPUTERS
Y
NAR
M37735S4BFP
MI
I
L
E
.
.
tion hange
c
ifica
pec ject to
s
l
fina
sub
ot a its are
is n
his tric lim
T
:
me
ice
Not e para
Som
PR
___
___
CS 0 to CS4 are the chip select signals and are “L” when the address
____
shown in Table 2 is accessed. RSMP is the ready-sampling signal
___
which is output for the RDY input described later when the external
____
memory area is accessed. By inputting logical AND of RSMP and
___
____
CSn (n = 0 to 4) to the RDY pin, read/write term for any address areas
can be extended by 1 cycle of clock
1. In addition, the read/write
term can also be extended by 2 cycles of clock
1 if the above
function and wait 0/1 function specified with the wait bit are used
together.
Pins P10/A8/D8 — P17/A15/D15 have two functions depending on the
level of the BYTE pin.
When the BYTE pin level is “L”, pins P10/A8/D8 — P17/A15/D15 function
___
___ ___
as address (A8 to A15 ) output pins while RDE or WEL, WEH are “H”
and as odd address data I/O pins while these signals are “L”. However,
___
if an internal memory is read, external data is ignored while RDE is
“L”.
When the BYTE pin level is “H”, pins P10/A8/D8 — P17/A15/D15 function
as address (A8 to A15 ) output pins.
Pins P20/A0/D0 — P27/A7/D 7 have two functions depending on the
level of the BYTE pin.
When the BYTE pin level is “L”, pins P20/A0/D0 — P27/A7/D7 function
___
___ ___
as address (A0 to A7) output pins while RDE or WEL, WEH are “H” and
as even address data I/O pins while these signals are “L”. However,
___
if an internal memory is read, external data is ignored while RDE is
“L”.
When the BYTE pin level is “H”, pins P20/A0/D0 — P27/A7/D7 function
___
___ ___
as address (A0 to A7) output pins while RDE or WEL, WEH are “H” and
as even and odd address data I/O pins while these signals are “L”.
However, if an internal memory is read, external data is ignored while
___
RDE is “L”.
___ ___
WEL, WEH are the write-enable low signal and the write-enable high
signal, respectively. These signals are “L” during the data write term
of the write cycle, but their operations differ depending on the BYTE
pin level.
___
In the case the BYTE pin level is “L”, WEL is “L” when writing to
___
an even address, WEH is “L” when writing to an odd address, and
___
___
both WEL and WEH are “L” when writing to even and odd addresses.
In the case the BYTE pin level is “H”, regardless of address, only
___
___
___
___
WEL is “L”, and WEH retains “H”. WEL and WEH can also be fixed to
___
“H” when the internal memory is accessed, same as RDE, by writing
“1” to the signal output disable selection bit.
ALE is an address latch enable signal used to latch the address signal
from a multiplexed signal of address and data. The latch is transparent
while ALE is “H” to let the address signal pass through and held
while ALE is “L”.
____
HLDA is a hold acknowledge signal and is used to notify externally
____
when the microcomputer receives HOLD input and enters into hold
state.
____
HOLD is a hold request signal. It is an input signal used to put the
____
microcomputer in hold state. HOLD input is accepted when the internal
clock
falls from “H” level to “L” level while the bus is not used.
___
____
___
Pins P00/ CS0 — P31/WEH and RDE are floating while the microcomputer
____
stays in hold state. After HLDA signal changes to “L” level and one
cycle of internal clock
passed, these ports become floating. After
____
HLDA signal changes to “H” level and one cycle of internal clock
passed, these ports are released from floating state.
16-BIT CMOS MICROCOMPUTER
___
RDY is a ready signal. If this signal goes “L”, the internal clock
___
stops at “L”. RDY is used when slow external memory is attached.
P42 /
1 pin is an output pin for clock
1. The
1 output is
___
independent of RDY and does not___
stop even when internal clock
stops because of “L” input to the RDY pin.
13
MITSUBISHI MICROCOMPUTERS
Y
NAR
M37735S4BFP
MI
I
L
E
.
.
tion hange
c
ifica
pec ject to
s
l
fina
sub
ot a its are
is n
his tric lim
T
:
me
ice
Not e para
Som
PR
16-BIT CMOS MICROCOMPUTER
As shown in Table 3,
1 output can be stopped with the signal
output disable selection bit = “1”. In this case, write “1” to the port P4 2
direction register.
Table 1 shows the relationship between the CNVss pin input level
and the processor mode.
Table 1. Relationship between CNVss pin input levels and processor
mode
CNVss
Mode
Description
• Microprocessor
Microprocessor mode upon
Vcc
starting after reset.
Table 2. Relationship between access addresses and chip-select signals CS0 to CS 4
Chip-select
signal
____
CS 0
____
CS 1
____
CS 2
____
CS 3
____
CS 4
Access address
Area
Microprocessor mode
00 088016
to
00 7FFF16
00 800016
to
03 FFFF16
04 000016
to
07 FFFF16
08 000016
to
0B FFFF16
0C 000016
to
0F FFFF16
The first half of bank 0016 except
internal memory area
The latter half of bank 0016 except
internal memory area and banks
0116 to 0316.
Banks 0416 to 0716
Banks 0816 to 0B16
Banks 0C16 to 0F16
Table 3. Function of signal output disable selection bit CM6 (bit 6 of oscillation circuit control register 0)
Processor mode
Function
Pin
CM6 = “0”
___
___ ___
RDE,
WEL, WEH
internal/external memory area is accessed.
___
___
RDE, WEL, WEH are output when the
___ ___
___
CM6 = “1”
RDE, WEL, WEH are output only when the
external memory area is accessed.
“L” is output after WIT/STP instruction is
___
executed
After WIT/STP instruction is executed,
RDE
∗ Standby state selection bit (bit 0 of port
“H”
is
output.
Microprocessor mode
function control register) must be set to “1”.
“H” or “L” is output. (Contents of P42 port
latch is output.)
Clock
1 is output independent of
1
1
∗ Port P42 direction register must be set to
output selection bit.
“1”.
Note. Functions shown in Table 3 cannot be emulated with a debugger. For the oscillation circuit control register 0 and port function control
register, refer to Figures 64 and 11 in data sheet “M37735MHBXXXFP”, respectively.
14
MITSUBISHI MICROCOMPUTERS
Y
NAR
M37735S4BFP
MI
I
L
E
.
.
tion hange
c
ifica
pec ject to
s
l
fina
sub
ot a its are
is n
his tric lim
T
:
me
ice
Not e para
Som
PR
16-BIT CMOS MICROCOMPUTER
RESET CIRCUIT
_____
The microcomputer is released from the reset state when the RESET
pin is returned to “H” level after holding it at “L” level with the power
source voltage at 5 V ± 10%. Program execution starts at the address
formed by setting address A23 – A16 to 0016, A15 – A8 to the contents
of address FFFF16 , and A7 – A0 to the contents of address FFFE16.
Figure 13 shows an example of a reset circuit. If the stabilized clock
is input from the external to the main-clock oscillation circuit, the reset
input voltage must be 0.9 V or less when the power source voltage
reaches 4.5 V. If a resonator/oscillator is connected to the main-clock
oscillation circuit, change the reset input voltage from “L” to “H” after
the main-clock oscillation is fully stabilized.
Figure 12 shows the status of the internal registers during reset.
Address
Address
Port P0 direction register
(0416)•••
0016
Watchdog timer frequency selection flag
(6116)•••
Port P1 direction register
(0516)•••
0016
Waveform output mode register
(6216)••• 0
Port P2 direction register
(0816)•••
0016
UART2 transmit/receive mode register
(6416)•••
0 0 0 0 0 0 0
Port P3 direction register
(0916)•••
UART2 transmit/receive control register 0
(6816)•••
1 0 0 0
Port P4 direction register
(0C16)•••
0016
UART2 transmit/receive control register 1
(6916)••• 0 0 0 0 0 0 1 0
Port P5 direction register
(0D16)•••
0016
Oscillation circuit control register 0
(6C16)•••
Port P6 direction register
(1016)•••
0016
Port function control register
(6D16)•••
0 0 0 0
Port P7 direction register
(1116)•••
0016
Serial transmit control register
(6E16)•••
Port P8 direction register
(1416)•••
0016
Oscillation circuit control register 1
(6F16)••• 0
A-D control register 0
(1E16)••• 0 0 0 0 0 ? ? ?
A-D control register 1
(1F16)•••
0 0 0
UART 0 transmit/receive mode register
(3016)•••
UART 1 transmit/receive mode register
(3816)•••
UART 0 transmit/receive
control register 0
UART 1 transmit/receive
control register 0
UART 0 transmit/receive
control register 1
UART 1 transmit/receive
control register 1
Count start flag
0
0 0 0
0 0
0 0 0 0 0
1
0016
0 0
0 0 0 0 0
A-D/UART2 trans./rece. interrupt control register (7016)•••
0 0 0 0
UART 0 transmission interrupt control register
(7116)•••
0 0 0 0
0016
UART 0 receive interruupt control register
(7216)•••
0 0 0 0
0016
UART 1 transmission interrupt control register
(7316)•••
0 0 0 0
(3416)••• 0 0 0 0 1 0 0 0
UART 1 receive interruupt control register
(7416)•••
0 0 0 0
(3C16)••• 0 0 0 0 1 0 0 0
Timer A0 interrupt control register
(7516)•••
0 0 0 0
(3516)••• 0 0 0 0 0 0 1 0
Timer A1 interrupt control register
(7616)•••
0 0 0 0
(3D16)••• 0 0 0 0 0 0 1 0
Timer A2 interrupt control register
(7716)•••
0 0 0 0
(4016)•••
0016
Timer A3 interrupt control register
(7816)•••
0 0 0 0
One- shot start flag
(4216)•••
0 0 0 0 0
Timer A4 interrupt control register
(7916)•••
0 0 0 0
Up-down flag
(4416)•••
0016
Timer B0 interrupt control register
(7A16)•••
0 0 0 0
Timer A0 mode register
(5616)•••
0016
Timer B1 interrupt control register
(7B16)•••
0 0 0 0
Timer A1 mode register
(5716)•••
0016
Timer B2 interrupt control register
(7C16)•••
0 0 0 0
Timer A2 mode register
(5816)•••
0016
INT0 interrupt control register
(7D16)•••
0 0 0 0 0 0
Timer A3 mode register
(5916)•••
0016
INT1 interrupt control register
(7E16)•••
0 0 0 0 0 0
Timer A4 mode register
(5A16)•••
0016
INT2/key input interrupt control register
(7F16)•••
0 0 0 0
Timer B0 mode register
(5B16)••• 0 0 1 0 0 0 0 0
Processor status register (PS)
0 0 0 ? ? 0 0 0 1 ? ?
Timer B1 mode register
(5C16)••• 0 0 1
0 0 0 0
Program bank register (PG)
Timer B2 mode register
(5D16)••• 0 0 1
0 0 0 0
Program counter (PCH)
Content of FFFF16
Processor mode register 0
(5E16)•••
Program counter (PCL)
Content of FFFE16
Processor mode register 1
(5F16)•••
Watchdog timer register
(6016)•••
1 1
0016
0
FFF16
Direct page register (DPR)
Data bank register (DT)
0 0
0016
000016
0016
Contents of other registers and RAM are undefined during reset. Initialize them by software.
Fig. 12 Microcomputer internal status during reset
15
MITSUBISHI MICROCOMPUTERS
Y
NAR
M37735S4BFP
MI
I
L
E
.
.
tion hange
c
ifica
pec ject to
s
l
fina
sub
ot a its are
is n
his tric lim
T
:
me
ice
Not e para
Som
PR
16-BIT CMOS MICROCOMPUTER
ADDRESSING MODES
Power on
4.5 V
VCC
RESET
VCC
MACHINE INSTRUCTION LIST
0V
RESET
0V
0.9 V
Note. In this case, stabilized clock is input from the
external to the main-clock oscillation circuit.
Perform careful evaluation at the system design
level before using.
Fig. 13 Example of a reset circuit
16
The M37735S4BFP has 28 powerful addressing modes.Refer to the
MITSUBISHI SEMICONDUCTORS DATA BOOK SINGLE-CHIP 16BIT MICROCOMPUTERS for the details of each addressing mode.
The M37735S4BFP has 103 machine instructions. Refer to the
MITSUBISHI SEMICONDUCTORS DATA BOOK SINGLE-CHIP 16BIT MICROCOMPUTERS for details.
MITSUBISHI MICROCOMPUTERS
Y
NAR
M37735S4BFP
MI
I
L
E
.
.
tion hange
c
ifica
pec ject to
s
l
fina
sub
ot a its are
is n
his tric lim
T
:
me
ice
Not e para
Som
PR
16-BIT CMOS MICROCOMPUTER
ABSOLUTE MAXIMUM RATINGS
Symbol
Vcc
AVcc
VI
VI
VO
Pd
Topr
Tstg
Parameter
Conditions
Power source voltage
Analog power_____
source voltage
Input voltage RESET, CNVss, BYTE
Input voltage P10 /A8 /D8 – P17/A 15/D15, P20/A 0/D0 – P27 /A7 /D7,
P43 – P47 , P50 – P57 ,_____
P60 – ____
P67 , P70 – P77,
P80 –___
P87 , VREF, XIN, HOLD, RDY
Output voltage P00 /CS0 – P07 /A17, P10 /A8 /D____
8 – P1 7/A 15/D15,
_____
P20 /A0 /D0 – P27/A 7/D7 , P30 /WEL – P33/HLDA ,P42 / 1,
P43 – ____
P47 , P50 – P57 , P60 – P67 , P70 – P77, P8 0 – P87,
XOUT, RDE
Power dissipation
Ta = 25 °C
Operating temperature
Storage temperature
Ratings
–0.3 to +7
–0.3 to +7
–0.3 to +12
Unit
V
V
V
–0.3 to Vcc + 0.3
V
–0.3 to Vcc + 0.3
V
300
–20 to +85
–40 to +150
mW
°C
°C
RECOMMENDED OPERATING CONDITIONS (Vcc = 5 V ± 10%, Ta = –20 to +85 °C, unless otherwise noted)
Symbol
Vcc
AVcc
Vss
AVss
VIH
VIH
VIL
VIL
IOH(peak)
IOH(avg)
IOL(peak)
IOL(peak)
IOL(avg)
IOL(avg)
f(XIN)
f(XCIN)
Parameter
f(X IN) : Operating
f(X IN) : Stopped, f(XCIN) = 32.768 kHz
Analog power source voltage
Power source voltage
Analog power source voltage
____ ___
High-level input voltage HOLD, RDY, P43_____
– P47 , P50 – P57 , P60 – P67 , P70 – P77 ,
P80 – P87, XIN, RESET , CNVss, BYTE, XCIN (Note 3)
High-level input voltage____
P10/A___
8/D8 – P17/A15 /D15, P20/A0/D0 – P27/A 7/D7
Low-level input voltage HOLD, RDY, P43_____
– P47, P50 – P57 , P60 – P67 , P70 – P77 ,
P80 – P87, XIN, RESET, CNVss, BYTE, XCIN (Note 3)
Low-level input voltage P10/A8/D8 –___
P17/A 15/D15, P2 0/A 0/D0 – P27/A7/D7
High-level peak output current P00/CS 0 – P0 7/A17 , P10/A8/D____
8 – P1 7/A 15/D15,
_____
P20/A0/D0 – P27/A7/D7, P3 0/ WEL – P3 3/ HLDA,
P42/ 1, P43 – P4 7, P5 0 – P57, P60 – P67,
P70 – P7
7, P8 0 – P8 7
___
High-level average output current P00/CS 0 – P0 7/A17 , P10/A8/D____
8 – P1 7/A15/D15,
_____
P20/A0/D0 – P2 7/A7/D7, P30/ WEL – P33/HLDA,
P42/ 1, P43 – P47, P5 0 – P5 7, P6 0 – P67,
P7
0 – P77, P80 – P8 7
___
Low-level peak output current P00/ CS0 – P07/A17, P1 0/A8/D____
8 – P17/A15/D15 ,
_____
P20/A0/D0 – P27/A7/D7, P3 0/WEL – P3 3/ HLDA,
P42/ 1, P4 3, P5 4 – P57, P60 – P67, P7 0 – P7 7,
P80 – P8 7
Low-level peak output current P44 – P4
7, P5 0 – P5 3
___
Low-level average output current P00/ CS0 – P07/A17, P1 0/A 8/D____
8 – P17/A15/D15 ,
_____
P20/A0/D0 – P2 7/A7/D7, P3 0/ WEL – P33/ HLDA,
P42/ 1, P43, P54 – P57,P60 – P67, P70 – P77,
P80 – P87
Low-level average output current P44 – P4 7, P5 0 – P53
Main-clock oscillation frequency (Note 4)
Sub-clock oscillation frequency
Power source voltage
Min.
4.5
2.7
Limits
Typ.
5.0
Max.
5.5
5.5
Vcc
0
0
Unit
V
V
V
V
0.8 Vcc
Vcc
V
0.5 Vcc
Vcc
V
0
0.2Vcc
V
0
0.16Vcc
V
–10
mA
–5
mA
10
mA
20
mA
5
mA
15
25
50
mA
MHz
kHz
32.768
Notes 1. Average output current is the average
value of a 100 ms interval.
___
____
_____
2. The sum of IOL(peak) for ports P0 0/ CS0 – P07/A17, P1 0___
/A8/D8 – P17/A15/D15 , P20/A0/D0 – P2 7/A 7/D7, P30/WEL – P33/HLDA and
P8 must
____
be 80 mA or less, the sum of IOH(peak) for ports P0 0/ CS0 – P07/A17, P1 0/A8/D8 – P17/A15/D15 , P20/A0/D0 – P2 7/A7/D7, P30/WEL – P33/
_____
HLDA and P8 must be 80 mA or less, the sum of IOL(peak) for ports P4, P5, P6, and P7 must be 100 mA or less, and the sum of IOH(peak)
for ports P4, P5, P6, and P7 must be 80 mA or less.
3. Limits VIH and V IL for XCIN are applied when the sub clock external input selection bit = “1”.
4. The maximum value of f(XIN) = 12.5 MHz when the main clock division selection bit = “1”.
17
MITSUBISHI MICROCOMPUTERS
Y
NAR
M37735S4BFP
MI
I
L
E
.
.
tion hange
c
ifica
pec ject to
s
l
fina
sub
ot a its are
is n
his tric lim
T
:
me
ice
Not e para
Som
PR
16-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = –20 to +85 °C, f(XIN) = 25 MHz, unless otherwise noted)
Symbol
Parameter
Test conditions
___
VOH
VOH
High-level output voltage P00 /CS0 – P07/A17, P1 0/A 8/D_____
8 – P17 /A15/D15,
P20/A 0/D0 – P27 /A7 /D7, P3 3/HLDA, P42/ 1,
P43 – P47, P5 0 – P57, P6 0 – P67, P70 – P77,
P80 –___
P87
High-level output voltage P00 /CS0 – P07/A17, P1 0/A 8/D_____
8 – P17 /A15/D15,
P20/A 0/D0 – P27/A7 /D7, P3 3/HLDA, P42 / 1
____
____
VOH
High-level output voltage P30/ WEL, P31/ WEH, P3 2/ALE
VOH
High-level output voltage RDE
____
___
VOL
VOL
VOL
Low-level output voltage P00 /CS0 – P07/A17, P1 0/A 8/D_____
8 – P17 /A15/D15,
P20/A 0/D 0 – P27/A 7/D7 , P33 /HLDA, P42 / 1,
P43, P5 4 – P57, P6 0 – P67, P7 0 – P77,
P80 – P87
Low-level output voltage P44 – P47 , P50 – P53
___
Low-level output voltage P00 /CS0 – P07/A17, P1 0/A 8/D8_____
– P17 /A15/D15,
P20/A 0/D0 – P27/A7 /D7, P3 3/HLDA, P42 / 1
____
____
VOL
Low-level output voltage P30/WEL, P3 1/WEH, P32/ALE
VOL
Low-level output voltage RDE
____
____ ___
VT+ – VT–
VT+ – V T–
VT+ – V T–
VT+ – VT–
IIH
IIL
IIL
VRAM
18
Hysteresis ____
HOLD, ____
RDY , _____
TA0IN –____
TA4IN
, TB0____
IN – TB2IN,
____
INT0 – INT2 , AD
TRG
,
CTS
0
,
CTS
1
,
CTS
2, CLK0 ,
___
___
CLK1, CLK2, KI0 – KI3
_____
Hysteresis RESET
Hysteresis XIN
Hysteresis XCIN (When external clock is input)
High-level input current P10/A 8/D8 – P17 /A15/D15,
P20 /A0 /D0 – P27/A 7/D7 , P43 – P47 ,
P50 – P57 , P60 _____
– P67 , P70 – P77 ,
P80 – P87 , XIN, RESET, CNVss, BYTE
Low-level input current P10/A 8/D8 – P17 /A15/D15,
P20 /A0 /D0 – P27 /A7/D 7, P43 – P47 ,
P50 – P53, P60 ,_____
P61 , P65 – P67 , P70 – P77,
P80 – P87, XIN, RESET, CNVss, BYTE
Low-level input current P54 – P57, P6 2 – P6 4
RAM hold voltage
Min.
Limits
Typ.
Max.
Unit
3
V
A
4.7
V
IOH = –10 mA
IOH = –400 A
IOH = –10 mA
IOH = –400 A
3.1
4.8
3.4
4.8
V
IOH = –10 mA
IOH = –400
V
IOL = 10 mA
2
V
IOL = 20 mA
2
V
IOL = 2 mA
0.45
V
IOL = 10 mA
IOL = 2 mA
IOL = 10 mA
IOL = 2 mA
1.9
0.43
1.6
0.4
V
V
0.4
1
V
0.2
0.1
0.1
0.5
0.4
0.4
V
V
V
VI = 5 V
5
A
VI = 0 V
–5
A
–5
A
–1.0
mA
VI = 0 V,
without a pull-up
transistor
VI = 0 V,
with a pull-up
transistor
When clock is stopped.
–0.25
2
–0.5
V
MITSUBISHI MICROCOMPUTERS
Y
NAR
M37735S4BFP
MI
I
L
E
.
.
tion hange
c
ifica
pec ject to
s
l
fina
sub
ot a its are
is n
his tric lim
T
:
me
ice
Not e para
Som
PR
16-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = –20 to +85 °C, unless otherwise noted)
Symbol
Parameter
Power source
current
I CC
Test conditions
Min.
VCC = 5 V,
f(X IN) = 25 MHz (square waveform),
(f(f2) = 12.5 MHz),
f(X CIN) = 32.768 kHz,
in operating (Note 1)
VCC = 5 V,
f(X IN) = 25 MHz (square waveform),
(f(f2) = 1.5625 MHz),
f(X CIN): Stopped
in operating (Note 1)
When external bus VCC = 5 V,
f(X IN) = 25 MHz (square waveform),
is in use, output
pins are open, and f(X CIN) = 32.768 kHz,
other pins are VSS. when a WIT instruction is executed (Note 2)
VCC = 5 V,
f(X IN) : Stopped,
f(X CIN) = 32.768 kHz,
in operating (Note 3)
VCC = 5 V,
f(X IN) : Stopped,
f(X CIN) = 32.768 kHz,
when a WIT instruction is executed (Note 4)
Ta = 25 °C,
when clock is stopped
Ta = 85 °C,
when clock is stopped
Limits
Typ.
Max.
Unit
11.4
22.8
mA
1.6
3.2
mA
10
20
A
60
120
A
5
10
A
1
A
20
A
Notes 1. This applies when the main clock external input selection bit = “1”, the main clock division selection bit = “0”, and the signal output stop
bit = “1”.
2. This applies when the main clock external input selection bit = “1” and the system clock stop bit at wait state = “1”.
3. This applies when CPU and the clock timer are operating with the sub clock (32.768 kHz) selected as the system clock.
4. This applies when the XCOUT drivability selection bit = “0” and the system clock stop bit at wait state = “1”.
A–D CONVERTER CHARACTERISTICS
(VCC = AVCC = 5 V, VSS = AVSS = 0 V, Ta = –20 to +85 °C, f(XIN) = 25 MHz, unless otherwise noted (Note))
Symbol
—
—
RLADDER
tCONV
VREF
VIA
Parameter
Resolution
Absolute accuracy
Ladder resistance
Conversion time
Reference voltage
Analog input voltage
Test conditions
VREF = VCC
VREF = VCC
VREF = VCC
Min.
10
9.44
2
0
Limits
Typ.
Max.
10
±3
25
VCC
VREF
Unit
Bits
LSB
kΩ
s
V
V
Note. This applies when the main clock division selection bit = “0” and f(f2) = 12.5 MHz.
19
MITSUBISHI MICROCOMPUTERS
Y
NAR
M37735S4BFP
MI
I
L
E
.
.
tion hange
c
ifica
pec ject to
s
l
fina
sub
ot a its are
is n
his tric lim
T
:
me
ice
Not e para
Som
PR
16-BIT CMOS MICROCOMPUTER
TIMING REQUIREMENTS (VCC = 5 V ± 10%, VSS = 0 V, Ta = –20 to +85 °C, f(XIN) = 25 MHz, unless otherwise noted (Note 1))
Notes 1. This applies when the main clock division selection bit = “0” and f(f2) = 12.5 MHZ .
2. Input signal’s rise/fall time must be 100 ns or less, unless otherwise noted.
External clock input
Symbol
tc
tw(H)
tw(L)
tr
tf
Parameter
External clock input cycle time (Note 1)
External clock input high-level pulse width (Note 2)
External clock input low-level pulse width (Note 2)
External clock rise time
External clock fall time
Limits
Min.
40
15
15
Max.
8
8
Unit
ns
ns
ns
ns
ns
Notes 1. When the main clock division selection bit = “1”, the minimum value of tc = 80 ns.
2. When the main clock division selection bit = “1”, values of tw(H) / t c and tw(L) / t c must be set to values from 0.45 through 0.55.
Microprocessor mode
Symbol
tsu(P4D–RDE)
tsu(P5D–RDE)
tsu(P6D–RDE)
tsu(P7D–RDE)
tsu(P8D–RDE)
th(RDE–P4D)
th(RDE–P5D)
th(RDE–P6D)
th(RDE–P7D)
th(RDE–P8D)
Parameter
Port P4 input setup time
Port P5 input setup time
Port P6 input setup time
Port P7 input setup time
Port P8 input setup time
Port P4 input hold time
Port P5 input hold time
Port P6 input hold time
Port P7 input hold time
Port P8 input hold time
Limits
Min.
60
60
60
60
60
0
0
0
0
0
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Microprocessor mode
Symbol
tsu(D–RDE)
tsu(RDY– 1)
tsu(HOLD– 1)
th(RDE–D)
th( 1–RDY)
th( 1–HOLD)
20
Parameter
Data input setup time
___
RDY input setup time
____
HOLD input setup time
Data input hold time
___
RDY input hold time
____
HOLD input hold time
Limits
Min.
32
55
55
0
0
0
Max.
Unit
ns
ns
ns
ns
ns
ns
MITSUBISHI MICROCOMPUTERS
Y
NAR
M37735S4BFP
I
ge.
ion.
icat to chan
ecif
l sp ubject
a
in
af
es
not mits ar
li
is is
: Th metric
e
ic
Not e para
Som
IM
REL
P
Timer A input
(Count input in event counter mode)
Symbol
tc(TA)
tw(TAH)
tw(TAL)
16-BIT CMOS MICROCOMPUTER
Parameter
TAiIN input cycle time
TAiIN input high-level pulse width
TAiIN input low-level pulse width
Limits
Min.
80
40
40
Max.
Unit
ns
ns
ns
Timer A input (Gating input in timer mode)
Symbol
tc(TA)
tw(TAH)
tw(TAL)
Parameter
TAiIN input cycle time (Note)
TAiIN input high-level pulse width (Note)
TAiIN input low-level pulse width (Note)
Limits
Min.
320
160
160
Max.
Unit
ns
ns
ns
Note. Limits change depending on f(XIN). Refer to “DATA FORMULAS”.
Timer A input (External trigger input in one-shot pulse mode)
Symbol
t c(TA)
t w(TAH)
t w(TAL)
Parameter
TAiIN input cycle time (Note)
TAiIN input high-level pulse width
TAiIN input low-level pulse width
Limits
Min.
320
80
80
Max.
Unit
ns
ns
ns
Note. Limits change depending on f(XIN). Refer to “DATA FORMULAS”.
Timer A input (External trigger input in pulse width modulation mode)
Symbol
tw(TAH)
tw(TAL)
Parameter
TAiIN input high-level pulse width
TAiIN input low-level pulse width
Limits
Min.
80
80
Max.
Unit
ns
ns
Timer A input (Up-down input in event counter mode)
Symbol
tc(UP)
tw(UPH)
tw(UPL)
tsu(UP–TIN)
th(TIN–UP)
Parameter
TAiOUT input cycle time
TAiOUT input high-level pulse width
TAiOUT input low-level pulse width
TAiOUT input setup time
TAiOUT input hold time
Limits
Min.
2000
1000
1000
400
400
Max.
Unit
ns
ns
ns
ns
ns
Timer A input (Two-phase pulse input in event counter mode)
Symbol
tc(TA)
tsu(TAjIN–TAjOUT)
tsu(TAjOUT–TAjIN)
Parameter
TAjIN input cycle time
TAjIN input setup time
TAjOUT input setup time
Limits
Min.
800
200
200
Max.
Unit
ns
ns
ns
21
MITSUBISHI MICROCOMPUTERS
Y
NAR
M37735S4BFP
I
ge.
ion.
icat to chan
ecif
l sp ubject
a
in
af
es
not mits ar
li
is is
: Th metric
e
ic
Not e para
Som
IM
REL
P
16-BIT CMOS MICROCOMPUTER
Timer B input (Count input in event counter mode)
Symbol
tc(TB)
tw(TBH)
tw(TBL)
tc(TB)
tw(TBH)
tw(TBL)
Limits
Parameter
Min.
80
40
40
160
80
80
TBiIN input cycle time (one edge count)
TBiIN input high-level pulse width (one edge count)
TBiIN input low-level pulse width (one edge count)
TBiIN input cycle time (both edges count)
TBiIN input high-level pulse width (both edges count)
TBiIN input low-level pulse width (both edges count)
Max.
Unit
ns
ns
ns
ns
ns
ns
Timer B input (Pulse period measurement mode)
Symbol
tc(TB)
tw(TBH)
tw(TBL)
Limits
Parameter
Min.
320
160
160
TBiIN input cycle time (Note)
TBiIN input high-level pulse width (Note)
TBiIN input low-level pulse width (Note)
Max.
Unit
ns
ns
ns
Note. Limits change depending on f(XIN). Refer to “DATA FORMULAS”.
Timer B input (Pulse width measurement mode)
Symbol
Limits
Parameter
tc(TB)
tw(TBH)
tw(TBL)
TBiIN input cycle time (Note)
TBiIN input high-level pulse width (Note)
TBiIN input low-level pulse width (Note)
Note. Limits change depending on f(XIN). Refer to “DATA FORMULAS”.
Min.
320
160
160
Max.
Unit
ns
ns
ns
A-D trigger input
Symbol
Limits
Parameter
Min.
1000
125
_____
tc(AD)
tw(ADL)
AD
TRG input cycle time (minimum allowable trigger)
_____
ADTRG input low-level pulse width
Max.
Unit
ns
ns
Serial I/O
Symbol
tc(CK)
tw(CKH)
tw(CKL)
td(C–Q)
th(C–Q)
tsu(D–C)
th(C–D)
Limits
Parameter
Min.
200
100
100
CLKi input cycle time
CLKi input high-level pulse width
CLKi input low-level pulse width
TXDi output delay time
TXDi hold time
RXDi input setup time
RXDi input hold time
Max.
80
0
30
90
____
Unit
ns
ns
ns
ns
ns
ns
ns
___
External interrupt INT i input, key input interrupt KIi input
Symbol
Parameter
____
tw(INH)
tw(INL)
tw(KIL)
22
INTi input high-level pulse width
INTi input low-level pulse width
KIi input low-level pulse width
____
___
Limits
Min.
250
250
250
Max.
Unit
ns
ns
ns
MITSUBISHI MICROCOMPUTERS
Y
NAR
M37735S4BFP
MI
I
L
E
.
.
tion hange
c
ifica
pec ject to
s
l
fina
sub
ot a its are
is n
his tric lim
T
:
me
ice
Not e para
Som
PR
16-BIT CMOS MICROCOMPUTER
DATA FORMULAS
Timer A input (Gating input in timer mode)
Symbol
Parameter
tc(TA)
TAiIN input cycle time
tw(TAH)
TAiIN input high-level pulse width
tw(TAL)
TAiIN input low-level pulse width
Limits
Min.
8 ✕ 109
2 • f(f2)
4 ✕ 109
2 • f(f2)
4 ✕ 109
2 • f(f2)
Max.
Unit
ns
ns
ns
Timer A input (External trigger input in one-shot pulse mode)
Symbol
tc(TA)
Parameter
TAiIN input cycle time
Limits
Min.
8 ✕ 109
2 • f(f2)
Max.
Unit
ns
Timer B input (In pulse period measurement mode or pulse width measurement mode)
Symbol
Parameter
tc(TB)
TBiIN input cycle time
tw(TBH)
TBiIN input high-level pulse width
tw(TBL)
TBiIN input low-level pulse width
Limits
Min.
8 ✕ 109
2 • f(f2)
4 ✕ 109
2 • f(f2)
4 ✕ 109
2 • f(f2)
Max.
Unit
ns
ns
ns
Note. f(f2) represents the clock f2 frequency.
For the relation to the main clock and sub clock, refer to Table 10 in data sheet “M37735MHBXXXFP”.
23
MITSUBISHI MICROCOMPUTERS
Y
NAR
M37735S4BFP
MI
I
L
E
.
.
tion hange
c
ifica
pec ject to
s
l
fina
sub
ot a its are
is n
his tric lim
T
:
me
ice
Not e para
Som
PR
16-BIT CMOS MICROCOMPUTER
SWITCHING CHARACTERISTICS
(VCC = 5 V ± 10%, VSS = 0 V, Ta = –20 to +85°C, f(XIN) = 25 MHz, unless otherwise noted (Note))
Microprocessor mode
Symbol
Parameter
t d(WE–P4Q)
t d(WE–P5Q)
t d(WE–P6Q)
t d(WE–P7Q)
t d(WE–P8Q)
Port P4 data output delay time
Port P5 data output delay time
Port P6 data output delay time
Port P7 data output delay time
Port P8 data output delay time
Test conditions
Fig. 14
Note. This applies when the main clock division selection bit = “0” and f(f2) = 12.5 MHz.
CS0 – CS4
RSMP
A16, A17
A0/D0 – A15/D15
WEL
WEH
ALE
HLDA
P4
P5
P6
P7
P8
1
RDE
Fig. 14 Measuring circuit for each pin
24
50 pF
Limits
Min.
Max.
80
80
80
80
80
Unit
ns
ns
ns
ns
ns
MITSUBISHI MICROCOMPUTERS
Y
NAR
M37735S4BFP
MI
I
L
E
.
.
tion hange
c
ifica
pec ject to
s
l
fina
sub
ot a its are
is n
his tric lim
T
:
me
ice
Not e para
Som
PR
16-BIT CMOS MICROCOMPUTER
Microprocessor mode
(VCC = 5 V ± 10%, VSS = 0 V, Ta = –20 to +85 °C, f(XIN) = 25 MHz, unless otherwise noted (Note 1))
Symbol
td(CS–WE)
td(CS–RDE)
Parameter
Chip-select output delay time
th(WE–CS)
th(RDE–CS)
Chip-select hold time
td(An–WE)
td(An–RDE)
Address output delay time
td(A–WE)
td(A–RDE)
Address output delay time
th(WE–An)
th(RDE–An)
Address hold time
tw(ALE)
ALE pulse width
tsu(A–ALE)
th(ALE–A)
td(ALE–WE)
td(ALE–RDE)
td(WE–DQ)
th(WE–DQ)
Address output setup time
Address hold time
ALE output delay time
tpxz(RDE–DZ)
tpzx(RDE–DZ)
tw(RDE)
td(RSMP–WE)
td(RSMP–RDE)
th( 1–RSMP)
td(WE– 1)
td(RDE– 1)
td( 1–HLDA)
No wait
Wait 1
Wait 0
No wait
Wait 1
Wait 0
No wait
Wait 1
Wait 0
No wait
Wait 1
Wait 0
No wait
Wait 1
Wait 0
No wait
Wait 1
Wait 0
Fig. 14
WEL/ WEH pulse width
No wait
Wait 1
Wait 0
RDE pulse width
No wait
Wait 1
Wait 0
____
RSMP output delay time
____
RSMP hold time
1
Max.
output delay time
ns
87
ns
4
ns
12
ns
87
ns
12
ns
75
ns
18
ns
22
ns
57
ns
5
ns
45
ns
9
ns
15
ns
4
ns
10
18
50
130
ns
ns
ns
ns
ns
20
48
ns
ns
ns
128
ns
10
ns
0
ns
0
18
ns
50
ns
____
HLDA output delay time
Unit
12
5
Floating start delay time
Floating release delay time
___
Limits
Min.
45
Data output delay time
Data hold time
___ ___
tw(WE)
Test
(Note 2)
Wait mode conditions
No wait
Wait 1
Wait 0
Notes 1. This applies when the main clock division selection bit = “0” and f(f2) = 12.5 MHz.
2. No wait : Wait bit = “1”.
Wait 1 : The external memory area is accessed with wait bit = “0” and wait selection bit = “1”.
Wait 0 : The external memory area is accessed with wait bit = “0” and wait selection bit = “0”.
25
MITSUBISHI MICROCOMPUTERS
Y
NAR
M37735S4BFP
MI
I
L
E
.
.
tion hange
c
ifica
pec ject to
s
l
fina
sub
ot a its are
is n
his tric lim
T
:
me
ice
Not e para
Som
PR
16-BIT CMOS MICROCOMPUTER
Microprocessor mode
Bus timing data formulas (VCC = 5 V ± 10%, VSS = 0 V, Ta = –20 to +85 °C, f(XIN) = 25 MHz (Max.), unless otherwise noted (Note1))
Symbol
Parameter
td(CS–WE)
td(CS–RDE)
Chip-select output delay time
th(WE–CS)
th(RDE–CS)
Chip-select hold time
td(An–WE)
td(An–RDE)
Wait 0
Address output delay time
Address output delay time
th(WE–An)
th(RDE–An)
Address hold time
No wait
Wait 1
Wait 0
ALE pulse width
No wait
Wait 1
Wait 0
tsu(A–ALE)
Address output setup time
No wait
Wait 1
Wait 0
th(ALE–A)
Address hold time
No wait
Wait 1
ALE output delay time
td(WE–DQ)
Data output delay time
th(WE–DQ)
tpxz(RDE–DZ)
tpzx(RDE–DZ)
tw(RDE)
td(RSMP–WE)
td(RSMP–RDE)
th( 1–RSMP)
td(WE– 1)
td(RDE– 1)
No wait
Wait 1
WEL/ WEH pulse width
1 ✕ 109
2 • f(f 2)
3 ✕ 109
2 • f(f 2)
1 ✕ 109
2 • f(f 2)
3 ✕ 109
2 • f(f 2)
1 ✕ 109
2 • f(f 2)
1 ✕ 109
2 • f(f 2)
2 ✕ 109
2 • f(f 2)
1 ✕ 109
2 • f(f 2)
2 ✕ 109
2• f(f 2)
– 28
ns
– 33
ns
– 28
ns
– 45
ns
– 22
ns
– 18
ns
– 23
ns
– 35
ns
– 35
ns
ns
– 25
1 ✕ 10
2 • f(f 2)
No wait
1 ✕ 109
2 • f(f 2)
2 ✕ 109
2 • f(f 2)
4 ✕ 109
2 • f(f 2)
ns
– 30
RSMP output delay time
____
RSMP hold time
1
output delay time
Wait 1
Wait 0
ns
– 30
ns
– 30
ns
5
Wait 1
Wait 0
1 ✕ 109
2 • f(f 2)
2 ✕ 109
2 • f(f 2)
4 ✕ 109
2 • f(f 2)
1 ✕ 109
2 • f(f 2)
0
ns
– 22
ns
– 20
ns
– 32
ns
– 32
ns
– 30
ns
0
Notes 1. This applies when the main clock division selection bit = “0”.
2. f(f 2) represents the clock f2 frequency.
For the relation to the main clock and sub clock, refer to Table 10 in data sheet “M37735MHBXXXFP”.
26
ns
45
No wait
____
ns
4
Wait 0
Floating release delay time
RDE pulse width
ns
ns
Floating start delay time
___
ns
9
1 ✕ 10
2 • f(f 2)
Unit
9
Data hold time
___ ___
tw(WE)
Max.
9
Wait 0
td(ALE–WE)
td(ALE–RDE)
Limits
Min.
1 ✕ 109
–28
2 • f(f 2)
9
3 ✕ 10
– 33
2 • f(f 2)
4
No wait
Wait 1
Wait 0
td(A–WE)
td(A–RDE)
tw(ALE)
Wait mode
No wait
Wait 1
ns
18
ns
MITSUBISHI MICROCOMPUTERS
Y
NAR
M37735S4BFP
MI
ELI
ion. hange.
icat
ecif ct to c
p
s
al
bje
a fin are su
not
s
is is ric limit
h
T
met
ice:
Not e para
Som
PR
16-BIT CMOS MICROCOMPUTER
TIMING DIAGRAM
tr
tf
tc
tw(H)
tw(L)
XIN
RDE, WEL, WEH
td(WE–P4Q)
Port P4 output
tsu(P4D–RDE)
th(RDE–P4D)
Port P4 input
td(WE–P5Q)
Port P5 output
tsu(P5D–RDE)
th(RDE–P5D)
Port P5 input
td(WE–P6Q)
Port P6 output
tsu(P6D–RDE)
th(RDE–P6D)
Port P6 input
td(WE–P7Q)
Port P7 output
tsu(P7D–RDE)
th(RDE–P7D)
Port P7 input
td(WE–P8Q)
Port P8 output
tsu(P8D–RDE)
th(RDE–P8D)
Port P8 input
27
MITSUBISHI MICROCOMPUTERS
Y
NAR
M37735S4BFP
MI
I
L
E
.
.
tion hange
c
ifica
pec ject to
s
l
fina
sub
ot a its are
is n
his tric lim
T
:
me
ice
Not e para
Som
PR
16-BIT CMOS MICROCOMPUTER
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
In event count mode
TAiOUT input
(Up-down input)
TAiIN input
(when count by falling)
TAiIN input
(when count by rising)
th(TIN–UP)
tsu(UP–TIN)
In event counter mode
(When two-phase pulse input is selected)
tc(TA)
TAjIN input
tsu(TAjIN–TAjOUT)
tsu(TAjIN–TAjOUT)
tsu(TAjOUT–TAjIN)
TAjOUT input
tsu(TAjOUT–TAjIN)
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
28
MITSUBISHI MICROCOMPUTERS
Y
NAR
M37735S4BFP
MI
I
L
E
.
.
tion hange
c
ifica
pec ject to
s
l
fina
sub
ot a its are
is n
his tric lim
T
:
me
ice
Not e para
Som
PR
16-BIT CMOS MICROCOMPUTER
tc(AD)
tw(ADL)
ADTRG input
tc(CK)
tw(CKH)
CLKi
tw(CKL)
th(C–Q)
TxDi
td(C–Q)
tsu(D–C)
th(C–D)
RxDi
tw(INL)
INTi input
Kli input
tw(INH)
tw(KNL)
29
MITSUBISHI MICROCOMPUTERS
Y
NAR
M37735S4BFP
I
ge.
ion.
icat to chan
ecif
l sp ubject
a
in
af
es
not mits ar
li
is is
: Th metric
e
ic
Not e para
Som
IM
REL
P
16-BIT CMOS MICROCOMPUTER
Microprocessor mode
(When wait bit = “1”)
1
WEL
WEH
RDE
RDY input
tsu(RDY–
1)
th(
1–RDY)
tsu(RDY–
1)
th(
1–RDY)
(When wait bit = “0”)
1
WEL
WEH
RDE
RDY input
(When wait bit = “1” or “0” in common)
1
tsu(HOLD–
th(
1)
1–HOLD)
HOLD input
td(
1–HLDA)
HLDA output
Test conditions
• VCC = 5 V ± 10%
• Input timing voltage : VIL = 1.0 V, VIH = 4.0 V
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
30
td(
1–HLDA)
MITSUBISHI MICROCOMPUTERS
Y
NAR
M37735S4BFP
MI
I
L
E
.
.
tion hange
c
ifica
pec ject to
s
l
fina
sub
ot a its are
is n
his tric lim
T
:
me
ice
Not e para
Som
PR
16-BIT CMOS MICROCOMPUTER
Microprocessor mode
(No wait : When wait bit = “1”)
tw(L)
tw(H)
tf
tr
tc
XIN
1
td(WE–
td(WE–
1)
td(RDE–
1)
td(RDE–
1)
1)
CS0 – CS4
td(CS–WE)
td(CS–RDE)
th(WE–CS)
An
th(RDE–CS)
Address
Address
td(An–WE)
tw(ALE)
Address
td(An–RDE)
td(ALE–WE)
th(RDE–An)
th(WE–An)
ALE
td(ALE–RDE)
th(ALE–A)
tsu(A–ALE)
th(WE–DQ)
Am/Dm
Address
Data
tpxz(RDE–DZ)
tpzx(RDE–DZ)
Address
Address
td(A–RDE)
td(WE–DQ)
td(A–WE)
tw(WE)
th(RDE–D)
WEL, WEH
tsu(D–RDE)
DmIN
Data
tw(RDE)
RDE
th(
1–RSMP)
td(RSMP–WE)
td(RSMP–RDE)
RSMP
Test condition
• Vcc = 5 V ± 10%
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
• Data input DmIN : VIL = 0.8 V, VIH = 2.5 V
31
MITSUBISHI MICROCOMPUTERS
Y
NAR
M37735S4BFP
MI
I
L
E
.
.
tion hange
c
ifica
pec ject to
s
l
fina
sub
ot a its are
is n
his tric lim
T
:
me
ice
Not e para
Som
PR
16-BIT CMOS MICROCOMPUTER
Microprocessor mode
(Wait 1 : The external area is accessed when wait bit = “0” and wait selection bit = “1”.)
tw(L)
tw(H)
tf tr
tc
XIN
1
td(WE–
td(WE–
1)
1)
td(RDE–
td(RDE-
CS0 – CS4
1)
1)
th(WE–CS)
th(RDE–CS)
td(CS–RDE)
td(CS–WE)
Address
An
td(An–WE)
tw(ALE)
Address
Address
th(RDE–An)
td(An–RDE)
td(ALE–WE)
th(WE-An)
ALE
th(ALE–A)
tsu(A–ALE)
Am/Dm
td(ALE–RDE)
tpxz(RDE–DZ)
th(WE–DQ)
Address
td(A–WE)
Data
td(WE–DQ)
Address
tpzx(RDE–DZ)
Address
td(A–RDE)
tw(WE)
th(RDE–D)
WEL, WEH
tsu(D–RDE)
DmIN
Data
tw(RDE)
RDE
th(
RSMP
1–RSMP)
td(RSMP–WE)
Test condition
• Vcc = 5 V ± 10%
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
• Data input DmIN : VIL = 0.8 V, VIH = 2.5 V
32
td(RSMP–RDE)
MITSUBISHI MICROCOMPUTERS
Y
NAR
M37735S4BFP
MI
I
L
E
.
.
tion hange
c
ifica
pec ject to
s
l
fina
sub
ot a its are
is n
his tric lim
T
:
me
ice
Not e para
Som
PR
16-BIT CMOS MICROCOMPUTER
Microprocessor mode
(Wait 0 : The external memory are is accessed when wait bit = “0” and wait selection bit = “0”.)
tw(L)
tw(H)
tf tr
tc
XIN
1
td(WE–
td(WE–
1)
td(RDE–
1)
td(RDE–
1)
1)
CS0 – CS4
th(WE–CS)
td(CS–WE)
td(CS–RDE)
th(RDE–CS)
Address
An
Address
td(An–WE)
tw(ALE)
Address
td(An–RDE)
td(ALE–WE)
th(RDE–An)
th(WE–An)
ALE
td(ALE–RDE)
tsu(A–ALE)
Am/Dm
th(ALE–A)
Address
Data
tpxz(RDE–DZ)
th(WE–DQ)
tpzx(RDE–DZ)
Address
Address
td(WE–DQ)
td(A–WE)
td(A–RDE)
tw(WE)
WEL, WEH
tsu(D–RDE)
th(RDE–D)
Data
DmIN
tw(RDE)
RDE
td(RSMP–WE)
th(
1–RSMP)
td(RSMP–RDE)
RSMP
Test conditions
• Vcc = 5 V ± 10%
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
• Data input DmIN : VIL = 0.8 V, VIH = 2.5 V
33
Y
NAR
I
ge.
ion.
icat to chan
ecif
l sp ubject
a
in
af
es
not mits ar
li
is is
: Th metric
e
ic
Not e para
Som
IM
REL
MITSUBISHI MICROCOMPUTERS
M37735S4BFP
P
PACKAGE OUTLINE
34
16-BIT CMOS MICROCOMPUTER
I
Y
NAR
ge.
ion.
icat to chan
ecif
l sp ubject
a
in
af
es
not mits ar
li
is is
: Th metric
e
ic
Not e para
Som
IM
REL
MITSUBISHI MICROCOMPUTERS
M37735S4BFP
P
16-BIT CMOS MICROCOMPUTER
MEMO
35
Y
NAR
MI
I
L
E
.
.
tion hange
c
ifica
pec ject to
s
l
fina
sub
ot a its are
is n
his tric lim
T
:
me
ice
Not e para
Som
MITSUBISHI MICROCOMPUTERS
M37735S4BFP
PR
16-BIT CMOS MICROCOMPUTER
Keep safety first in your circuit designs!
•
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of
substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
•
These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any
intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples
contained in these materials.
All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi
Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor for the latest product information before purchasing a product listed herein.
Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact
Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for
transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.
If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the
approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
Notes regarding these materials
•
•
•
•
•
•
© 1996 MITSUBISHI ELECTRIC CORP.
H-LF426-A KI-9606 Printed in Japan (ROD)
New publication, effective Jun. 1996.
Specifications subject to change without notice.