MITSUBISHI (Dig./Ana. INTERFACE) M62376GP 8-BIT 12CH D-A CONVERTER IC BUILT-IN 12-BIT I/O EXPANDER DESCRIPTION PIN CONFIGURATION (TOP VIEW) The M62376GP is a semiconductor IC that adopts a CMOS structure having 12-channel of 8-bit D-A converter and 12-bit I/O expander. The IC has achieved a wide operation range of 2.7V to A1 1 24 GND 5.5V in power voltage. A2 2 23 REST Data is easily available via 3-wire combination system serial input A3 3 22 EN of SI, CLK and EN. The IC also provides an SO pin enabling A4 4 21 SO cascade connection. It provides 8 pins that share D-A converter D11/A5 5 20 SI D10/A6 6 19 CLK and I/O ports that can be arbitrarily switched with serial input data. D9/A7 7 18 D0 D8/A8 8 17 D1 D7/A9 9 16 D2 D6/A10 10 15 D3 share DAC output and I/O. D5/A11 11 14 VCC Each port can be set by serial data for input/output status. D4/A12 12 13 VDD FEATURES Supply voltage 2.7 to 5.5V Adopts 4 special ports for each of DAC and I/O and 8 ports that Built-in power-on reset where D-A output is set to "L" in the Outline 24P2E-A initial status and I/O goes to Hi-impedance when power is turned on. Small package of 0.65mm pitch and 24 pin. APPLICATION Adjustment/control of industrial or home-use electronic equipment, such as VCR camera, VCR set, TV, and CRT display. BLOCK DIAGRAM SI 20 EN 22 CLK 19 RESET VDD VCC GND 23 13 14 24 SHIFT REGISTER S15 S14 S13 S12 S11 S10 S9 CLOCK CONTROL CIRCUIT S8 S7 S6 21 SO S5 S4 S3 S2 S1 S0 DECODER 8-BIT LATCH ••• 8-BIT LATCH 8-BIT LATCH •••••• 8-BIT LATCH 8-BIT D-A CONVERTER ••• 8-BIT D-A CONVERTER 8-BIT D-A CONVERTER •••••• 8-BIT D-A CONVERTER ••• Amp. Hi-Z 8-BIT LATCH I/O SELECT 12-BIT LATCH (12) •••••• A1 A4 A5 A12 •••••• •••••• OUTPUT DATA 8-BIT LATCH 1 A1 ••• 4 5 A4 D11/A5 •••••• OUTPUT DATA 4-BIT LATCH 12 15 D4/A12 D3 18 •••••• D0 MITSUBISHI (Dig./Ana. INTERFACE) M62376GP 8-BIT 12CH D-A CONVERTER IC BUILT-IN 12-BIT I/O EXPANDER EXPLANATION OF TERMINALS Pin No. 20 SI Function Serial data input pin. Enters serial data of 16-bit in length. 21 SO Outputs data from 16-bit shift register that reads serial data or parallel data. 19 CLK 22 EN 1 13 A1 A2 A3 A4 D11/A5 D10/A6 D9/A7 D8/A8 D7/A9 D6/A10 D5/A11 D4/A12 D0 D1 D2 D3 VCC GND VDD 23 RESET 2 3 4 5 6 7 8 9 10 11 12 18 17 16 15 14 24 Symbol Shift clock input pin. At the rise of shift clock, input signal from the SI pin is entered into the 16-bit shift register. Entry of low level into the EN pin starts to read data. Putting 16-bit data at high level after input loads the input data to a specified register. Special output pin for 8-bit D-A converter (DAC) Pin that shares I/O and DAC output. Settings can be selected with serial data. D4 to D11 are connected to the VDD power supply. Digital input output pin. Digital block power supply pin. GND pin Power supply pin in analog block and reference voltage input pin on the upper side of D-A converter RESET pin MITSUBISHI (Dig./Ana. INTERFACE) M62376GP 8-BIT 12CH D-A CONVERTER IC BUILT-IN 12-BIT I/O EXPANDER EXPLANATION OF TERMINALS BLOCK DIAGRAM VDD VCC GND 13 14 24 [1110] EN 22 CLOCK CONTROL Di11 Di10 Di9 Di8 Di7 Di6 Di5 Di4 Di3 Di2 Di1 Di0 EN SHIFT REGISTER CLK S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 CLK 19 SI 20 RESET 23 POWER ON RESET 21 SO S3 S2 S1 S0 LEVEL SHIFT EN LEVEL SHIFT DECODER (12) EN DECODER (4) ••••• [0000] 8-BIT LATCH 8-BIT D-A CONVERTER ••• ••• 8-BIT LATCH 8-BIT LATCH 8-BIT D-A CONVERTER 8-BIT D-A CONVERTER •••••• 8-BIT LATCH 8-BIT LATCH •••••• 8-BIT D-A CONVERTER LEVEL SHIFT (8) ••• [11010000] (A5 to A12 Hi-Z) 12-BIT LATCH A4 A5 (12) (8) •••••• A1 A12 LEVEL SHIFT [1101] LATCH (4) LATCH (8) 1 A1 ••• 4 5 A4 D11/A5 •••••• [1111] 12 15 16 17 18 D4/A12 D3 D2 D1 D0 MITSUBISHI (Dig./Ana. INTERFACE) M62376GP 8-BIT 12CH D-A CONVERTER IC BUILT-IN 12-BIT I/O EXPANDER DATA STRUCTURE Serial data MSB LSB S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 Data for DAC and I/O expander • I/O expander (serial S2 0 0 0 0 1 1 1 1 0 0 0 0 1 S1 0 0 1 1 0 0 1 1 0 0 1 1 0 S0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 1 1 1 0 1 1 1 1 S1 S0 Address data Address data S3 0 0 0 0 0 0 0 0 1 1 1 1 1 S2 parallel conversion) Outputs data on S4 to S15 to pins D0 to D11. Setup (a) A1 selection A2 selection A3 selection A4 selection A5 selection A6 selection A7 selection A8 selection A9 selection A10 selection A11 selection A12 selection I/O expander (serial parallel conversion) I/O expander (parallel serial conversion) I/O expander status setup S3 1 S2 1 S1 0 • I/O expander (parallel S0 1 serial conversion) Writes data on D0 to D11 pins into S4 to S15. When next data communication is provided, outputs data sequentially from SO pin at the rise of the shift clock (CLK). S3 1 S2 1 S1 1 S0 0 • I/O expander status setup register Sets input/output pin of I/O expanders. Data "0": Input mode (Hi-Z status) "1": Output mode S3 1 S2 1 S1 1 S0 1 Data S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 Pin D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DAC data (*) Analog output voltage (Reference S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 X X X X X X X X X 0 0 0 (VDD/256)X1 [V] (1LSB) (VDD/256)X2 [V] (2LSB) (VDD/256)X3 [V] (3LSB) 1 1 X 1 1 X 1 1 X 1 1 X 1 1 X 1 1 X 1 1 X 0 1 X X X X X X X X X X 0 0 1 (VDD/256)X255 [V] (255LSB) VDD [V] (256LSB) Analog output voltage Sets D-A output of A5 to A12 to High-impedance. voltage on the lower side=0.0V fixed) High-impedance (I/O expander selected) X :Don't care (*): Only A5 to A12 outputs are available for DAC output by S4 and Hi-Z conversion. (a) Command to set DAC output to High-impedance (DACHiZ command) S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 X X X X X X X X 1 1 0 1 0 0 0 0 MITSUBISHI (Dig./Ana. INTERFACE) M62376GP 8-BIT 12CH D-A CONVERTER IC BUILT-IN 12-BIT I/O EXPANDER (b) Initial status just after power is turned on: (c) The DACHiZ command is effective only for DAC settings (A5 Low level output from A1 to A4 (set to [00]h) to A12), but not for the I/O ports (D0 to D11) D4/A12 to D11/A5: DAC output of High-impedance (Hi-Z), I/O Note: To change the status of pins D4/A12 to D11/A5, switch both analog of input mode (Hi-Z) D0 to D3 and digital after setup of High-impedance. :input mode (Hi-Z) TIMING CHART (MODEL) EN ••• ••• CLK S0 SI n-1 ••• ••• S15 S0 n-1 n S1 n S2 n S3 ••• PARALLEL INPUT D0 to ( SERIAL OUTPUT) D11 ••• (SERIAL INPUT ) D0 to PARALLEL OUTPUT D11 ••• SO H-Z S15 S0 ••• n-3 n-2 A1 to A12 S15 n-2 H-Z S15 S0 S1 S2 S3 ••• n-2 n-1 n-1 n-1 n-1 ••• S12 S13 S14 S15 n n n n S12 S13 S14 S15 n-1 n-1 n-1 H-Z ••• ABSOLUTE MAXIMUM RATINGS Symbol VCC VDD VIN Vout VIN Vout Pd Topr Tstg Parameter Digital supply voltage Analog supply (D-A converter upper reference voltage) Input voltage Output voltage Input voltage Output voltage Power dissipation Operating temperature Storage temperature Conditions VCC supply side pin VCC supply side pin VDD supply side pin VDD supply side pin Ratings -0.3 to 7.0 Unit V -0.3 to 7.0 V -0.3 to VCC+0.3 -0.3 to VCC+0.3 -0.3 to VDD+0.3 -0.3 to VDD+0.3 200 -20 to +85 -40 to +125 V V V V mW ˚C ˚C MITSUBISHI (Dig./Ana. INTERFACE) M62376GP 8-BIT 12CH D-A CONVERTER IC BUILT-IN 12-BIT I/O EXPANDER ELECTRICAL CHARACTERISTICS RECOMMENDED OPERATING CONDITION Symbol VCC VDD VIN VOUT VIN VOUT Parameter Digital supply voltage Analog supply (D-A converter upper reference voltage) Input pin voltage (VCC part) Output pin voltage (VCC part) Input pin voltage (VDD part) Output pin voltage (VDD part) Conditions Ratings 2.7 to 5.5 Unit V VDD≥VCC 2.7 to 5.5 V EN, SI, D0 to D3 SO, D0 to D3 0 to VCC 0 to VCC 0 to VDD 0 to VDD V V V V RESET, D4/A12 to D11/A5 A1 to A4, D4/A12 to D11/A5 DIGITAL PART [VCC] (VCC=2.7 to 5.5V, Ta=-20 to +85˚C, unless otherwise noted) Symbol VCC ICC IILK VIL VIH VOL VOH VT+ VT- Parameter Supply voltage Supply current Input leak current Input low voltage Input high voltage Output low voltage Output high voltage Forward threshold voltage (EN, CLK) Backward threshold voltage (EN, CLK) Test conditions CLK=1MHz operation, VCC=3V, IAO=0µA VIN=0 to VCC Min. 2.7 – -10 Limits Typ. 3.0 Max. 5.5 2.5 10 0.2VCC 0.5VCC 0.4 IOL=2.5mA IOH=-400µA VCC-0.4 0.5VCC 0.2VCC Unit V mA µA V V V V V V DIGITAL PART [VDD] (VDD=2.7 to 5.5V, Ta=-20 to +85˚C, unless otherwise noted) Symbol VDD IILK VIL VIH VOL VOH Parameter Supply voltage Input leak current Input low voltage Input high voltage Output low voltage Output high voltage Test conditions VIN=0 to VDD Min. 2.7 -10 Limits Typ. 3.0 Max. 5.5 10 0.2VDD 0.5VDD IOL=2.5mA IOH=-400µA 0.4 VDD-0.4 Unit V µA V V V V Note. For circuit current of VDD, see the analog block. ANALOG PART (VDD (VrefU) =2.7 to 5.5V, Ta=-20 to +85˚C, unless otherwise noted) Symbol Parameter IDD Dissipation current VDD (VrefU) D-A converter upper reference voltage range VAO Buffer amplifier output voltage range IAO Buffer amplifier output drive range SDL SL SZERO SFULL CO RO Differential nonlinearity error Nonlinearity error Zero code error Full scale error Output capacitative load Buffer amplifier output impedance Test conditions VrefU=3V input data condition: When maximum current of R-2R rudder is supplied Min. – Limits Typ. Max. 1.5 3.5 mA 5.5 V Unit In the setup range of reference voltage, all values are not taken with output. Values to be taken depend on the item of 2.7 buffer amplifier output voltage range. IAO=±100µA +500µA IAO= -200µA Upper side saturation voltage=0.4V Lower side saturation voltage=0.4V VDD=2.700V (VrefU) Without load (IAO=+0µA) 0.1 VDD-0.1 0.2 VDD-0.2 V -0.3 1 mA -1.0 -1.5 -2.0 -2.0 1.0 1.5 2.0 2.0 10 LSB LSB LSB LSB µF Ω 5 MITSUBISHI (Dig./Ana. INTERFACE) M62376GP 8-BIT 12CH D-A CONVERTER IC BUILT-IN 12-BIT I/O EXPANDER AC ELECTRICAL CHARACTERISTICS (VCC, VDD=2.7 to 5.5V, Ta=-20 to +85˚C, unless otherwise noted) Symbol Parameter tCKL tCKH tCR tCF tDCH tCHD tCLH tCHL tENH tSO tDO Clock low pulse width Clock high pulse width Clock rise time Clock fall time Data setup time Data hold time tLDD D-A output settling time Test conditions CL=100pF CL=100pF CL≤100pF, VAO:0.1 2.6V Until output takes ±2LSB of the final value. OUTPUT DUT CL TIMING CHART tENH EN tCLH tCR tCKH tCF tCHL CLK tCKL SI tDCH tDCH D0 to D11 INPUT tCHD tCHD D0 to D11 OUTPUT tSO tDO SO OUTPUT tLDD A0 to A11 OUTPUT Limits Typ. Max. Unit ns ns 200 ns 350 600 ns ns ns ns ns ns ns 100 µs 30 60 100 200 200 Clock (EN) setup time EN setup time EN high hold time Serial data output delay time Parallel data output delay time INPUT Min. 200 200 MITSUBISHI (Dig./Ana. INTERFACE) M62376GP 8-BIT 12CH D-A CONVERTER IC BUILT-IN 12-BIT I/O EXPANDER APPLICATION EXAMPLE VDD DAC OUTPUT ADJUSTMENT PINS FOR ANALOG IC 1 A1 2 A2 3 4 5 VCC 13 14 VDD VCC (*) RESET 23 A3 EN 22 A4 SO 21 D11/A5 SI 20 6 D10/A6 CLK 19 7 D9/A7 8 D8/A8 D0 18 9 D7/A9 D1 17 10 D6/A10 D2 16 11 D5/A11 D3 15 12 D4/A12 MCU SHARED PINS FOR DAC AND I/O DAC OUTPUT ADJUSTMENT PINS FOR ANALOG IC I/O LOGIC IC COMPARATOR I/O LOGIC IC COMPARATOR GND 24 PRECAUTION FOR USE This IC has two power supply pins and a ground pin. (*) The RESET pin is directly connected with the power pin to Superimposition of these pins with ripple and spike noise may use power-on reset. However, when forced reset is done cause reduction of conversion accuracy and occurrence of from outside, the capacitance (0.1 to 10µF) should be malfunction. Be sure to insert a capacitor between each power connected between RESET pin and ground to remove noise supply and the GND pin to stabilize D-A converting operation. due to installation of line, etc. The output buffer amplifier of this IC has strong characteristics against capacitive load. Accordingly, when the capacitance (10µF MAX.) is connected between output and ground to remove jitter and noise due to installation of output line, no problem may occur in operation of DAC. However, notice that the removal results in lengthening the settling time. This IC also provides power-on reset function. To assure the resetting operation, power supply should be turned on in the order of timing shown in the diagram below. (Order): 1. VCC 2. VDD VDD VCC Time t Fig. 1 Order for power-on