SEMICONDUCTOR TECHNICAL DATA The MC10170 is a 11–bit parity circuit, which is segmented into 9 data bits and 2 control bits. Output A generates odd parity on 9 bits; that is, Output A goes high for an odd number of high logic levels on the bit inputs in only 2 gate delays. The Control Inputs can be used to expand parity to larger numbers of bits with minimal delay or can be used to generate even parity. To expand parity to larger words, the MC10170 can be used with the MC10160 or other MC10170’s. The MC10170 can generate both even and odd parity. L SUFFIX CERAMIC PACKAGE CASE 620–10 PD = 300 mW typ/pkg (No Load) tpd = 2.5 ns typ(Control Inputs to B Output) 4.0 ns typ (Data Inputs to A Output) 6.0 ns typ (Data Inputs to B Output) tr,tf = 2.0 ns typ (20%–80%) P SUFFIX PLASTIC PACKAGE CASE 648–08 PIN ASSIGNMENT LOGIC DIAGRAM CONTROL INPUTS 13 HIGH VCC1 1 16 VCC2 A 2 15 B D0 3 14 LOW D2 5 D1 4 13 HIGH D3 6 D2 5 12 D8 D3 6 11 D7 D4 7 10 D6 VEE 8 9 D5 15 B EVEN PARITY 14 LOW D0 3 D1 4 D4 7 2 A ODD PARITY D5 9 D6 10 VCC1 = PIN 1 VCC2 = PIN 16 VEE = PIN 8 D7 11 D8 12 INPUTS OUTPUTS Sum of D Inputs Inp ts at High Level Odd Parity Even Parity Output A Output B Even Odd Low High High Low 9/96 Motorola, Inc. 1996 3–103 REV 6 MC10170 ELECTRICAL CHARACTERISTICS Test Limits Characteristic Power Supply Drain Current Input Current Symbol Pin Pi Under Test IE 8 78 IinH 3 5 350 350 IinL 3 0.5 –30°C Min +25°C Max Min +85°C Max Unit 71 78 mAdc 200 220 220 220 µAdc Typ Max 57 0.5 Min µAdc 0.3 Output Voltage Logic 1 VOH 2 15 –1.060 –1.060 –0.890 –0.890 –0.960 –0.960 –0.810 –0.810 –0.890 –0.890 –0.700 –0.700 Vdc Output Voltage Logic 0 VOL 2 15 –1.890 –1.890 –1.675 –1.675 –1.850 –1.850 –1.650 –1.650 –1.825 –1.825 –1.615 –1.615 Vdc Threshold Voltage Logic 1 VOHA 2 15 –1.080 –1.080 Threshold Voltage Logic 0 VOLA 2 15 Switching Times –0.980 –0.980 –0.910 –0.910 –1.655 –1.655 –1.630 –1.630 Vdc –1.595 –1.595 (50Ω Load) Propagation Delay ns t13+15+ t14–15– t3+2– t3–15+ 15 15 2 15 1.5 1.5 2.0 4.0 4.2 4.2 6.6 9.5 1.5 1.5 2.0 4.0 2.5 2.5 4.0 6.0 4.0 4.0 6.0 8.8 1.5 1.5 2.0 4.0 4.4 4.4 6.6 9.5 Rise Time (20 to 80%) t2+ 2 1.5 4.3 1.5 2.0 3.9 1.5 4.3 Fall Time (20 to 80%) t2– 2 1.5 4.3 1.5 2.0 3.9 1.5 4.3 MOTOROLA Vdc 3–104 MECL Data DL122 — Rev 6 MC10170 ELECTRICAL CHARACTERISTICS (continued) TEST VOLTAGE VALUES (Volts) Characteristic Power Supply Drain Current Input Current @ Test Temperature VIHmax VILmin VIHAmin VILAmax VEE –30°C –0.890 –1.890 –1.205 –1.500 –5.2 +25°C –0.810 –1.850 –1.105 –1.475 –5.2 +85°C –0.700 –1.825 –1.035 –1.440 –5.2 Symbol Pin Under Test IE 8 IinH 3 5 IinL 3 TEST VOLTAGE APPLIED TO PINS LISTED BELOW VIHmax VILmin VIHAmin VILAmax VEE (VCC) Gnd 1, 16 3 5 3 8 8 1, 16 1, 16 8 1, 16 Output Voltage Logic 1 VOH 2 15 3, 4, 5 14 8 8 1, 16 1, 16 Output Voltage Logic 0 VOL 2 15 4, 5 13, 14 8 8 1, 16 1, 16 Threshold Voltage Logic 1 VOHA 2 15 8 8 1, 16 1, 16 Threshold Voltage Logic 0 VOLA 2 15 5 13 8 8 1, 16 1, 16 Pulse In Pulse Out –3.2 V +2.0 Switching Times (50Ω Load) Propagation Delay Rise Time 5 13 (20 to 80%) t13+15+ t14–15– t3+2– t3–15+ 15 15 2 15 13 14 3 3 15 15 2 15 8 8 8 8 1, 16 1, 16 1, 16 1, 16 t2+ 2 3 2 8 1, 16 Fall Time (20 to 80%) t2– 2 3 2 8 1, 16 Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the same manner. MECL Data DL122 — Rev 6 3–105 MOTOROLA MC10170 OUTLINE DIMENSIONS L SUFFIX CERAMIC DIP PACKAGE CASE 620–10 ISSUE V –A– 16 9 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. –B– C L DIM A B C D E F G H K L M N –T– K N SEATING PLANE M E F J G D 16 PL 0.25 (0.010) 16 PL 0.25 (0.010) M T A T B M –A– 9 1 8 B F C L S –T– SEATING PLANE K H G D M J 16 PL 0.25 (0.010) M MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 ––– 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01 S P SUFFIX PLASTIC DIP PACKAGE CASE 648–08 ISSUE R 16 S INCHES MIN MAX 0.750 0.785 0.240 0.295 ––– 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 T A M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. 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Box 5405, Denver, Colorado 80217. 303–675–2140 or 1–800–441–2447 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 81–3–3521–8315 Mfax: [email protected] – TOUCHTONE 602–244–6609 INTERNET: http://Design–NET.com ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 ◊ MOTOROLA 3–106 *MC10170/D* MC10170/D MECL Data DL122 — Rev 6