SEMICONDUCTOR TECHNICAL DATA The MC100LVEL05 is a 2-input differential AND/NAND gate. The device is functionally equivalent to the MC100EL05 device and operates from a 3.3V supply voltage. With propagation delays and output transition times equivalent to the EL05, the LVEL05 is ideally suited for those applications which require the ultimate in AC performance at low voltage power supplies. Because a negative 2-input NAND is equivalent to a 2-input OR function, the differential inputs and outputs of the device allows the LVEL05 to also be used as a 2-input differential OR/NOR gate. • • • • 340ps Propagation Delay High Bandwidth Output Transitions 75kΩ Internal Input Pulldown Resistors >2000V ESD Protection D SUFFIX 8–LEAD PLASTIC SOIC PACKAGE CASE 751-05 LOGIC DIAGRAM AND PINOUT ASSIGNMENT D0 1 8 VCC D0 2 7 Q D1 3 6 Q D1 4 5 VEE PIN DESCRIPTION PIN FUNCTION D0, D1 Q Data Inputs Data Outputs 1/97 Motorola, Inc. 1997 3–1 REV 0 MC100LVEL05 DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = GND) –40°C Symbol Characteristic IEE Power Supply Current VEE Power Supply Voltage IIH Input HIGH Current IIL Input LOW Current Min 0°C Typ Max 18 25 –3.0 –3.8 Min Typ Max 18 25 –3.0 –3.8 150 0.5 25°C Min Typ Max 18 25 –3.0 –3.8 150 0.5 85°C Min Typ Max Unit 19 26 mA –3.8 V 150 µA –3.0 150 0.5 µA 0.5 AC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = GND) –40°C Symbol Characteristic 0°C Min Typ Max Min 260 440 240 Typ 25°C 85°C Max Min Typ Max Min 440 240 340 440 250 tPLH tPHL Propagation Delay to Output 240 VPP Minimum Input Swing (Note 1.) 150 VCMR Common Mode Range (Note 2.) VPP < 500mV VPP ≥ 500mV –2.1 –1.9 –0.2 –0.2 –2.2 –2.0 –0.2 –0.2 –2.2 –2.0 tr tf Output Rise/Fall Times Q (20% – 80%) 100 320 100 320 100 Typ Max Unit ps 450 mV 150 150 150 V –0.2 –0.2 –2.2 –2.0 –0.2 –0.2 320 100 320 ps 210 1. Minimum input swing for which AC parameters are guaranteed. The device has a DC gain of ≈40. 2. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1V. The lower end of the CMR range varies 1:1 with VEE. The number in the spec table assumes a nominal VEE = –3.3V. Note for PECL operation, the VCMR(min) will be fixed at 3.3V – |VCMR(min)|. MOTOROLA 3–2 ECLinPS and ECLinPS Lite DL140 — Rev 3 MC100LVEL05 OUTLINE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751–05 ISSUE R D A NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS ARE IN MILLIMETERS. 3. DIMENSION D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE MOLD PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. C 8 5 0.25 H E M B M 1 4 h B X 45 _ e q A C SEATING PLANE L 0.10 A1 B 0.25 M C B S A S DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.35 0.49 0.18 0.25 4.80 5.00 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.25 0_ 7_ Motorola reserves the right to make changes without further notice to any products herein. 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How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405; Denver, Colorado 80217. 303–675–2140 or 1–800–441–2447 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 81–3–3521–8315 Mfax: [email protected] – TOUCHTONE 602–244–6609 INTERNET: http://Design–NET.com ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 ◊ ECLinPS and ECLinPS Lite DL140 — Rev 3 3–3 MC100LVEL05/D MOTOROLA