SN54/74LS194A 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER The SN54 / 74LS194A is a High Speed 4-Bit Bidirectional Universal Shift Register. As a high speed multifunctional sequential building block, it is useful in a wide variety of applications. It may be used in serial-serial, shift left, shift right, serial-parallel, parallel-serial, and parallel-parallel data register transfers. The LS194A is similar in operation to the LS195A Universal Shift Register, with added features of shift left without external connections and hold (do nothing) modes of operation. It utilizes the Schottky diode clamped process to achieve high speeds and is fully compatible with all Motorola TTL families. • • • • • Typical Shift Frequency of 36 MHz Asynchronous Master Reset Hold (Do Nothing) Mode Fully Synchronous Serial or Parallel Data Transfers Input Clamp Diodes Limit High Speed Termination Effects 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 620-09 16 1 N SUFFIX PLASTIC CASE 648-08 CONNECTION DIAGRAM DIP (TOP VIEW) VCC Q0 Q1 Q2 Q3 CP S1 S0 16 15 14 13 12 11 10 9 16 1 16 1 1 2 3 4 5 6 7 8 MR DSR P0 P1 P2 P3 DSL GND ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD PIN NAMES LOADING (Note a) HIGH S0, S1 P0 – P3 DSR DSL CP MR Q0 – Q3 Mode Control Inputs Parallel Data Inputs Serial (Shift Right) Data Input Serial (Shift Left) Data Input Clock (Active HIGH Going Edge) Input Master Reset (Active LOW) Input Parallel Outputs (Note b) 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. D SUFFIX SOIC CASE 751B-03 LOW 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 (2.5) U.L. NOTES: a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) b. Temperature Ranges. FAST AND LS TTL DATA 5-360 Ceramic Plastic SOIC SN54/74LS194A LOGIC DIAGRAM FUNCTIONAL DESCRIPTION Q3 outputs respectively following the next LOW to HIGH transition of the clock. The asynchronous Master Reset (MR), when LOW, overrides all other input conditions and forces the Q outputs LOW. Special logic features of the LS194A design which increase the range of application are described below: Two mode control inputs (S0, S 1) determine the synchronous operation of the device. As shown in the Mode Selection Table, data can be entered and shifted from left to right (shift right, Q0 º Q1, etc.) or right to left (shift left, Q3 º Q2, etc.), or parallel data can be entered loading all four bits of the register simultaneously. When both S0 and S1,are LOW, the existing data is retained in a “do nothing” mode without restricting the HIGH to LOW clock transition. D-type serial data inputs (DSR, DSL) are provided on both the first and last stages to allow multistage shift right or shift left data transfers without interfering with parallel load operation. The Logic Diagram and Truth Table indicate the functional characteristics of the LS194A 4-Bit Bidirectional Shift Register. The LS194A is similar in operation to the Motorola LS195A Universal Shift Register when used in serial or parallel data register transfers. Some of the common features of the two devices are described below: All data and mode control inputs are edge-triggered, responding only to the LOW to HIGH transition of the Clock (CP). The only timing restriction, therefore, is that the mode control and selected data inputs must be stable one set-up time prior to the positive transition of the clock pulse. The register is fully synchronous, with all operations taking place in less than 15 ns (typical) making the device especially useful for implementing very high speed CPUs, or the memory buffer registers. The four parallel data inputs (P0, P1, P2, P3) are D-type inputs. When both S0 and S1 are HIGH, the data appearing on P0, P1, P2, and P3 inputs is transferred to the Q0, Q1, Q2, and MODE SELECT — TRUTH TABLE OPERATING MODE INPUTS MR OUTPUTS S0 X DSL Q1 Q2 X X Pn X Q0 L S1 X DSR Reset L L L Q3 L Hold H I I X X X Shift Left H H h h I I X X I h X X q0 q1 q1 q1 q2 q2 q2 q3 q3 q3 L H Shift Right H H I I h h I h X X X X L H q0 q0 q1 q1 q2 q2 Parallel Load H h h X X Pn P0 P1 P2 P3 L = LOW Voltage Level H = HIGH Voltage Level X = Don’t Care I = LOW voltage level one set-up time prior to the LOW to HIGH clock transition h = HIGH voltage level one set-up time prior to the LOW to HIGH clock transition pn (qn) = Lower case letters indicate the state of the referenced input (or output) one set-up time prior to the LOW to HIGH clock transition. FAST AND LS TTL DATA 5-361 SN54/74LS194A GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 74 4.5 4.75 5.0 5.0 5.5 5.25 V TA Operating Ambient Temperature Range 54 74 – 55 0 25 25 125 70 °C IOH Output Current — High 54, 74 – 0.4 mA IOL Output Current — Low 54 74 4.0 8.0 mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Min Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage VOH Output HIGH Voltage VOL Output LOW Voltage IIH Input HIGH Current IIL Input LOW Current IOS Short Circuit Current (Note 1) ICC Power Supply Current Typ Max Unit 2.0 54 0.7 74 0.8 – 0.65 – 1.5 Test Conditions V Guaranteed Input HIGH Voltage for All Inputs V Guaranteed Input LOW Voltage for All Inputs V VCC = MIN, IIN = – 18 mA 54 2.5 3.5 V 74 2.7 3.5 V VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table VCC = VCC MIN, VIN = VIL or VIH per Truth Table 54, 74 0.25 0.4 V IOL = 4.0 mA 74 0.35 0.5 V IOL = 8.0 mA 20 µA VCC = MAX, VIN = 2.7 V 0.1 mA VCC = MAX, VIN = 7.0 V – 0.4 mA VCC = MAX, VIN = 0.4 V – 100 mA VCC = MAX 23 mA VCC = MAX – 20 Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C) Limits Symbol Parameter Min Typ 25 36 Max Unit fMAX Maximum Clock Frequency tPLH tPHL Propagation Delay, Clock to Output 14 17 22 26 ns tPHL Propagation Delay, MR to Output 19 30 ns MHz FAST AND LS TTL DATA 5-362 Test Conditions VCC = 5.0 V CL = 15 pF SN54/74LS194A AC SETUP REQUIREMENTS (TA = 25°C) Limits Symbol Parameter Min Typ Unit Max tW Clock or MR Pulse Width 20 ns ts Mode Control Setup Time 30 ns ts Data Setup Time 20 ns th Hold time, Any Input 0 ns trec Recovery Time 25 ns Test Conditions VCC = 5.0 V DEFINITIONS OF TERMS SETUP TIME(ts) —is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW to HIGH in order to be recognized and transferred to the outputs. HOLD TIME (th) — is defined as the minimum time following the clock transition from LOW to HIGH that the logic level must be maintained at the input in order to ensure continued recognition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW to HIGH and still be recognized. RECOVERY TIME (trec) — is defined as the minimum time required between the end of the reset pulse and the clock transition from LOW to HIGH in order to recognize and transfer HIGH Data to the Q outputs. AC WAVEFORMS The shaded areas indicate when the input is permitted to change for predictable output performance. (*%. " " -# - - ! ! " " " -, -, -) Figure 1. Clock to Output Delays Clock Pulse Width and fmax -) -, -, -) -) " " ! ! " /! /! -+'& -# $ $ Figure 3. Setup (ts) and Hold (th) Time for Serial Data (DSR, DSL) and Parallel Data (P0, P1, P2, P3) " - ! ! " " -, -, -) Figure 2. Master Reset Pulse Width, Master Reset to Output Delay and Master Reset to Clock Recovery Time -) " " Figure 4. Setup (ts) and Hold (th) Time for S Input FAST AND LS TTL DATA 5-363 Case 751B-03 D Suffix 16-Pin Plastic SO-16 -A- "! ! " " ! " # 1 %# ) ! !" $ !" 8 C -T- D M K " ! #! J F ! Case 648-08 N Suffix 16-Pin Plastic R X 45° G " ! ) #! P ! " " 9 -B- ! 16 & ! ! ° ° ° ° ( ( ( ( "! ! " " ! ! ' " " ! ' ! " # & -A- 16 9 1 8 ! ! $ ! B # ) " ! " # ) !" $ !" ) F L C S -T- K H G M J D " Case 620-09 J Suffix 16-Pin Ceramic Dual In-Line -A- ! ! ! ! ° ° ° ° "! ! " 16 " ) " L K M N J G D " $ " $ ! " " ! ! FAST AND LS TTL DATA 5-364 & # ) !" $ !" ) -T $ " " C F & 8 E ! ! ! " " -B1 & 9 * * ! ! ! ! * * ! ° ° ! ° ° Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. 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ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. ◊ FAST AND LS TTL DATA 5-365