MOTOROLA MLP1N06

MOTOROLA
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by MLP1N06CL/D
SEMICONDUCTOR TECHNICAL DATA
SMARTDISCRETES 
Internally Clamped, Current Limited
N–Channel Logic Level Power MOSFET
These SMARTDISCRETES devices feature current limiting for short circuit
protection, an integral gate–to–source clamp for ESD protection and gate–to–drain
clamp for over–voltage protection. No additional gate series resistance is required
when interfacing to the output of a MCU, but a 40 kΩ gate pulldown resistor is
recommended to avoid a floating gate condition.
The internal gate–to–source and gate–to–drain clamps allow the devices to be
applied without use of external transient suppression components. The gate–to–
source clamp protects the MOSFET input from electrostatic gate voltage stresses
up to 2.0 kV. The gate–to–drain clamp protects the MOSFET drain from drain
avalanche stresses that occur with inductive loads. This unique design provides
voltage clamping that is essentially independent of operating temperature.
The MLP1N06CL is fabricated using Motorola’s SMARTDISCRETES technology which combines the advantages of a power MOSFET output device with
on–chip protective circuitry. This approach offers an economical means for
providing additional functions that protect a power MOSFET in harsh automotive
and industrial environments. SMARTDISCRETES devices are specified over a
wide temperature range from –50°C to 150°C.
MLP1N06CL
Motorola Preferred Device
VOLTAGE CLAMPED
CURRENT LIMITING
MOSFET
62 VOLTS (CLAMPED)
RDS(on) = 0.75 OHMS
D
R1
G
• Temperature Compensated Gate–to–Drain Clamp Limits Voltage Stress
Applied to the Device and Protects the Load From Overvoltage
• Integrated ESD Diode Protection
• Controlled Switching Minimizes RFI
R2
S
• Low Threshold Voltage Enables Interfacing Power Loads to Microprocessors
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Symbol
Value
Unit
Drain–to–Source Voltage
VDSS
Clamped
Vdc
Drain–to–Gate Voltage (RGS = 1.0 MΩ)
VDGR
Clamped
Vdc
Gate–to–Source Voltage — Continuous
VGS
±10
Vdc
Drain Current — Continuous
Drain Current — Single Pulse
ID
IDM
Self–limited
1.8
Adc
Rating
Total Power Dissipation
PD
40
Watts
Electrostatic Discharge Voltage (Human Body Model)
ESD
2.0
kV
Operating and Storage Junction Temperature Range
TJ, Tstg
–50 to 150
°C
3.12
62.5
°C/W
260
°C
G
D
S
THERMAL CHARACTERISTICS
RθJC
RθJA
Thermal Resistance, Junction to Case
Thermal Resistance, Junction to Ambient
Maximum Lead Temperature for Soldering Purposes,
1/8″ from case
TL
CASE 221A–06, Style 5
TO–220AB
UNCLAMPED DRAIN–TO–SOURCE AVALANCHE CHARACTERISTICS
Single Pulse Drain–to–Source Avalanche Energy
(Starting TJ = 25°C, ID = 2.0 A, L = 40 mH) (Figure 6)
EAS
80
mJ
SMARTDISCRETES is a trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 1
TMOS
Motorola
Motorola, Inc.
1996 Power MOSFET Transistor Device Data
1
MLP1N06CL
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Symbol
Characteristic
Min
Typ
Max
Unit
59
59
62
62
65
65
—
—
0.6
6.0
5.0
20
—
—
0.5
1.0
5.0
20
1.0
0.6
1.5
—
2.0
1.6
—
—
—
—
0.63
0.59
1.1
1.0
0.75
0.75
1.9
1.8
gFS
1.0
1.4
—
mhos
VSD
—
1.1
1.5
Vdc
2.0
1.1
2.3
1.3
2.75
1.8
td(on)
—
1.2
2.0
tr
—
4.0
6.0
td(off)
—
4.0
6.0
tf
—
3.0
5.0
OFF CHARACTERISTICS
Drain–to–Source Sustaining Voltage (Internally Clamped)
(ID = 20 mA, VGS = 0)
(ID = 20 mA, VGS = 0, TJ = 150°C)
V(BR)DSS
Vdc
µAdc
Zero Gate Voltage Drain Current
(VDS = 45 V, VGS = 0)
(VDS = 45 V, VGS = 0, TJ = 150°C)
IDSS
Gate–Body Leakage Current
(VG = 5.0 V, VDS = 0)
(VG = 5.0 V, VDS = 0, TJ = 150°C)
IGSS
µAdc
ON CHARACTERISTICS*
Gate Threshold Voltage
(ID = 250 µA, VDS = VGS)
(ID = 250 µA, VDS = VGS, TJ = 150°C)
VGS(th)
Static Drain–to–Source On–Resistance
(ID = 1.0 A, VGS = 4.0 V)
(ID = 1.0 A, VGS = 5.0 V)
(ID = 1.0 A, VGS = 4.0 V, TJ = 150°C)
(ID = 1.0 A, VGS = 5.0 V, TJ = 150°C)
RDS(on)
Forward Transconductance (ID = 1.0 A, VDS = 10 V)
Static Source–to–Drain Diode Voltage (IS = 1.0 A, VGS = 0)
Static Drain Current Limit
(VGS = 5.0 V, VDS = 10 V)
(VGS = 5.0 V, VDS = 10 V, TJ = 150°C)
Vdc
Ohms
ID(lim)
A
RESISTIVE SWITCHING CHARACTERISTICS*
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
(VDD = 25 V, ID = 1.0 A,
VGS = 5.0 V, RG = 50 Ohms)
Fall Time
µs
* Indicates Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%.
TJ = 25°C
3
10 V
6V
8V
4V
2
VGS = 3 V
1
0
–50°C
3
25°C
2
TJ = 150°C
1
0
0
2
4
6
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 1. Output Characteristics
2
VDS ≥ 7.5 V
4
ID , DRAIN CURRENT (AMPS)
ID , DRAIN CURRENT (AMPS)
4
8
0
2
4
6
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
8
Figure 2. Transfer Function
Motorola TMOS Power MOSFET Transistor Device Data
MLP1N06CL
Motorola TMOS Power MOSFET Transistor Device Data
ID(lim) , DRAIN CURRENT (AMPS)
4
VGS = 5 V
VDS = 7.5 V
3
2
1
0
–50
0
50
100
TJ, JUNCTION TEMPERATURE (°C)
150
Figure 3. ID(lim) Variation With Temperature
R DS(on), ON–RESISTANCE (OHMS)
4
ID = 1 A
3
2
25°C
150°C
TJ = –50°C
1
0
0
2
4
6
8
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
10
Figure 4. RDS(on) Variation With
Gate–To–Source Voltage
1.25
ID = 1 A
RDS(on), ON–RESISTANCE (OHMS)
THE SMARTDISCRETES CONCEPT
From a standard power MOSFET process, several active
and passive elements can be obtained that provide on–chip
protection to the basic power device. Such elements require
only a small increase in silicon area and/or the addition of one
masking layer to the process. The resulting device exhibits
significant improvements in ruggedness and reliability as well
as system cost reduction. The SMARTDISCRETES device
functions can now provide an economical alternative to smart
power ICs for power applications requiring low on–resistance,
high voltage and high current.
These devices are designed for applications that require a
rugged power switching device with short circuit protection
that can be directly interfaced to a microcontroller unit
(MCU). Ideal applications include automotive fuel injector
driver, incandescent lamp driver or other applications where
a high in–rush current or a shorted load condition could occur.
OPERATION IN THE CURRENT LIMIT MODE
The amount of time that an unprotected device can withstand the current stress resulting from a shorted load before
its maximum junction temperature is exceeded is dependent
upon a number of factors that include the amount
of heatsinking that is provided, the size or rating of the device, its initial junction temperature, and the supply voltage.
Without some form of current limiting, a shorted load can
raise a device’s junction temperature beyond the maximum
rated operating temperature in only a few milliseconds.
Even with no heatsink, the MLP1N06CL can withstand a
shorted load powered by an automotive battery (10 to 14
Volts) for almost a second if its initial operating temperature
is under 100°C. For longer periods of operation in the current–limited mode, device heatsinking can extend operation
from several seconds to indefinitely depending on the
amount of heatsinking provided.
SHORT CIRCUIT PROTECTION AND THE EFFECT OF
TEMPERATURE
The on–chip circuitry of the MLP1N06CL offers an integrated means of protecting the MOSFET component from
high in–rush current or a shorted load. As shown in the schematic diagram, the current limiting feature is provided by an
NPN transistor and integral resistors R1 and R2. R2 senses
the current through the MOSFET and forward biases the
NPN transistor’s base as the current increases. As the NPN
turns on, it begins to pull gate drive current through R1, dropping the gate drive voltage across it, and thus lowering the
voltage across the gate–to–source of the power MOSFET
and limiting the current. The current limit is temperature dependent as shown in Figure 3, and decreases from about 2.3
Amps at 25°C to about 1.3 Amps at 150°C.
Since the MLP1N06CL continues to conduct current and
dissipate power during a shorted load condition, it is important to provide sufficient heatsinking to limit the device junction temperature to a maximum of 150°C.
The metal current sense resistor R2 adds about 0.4 ohms
to the power MOSFET’s on–resistance, but the effect of temperature on the combination is less than on a standard
MOSFET due to the lower temperature coefficient of R2. The
on–resistance variation with temperature for gate voltages of
4 and 5 Volts is shown in Figure 5.
Back–to–back polysilicon diodes between gate and source
provide ESD protection to greater than 2 kV, HBM. This on–
chip protection feature eliminates the need for an external
Zener diode for systems with potentially heavy line transients.
1
VGS = 4 V
0.75
VGS = 5 V
0.5
0.25
–50
0
50
100
TJ, JUNCTION TEMPERATURE (°C)
150
Figure 5. On–Resistance Variation With
Temperature
3
100
80
60
40
20
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
150
BV(DSS) , DRAIN–SOURCE SUSTAINING VOLTAGE (VOLTS)
WAS , SINGLE PULSE AVALANCHE ENERGY (mJ)
MLP1N06CL
64
63
62
61
60
–50
Figure 6. Single Pulse Avalanche Energy
versus Junction Temperature
FORWARD BIASED SAFE OPERATING AREA
The FBSOA curves define the maximum drain–to–source
voltage and drain current that a device can safely handle
when it is forward biased, or when it is on, or being turned on.
Because these curves include the limitations of simultaneous
high voltage and high current, up to the rating of the device,
they are especially useful to designers of linear systems. The
curves are based on a case temperature of 25°C and a maximum junction temperature of 150°C. Limitations for repetitive
pulses at various case temperatures can be determined by
using the thermal response curves. Motorola Application
Note, AN569, “Transient Thermal Resistance — General
Data and Its Use” provides detailed instructions.
0
50
100
TJ, JUNCTION TEMPERATURE (°C)
150
Figure 7. Drain–Source Sustaining
Voltage Variation With Temperature
DUTY CYCLE OPERATION
When operating in the duty cycle mode, the maximum
drain voltage can be increased. The maximum operating
temperature is related to the duty cycle (DC) by the following
equation:
TC = (VDS x ID x DC x RθCA) + TA
The maximum value of VDS applied when operating in a
duty cycle mode can be approximated by:
VDS =
150 – TC
ID(lim) x DC x RθJC
10
MAXIMUM DC VOLTAGE CONSIDERATIONS
The maximum drain–to–source voltage that can be continuously applied across the MLP1N06CL when it is in current
limit is a function of the power that must be dissipated. This
power is determined by the maximum current limit at maximum rated operating temperature (1.8 A at 150°C) and not
the RDS(on). The maximum voltage can be calculated by the
following equation:
Vsupply =
(150 – TA)
ID(lim) (RθJC + RθCA)
where the value of RθCA is determined by the heatsink that is
being used in the application.
4
I D , DRAIN CURRENT (AMPS)
6
ID(lim) – MAX
3
2
1 ms
1.5
ms
5 ms
ID(lim) – MIN
dc
1
0.6
DEVICE/POWER LIMITED
RDS(on) LIMITED
0.3
VGS = 5 V
SINGLE PULSE
TC = 25°C
0.2
0.1
1
2
3
6
10
20
30
60
100
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 8. Maximum Rated Forward Bias
Safe Operating Area (MLP1N06CL)
Motorola TMOS Power MOSFET Transistor Device Data
r(t), EFFECTIVE TRANSIENT THERMAL
RESISTANCE (NORMALIZED)
MLP1N06CL
1.0
0.7
0.5
D = 0.5
0.3
0.2
0.2
RθJC(t) = r(t) RθJC
RθJC(t) = 3.12°C/W Max
D Curves Apply for Power
Pulse Train Shown
Read Time at t1
TJ(pk) – TC = P(pk) RθJC(t)
0.1
0.1
0.07
0.05
0.05
0.02
P(pk)
0.03
t1
0.01
t2
DUTY CYCLE, D =t1/t2
0.02
0.01
0.01
SINGLE PULSE
0.02 0.03 0.05
0.1
0.2
0.3
0.5
1.0
2.0
3.0
5.0
10
20
30
50
100
200 300
500
1000
t, TIME (ms)
Figure 9. Thermal Response (MLP1N06CL)
ton
VDD
RL
Vin
PULSE GENERATOR
Rgen
Vout
td(on)
toff
tr
90%
td(off)
tf
90%
DUT
OUTPUT, Vout
INVERTED
z = 50 Ω
10%
50Ω
90%
50 Ω
50%
INPUT, Vin
Figure 10. Switching Test Circuit
ACTIVE CLAMPING
SMARTDISCRETES technology can provide on–chip realization of the popular gate–to–source and gate–to–drain
Zener diode clamp elements. Until recently, such features
have been implemented only with discrete components
which consume board space and add system cost. The
SMARTDISCRETES technology approach economically
melds these features and the power chip with only a slight
increase in chip area.
In practice, back–to–back diode elements are formed in a
polysilicon region monolithicly integrated with, but electrically
isolated from, the main device structure. Each back–to–back
diode element provides a temperature compensated voltage
element of about 7.2 volts. As the polysilicon region is
formed on top of silicon dioxide, the diode elements are free
from direct interaction with the conduction regions of the
power device, thus eliminating parasitic electrical effects
while maintaining excellent thermal coupling.
To achieve high gate–to–drain clamp voltages, several
voltage elements are strung together; the MLP1N06CL uses
8 such elements. Customarily, two voltage elements are
used to provide a 14.4 volt gate–to–source voltage clamp.
For the MLP1N06CL, the integrated gate–to–source voltage
Motorola TMOS Power MOSFET Transistor Device Data
50%
PULSE WIDTH
10%
Figure 11. Switching Waveforms
elements provide greater than 2.0 kV electrostatic voltage
protection.
The avalanche voltage of the gate–to–drain voltage clamp
is set less than that of the power MOSFET device. As soon
as the drain–to–source voltage exceeds this avalanche voltage, the resulting gate–to–drain Zener current builds a gate
voltage across the gate–to–source impedance, turning on
the power device which then conducts the current. Since virtually all of the current is carried by the power device, the
gate–to–drain voltage clamp element may be small in size.
This technique of establishing a temperature compensated
drain–to–source sustaining voltage (Figure 7) effectively removes the possibility of drain–to–source avalanche in the
power device.
The gate–to–drain voltage clamp technique is particularly
useful for snubbing loads where the inductive energy would
otherwise avalanche the power device. An improvement in
ruggedness of at least four times has been observed when
inductive energy is dissipated in the gate–to–drain clamped
conduction mode rather than in the more stressful gate–to–
source avalanche mode.
5
MLP1N06CL
TYPICAL APPLICATIONS: INJECTOR DRIVER, SOLENOIDS, LAMPS, RELAY COILS
The MLP1N06CL has been designed to allow direct interface to the output of a microcontrol unit to control an isolated
load. No additional series gate resistance is required, but a
40 kΩ gate pulldown resistor is recommended to avoid a
floating gate condition in the event of an MCU failure. The internal clamps allow the device to be used without any external transistent suppressing components.
VBAT
VDD
D
G
MCU
MLP1N06CL
S
PACKAGE DIMENSIONS
–T–
B
C
F
T
S
SEATING
PLANE
STYLE 5:
PIN 1.
2.
3.
4.
4
1 2 3
U
H
K
Z
L
R
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
DIM
A
B
C
D
F
G
H
J
K
L
N
Q
R
S
T
U
V
Z
A
Q
GATE
DRAIN
SOURCE
DRAIN
J
G
D
N
INCHES
MIN
MAX
0.570
0.620
0.380
0.405
0.160
0.190
0.025
0.035
0.142
0.147
0.095
0.105
0.110
0.155
0.018
0.025
0.500
0.562
0.045
0.060
0.190
0.210
0.100
0.120
0.080
0.110
0.045
0.055
0.235
0.255
0.000
0.050
0.045
–––
–––
0.080
MILLIMETERS
MIN
MAX
14.48
15.75
9.66
10.28
4.07
4.82
0.64
0.88
3.61
3.73
2.42
2.66
2.80
3.93
0.46
0.64
12.70
14.27
1.15
1.52
4.83
5.33
2.54
3.04
2.04
2.79
1.15
1.39
5.97
6.47
0.00
1.27
1.15
–––
–––
2.04
CASE 221A–06
ISSUE Y
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6
◊
*MLP1N06CL/D*
Motorola TMOS Power MOSFET Transistor
Device Data
MLP1N06CL/D