MOTOROLA MTP10N10E

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by MTP10N10E/D
SEMICONDUCTOR TECHNICAL DATA
 N–Channel Enhancement–Mode Silicon Gate
This advanced “E” series of TMOS power MOSFETs is designed
to withstand high energy in the avalanche and commutation
modes. These new energy efficient devices also offer drain–to–
source diodes with fast recovery times. Designed for low voltage,
high speed switching applications in power supplies, converters
and PWM motor controls, these devices are particularly well suited
for bridge circuits where diode speed and commutating safe
operating area are critical, and offer additional safety margin
against unexpected voltage transients.
• Internal Source–to–Drain Diode Designed to Replace External
Zener Transient Suppressor — Absorbs High Energy in the
Avalanche Mode — Unclamped Inductive Switching (UIS)
Energy Capability Specified at 100°C
• Commutating Safe Operating Area (CSOA) Specified for Use
in Half and Full Bridge Circuits
• Source–to–Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
TMOS POWER FETs
10 AMPERES
100 VOLTS
RDS(on) = 0.25 OHM

D
G
S
CASE 221A–06, Style 5
TO–220AB
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Symbol
Value
Unit
Drain–Source Voltage
VDSS
100
Vdc
Drain–Gate Voltage (RGS = 1.0 MΩ)
VDGR
100
Vdc
Gate–Source Voltage
VGS
± 20
Vdc
Drain Current — Continuous
Drain Current — Pulsed
ID
IDM
10
25
Adc
Total Power Dissipation
Derate above 25°C
PD
75
0.6
Watts
W/°C
TJ, Tstg
– 65 to 150
°C
RθJC
RθJA
1.67
62.5
°C/W
TL
275
°C
Rating
Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient°
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 5 seconds
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Designer’s is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
TMOS
 Motorola
Motorola, Inc.
1996
Power MOSFET Transistor Device Data
1
MTP10N10E
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Max
Unit
V(BR)DSS
100
—
Vdc
—
—
10
80
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage
(VGS = 0, ID = 0.25 mA)
Zero Gate Voltage Drain Current
(VDS = Rated VDSS, VGS = 0)
(VDS = 0.8 Rated VDSS, VGS = 0, TJ = 125°C)
µA
IDSS
Gate–Body Leakage Current, Forward (VGSF = 20 Vdc, VDS = 0)
IGSSF
—
100
nAdc
Gate–Body Leakage Current, Reverse (VGSR = 20 Vdc, VDS = 0)
IGSSR
—
100
nAdc
2.0
1.5
4.5
4.0
—
0.25
—
—
2.7
2.4
4.0
—
—
—
—
60
100
40
Ciss
—
600
Coss
—
400
Crss
—
100
td(on)
—
50
tr
—
80
td(off)
—
100
ON CHARACTERISTICS*
Gate Threshold Voltage
(VDS = VGS, ID = 1.0 mA)
TJ = 100°C
VGS(th)
Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 5.0 Adc)
RDS(on)
Drain–Source On–Voltage (VGS = 10 V)
(ID = 10 Adc)°
(ID = 5.0 Adc, TJ = 100°C)
VDS(on)
gFS
Forward Transconductance (VDS = 15 V, ID = 5.0 A)
Vdc
Ohm
Vdc
mhos
DRAIN–TO–SOURCE AVALANCHE CHARACTERISTICS
Unclamped Drain–to–Source Avalanche Energy See Figures 14 and 15
(ID = 25 A, VDD = 25 V, TC = 25°C, Single Pulse, Non–repetitive)
(ID = 10 A, VDD = 25 V, TC = 25°C, P.W. ≤ 200 µs, Duty Cycle ≤ 1%)
(ID = 4.0 A, VDD = 25 V, TC = 100°C, P.W. ≤ 200 µs, Duty Cycle ≤ 1%)
WDSR
mJ
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
(VDS = 25 V, VGS = 0,
f = 1.0 MHz)
See Figure 16
pF
SWITCHING CHARACTERISTICS* (TJ = 100°C)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
(VDD = 25 V, ID = 5.0 A,
RG = 50 Ω)
See Figure 9
Fall Time
Total Gate Charge
Gate–Source Charge
Gate–Drain Charge
(VDS = 0.8 Rated VDSS,
ID = Rated ID, VGS = 10 V)
See Figures 17 and 18
tf
—
80
Qg
15 (Typ)
30
Qgs
8.0 (Typ)
—
Qgd
7.0 (Typ)
—
VSD
1.4 (Typ)
1.7
ns
nC
SOURCE–DRAIN DIODE CHARACTERISTICS*
Forward On–Voltage
Forward Turn–On Time
(IS = Rated ID
VGS = 0)
Reverse Recovery Time
ton
trr
Vdc
Limited by stray inductance
70 (Typ)
—
3.5 (Typ)
4.5 (Typ)
—
—
7.5 (Typ)
—
ns
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the contact screw on tab to center of die)″
(Measured from the drain lead 0.25″ from package to center of die)
Ld
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
Ls
nH
* Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%.
2
Motorola TMOS Power MOSFET Transistor Device Data
MTP10N10E
I D, DRAIN CURRENT (AMPS)
20
VGS = 10 V
8V
TJ = 25°C
7V
16
6V
12
8
5V
4
4V
0
4
8
12
16
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
20
VGS(th), GATE THRESHOLD VOLTAGE (NORMALIZED)
TYPICAL ELECTRICAL CHARACTERISTICS
1.2
1
0.9
0.8
0.7
–50
20
I D, DRAIN CURRENT (AMPS)
TJ = –55°C
VDS = 10 V
VDS = 15 V
12
100°C
8
+25°C
4
0
0
2
4
6
8
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
10
RDS(on) , DRAIN–TO–SOURCE RESISTANCE
(NORMALIZED)
RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
0.4
TJ = 100°C
25°C
–55°C
0.1
2
4
6
8
150
1.6
VGS = 0 V
ID = 0.25 mA
1.2
0.8
0.4
0
–50
0
50
100
150
200
Figure 4. Breakdown Voltage Variation
With Temperature
VGS = 10 V
0
125
TJ, JUNCTION TEMPERATURE (°C)
0.5
0.2
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
2
Figure 3. Transfer Characteristics
0.3
–25
Figure 2. Gate–Threshold Voltage Variation
With Temperature
VBR(DSS), DRAIN–TO–SOURCE BREAKDOWN VOLTAGE
(NORMALIZED)
Figure 1. On–Region Characteristics
16
VDS = VGS
ID = 1 mA
1.1
10
2
1.6
VGS = 10 V
ID = 5 mA
1.2
0.8
0.4
0
–50
0
50
100
150
ID, DRAIN CURRENT (AMPS)
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. On–Resistance versus Drain Current
Figure 6. On–Resistance Variation
With Temperature
Motorola TMOS Power MOSFET Transistor Device Data
200
3
MTP10N10E
SAFE OPERATING AREA INFORMATION
40
10 µs
100 µs
10
1 ms
VGS = 20 V
SINGLE PULSE
TC = 25°C
3
10 ms
dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1
0.3
I D, DRAIN CURRENT (AMPS)
I D, DRAIN CURRENT (AMPS)
30
TJ ≤ 150°C
30
20
10
0
10
100
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
1
0
20
40
60
80
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7. Maximum Rated Forward Biased
Safe Operating Area
Figure 8. Maximum Rated Switching
Safe Operating Area
The FBSOA curves define the maximum drain–to–source
voltage and drain current that a device can safely handle
when it is forward biased, or when it is on, or being turned on.
Because these curves include the limitations of simultaneous
high voltage and high current, up to the rating of the device,
they are especially useful to designers of linear systems. The
curves are based on a case temperature of 25°C and a maximum junction temperature of 150°C. Limitations for repetitive
pulses at various case temperatures can be determined by
using the thermal response curves. Motorola Application
Note, AN569, “Transient Thermal Resistance–General Data
and Its Use” provides detailed instructions.
SWITCHING SAFE OPERATING AREA
r(t), TRANSIENT THERMAL RESISTANCE
(NORMALIZED)
The switching safe operating area (SOA) of Figure 8 is the
boundary that the load line may traverse without incurring
damage to the MOSFET. The fundamental limits are the
peak current, IDM and the breakdown voltage, V(BR)DSS. The
switching SOA shown in Figure 8 is applicable for both turn–
on and turn–off of the devices for switching times less than
one microsecond.
The power averaged over a complete switching cycle must
be less than:
TJ(max) – TC
RθJC
1K
td(off)
VDD = 25 V
ID = 5 A
VGS = 10 V
TJ = 25°C
500
300
200
t, TIME (ns)
FORWARD BIASED SAFE OPERATING AREA
1
0.7
0.5
100
100
70
50
30
20
tf
tr
td(on)
10
7
5
3
2
1
1
2 3
5
10
20 30 50 100 200 300 500
RG, GATE RESISTANCE (OHMS)
1K
Figure 9. Resistive Switching Time
versus Gate Resistance
D = 0.5
0.3
0.2
0.2
0.1
0.1
0.07
0.05
0.03
P(pk)
0.05
0.01
t1
t2
DUTY CYCLE, D = t1/t2
0.02
SINGLE PULSE
0.01
0.01
0.02 0.03 0.05
0.1
0.2 0.3
0.5
1
2 3
5
t, TIME (ms)
10
20
30
RθJC(t) = r(t) RθJC
RθJC = 1.67°C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) – TC = P(pk) RθJC(t)
50
100
200 300
500
1000
Figure 10. Thermal Response
4
Motorola TMOS Power MOSFET Transistor Device Data
MTP10N10E
COMMUTATING SAFE OPERATING AREA (CSOA)
The Commutating Safe Operating Area (CSOA) of Figure
12 defines the limits of safe operation for commutated
source-drain current versus re-applied drain voltage when
the source-drain diode has undergone forward bias. The
curve shows the limitations of IFM and peak VDS for a given
rate of change of source current. It is applicable when waveforms similar to those of Figure 11 are present. Full or halfbridge PWM DC motor controllers are common applications
requiring CSOA data.
Device stresses increase with increasing rate of change of
source current so dIs/dt is specified with a maximum value.
Higher values of dIs/dt require an appropriate derating of IFM,
peak VDS or both. Ultimately dIs/dt is limited primarily by device, package, and circuit impedances. Maximum device
stress occurs during trr as the diode goes from conduction to
reverse blocking.
VDS(pk) is the peak drain–to–source voltage that the device
must sustain during commutation; IFM is the maximum forward source-drain diode current just prior to the onset of
commutation.
VR is specified at 80% of V(BR)DSS to ensure that the
CSOA stress is maximized as IS decays from IRM to zero.
RGS should be minimized during commutation. TJ has only
a second order effect on CSOA.
Stray inductances in Motorola’s test circuit are assumed to
be practical minimums. dVDS/dt in excess of 10 V/ns was attained with dIs/dt of 400 A/µs.
15 V
VGS
0
IFM
IS
10%
trr
ton
IRM
0.25 IRM
VDS(pk)
VR
VDS
dVDS/dt
VdsL
Vf
MAX. CSOA
STRESS AREA
Figure 11. Commutating Waveforms
RGS
VR
+
IFM
IS
+
20
20 V
–
VGS
Li
VDS
25
15
VR = 80% OF RATED VDS
VdsL = Vf + Li ⋅ dls/dt
dIs/dt ≤ 400 A/µs
10
Figure 13. Commutating Safe Operating Area
Test Circuit
5
0
DUT
–
30
IS , SOURCE CURRENT (AMPS)
dls/dt
90%
100
20
40
60
80
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
0
120
V(BR)DSS
Vds(t)
Figure 12. Commutating Safe Operating Area (CSOA)
IO
L
VDS
ID
ID(t)
C
4700 µF
250 V
VDD
t
RGS
50 Ω
Figure 14. Unclamped Inductive Switching
Test Circuit
Motorola TMOS Power MOSFET Transistor Device Data
VDD
WDSR
ǒ Ǔǒ
Ǔ
t, (TIME)
tP
+
1 LI 2
O
2
V(BR)DSS
V(BR)DSS – VDD
Figure 15. Unclamped Inductive Switching
Waveforms
5
MTP10N10E
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
1250
TJ = 25°C
Ciss
C, CAPACITANCE (pF)
1000
Coss
750
500
Ciss
250
Coss
Crss
0
20
10
0
10
20
30
10
50 V
80 V
6
4
ID = RATED ID
2
0
0
4
8
12
QG, TOTAL GATE CHARGE (nC)
VGS
VDS
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 16. Capacitance Variation
16
20
Figure 17. Gate Charge versus
Gate–To–Source Voltage
+18 V
VDD
1 mA
47 k
Vin
TJ = 25°C
VDS = 30 V
8
10 V
15 V
SAME
DEVICE TYPE
AS DUT
100 k
2N3904
0.1 µF
2N3904
100 k
47 k
100
FERRITE
BEAD
DUT
Vin = 15 Vpk; PULSE WIDTH ≤ 100 µs, DUTY CYCLE ≤ 10%
Figure 18. Gate Charge Test Circuit
6
Motorola TMOS Power MOSFET Transistor Device Data
MTP10N10E
PACKAGE DIMENSIONS
–T–
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
SEATING
PLANE
C
F
T
S
4
A
Q
1 2 3
STYLE 5:
PIN 1.
2.
3.
4.
U
H
K
Z
L
R
V
J
G
D
N
GATE
DRAIN
SOURCE
DRAIN
DIM
A
B
C
D
F
G
H
J
K
L
N
Q
R
S
T
U
V
Z
INCHES
MIN
MAX
0.570
0.620
0.380
0.405
0.160
0.190
0.025
0.035
0.142
0.147
0.095
0.105
0.110
0.155
0.018
0.025
0.500
0.562
0.045
0.060
0.190
0.210
0.100
0.120
0.080
0.110
0.045
0.055
0.235
0.255
0.000
0.050
0.045
–––
–––
0.080
MILLIMETERS
MIN
MAX
14.48
15.75
9.66
10.28
4.07
4.82
0.64
0.88
3.61
3.73
2.42
2.66
2.80
3.93
0.46
0.64
12.70
14.27
1.15
1.52
4.83
5.33
2.54
3.04
2.04
2.79
1.15
1.39
5.97
6.47
0.00
1.27
1.15
–––
–––
2.04
CASE 221A–06
ISSUE Y
Motorola TMOS Power MOSFET Transistor Device Data
7
MTP10N10E
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different
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8
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*MTP10N10E/D*
Motorola TMOS Power MOSFET Transistor
Device Data
MTP10N10E/D