MOTOROLA MTP75N05HD

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SEMICONDUCTOR TECHNICAL DATA
 
Motorola Preferred Device
N–Channel Enhancement–Mode Silicon Gate
TMOS POWER FET
75 AMPERES
RDS(on) = 9.5 mΩ
50 VOLTS
This advanced high–cell density HDTMOS E–FET is designed to
withstand high energy in the avalanche and commutation modes.
This new energy–efficient design also offers a drain–to–source
diode with a fast recovery time. Designed for low–voltage,
high–speed switching applications in power supplies, converters
and PWM motor controls, and other inductive loads. The avalanche
energy capability is specified to eliminate the guesswork in designs
where inductive loads are switched, and to offer additional safety
margin against unexpected voltage transients.
•
•
•
•
•
•

Ultra Low RDS(on), High–Cell Density, HDTMOS
SPICE Parameters Available
Diode is Characterized for Use in Bridge Circuits
Diode Exhibits High Speed, Yet Soft Recovery
IDSS and VDS(on) Specified at Elevated Temperature
Avalanche Energy Specified
D
G
CASE 221A–06, Style 5
TO–220AB
S
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–Source Voltage
VDSS
50
Vdc
Drain–Gate Voltage (RGS = 1.0 MΩ)
VDGR
50
Vdc
Gate–Source Voltage — Continuous
VGS
± 20
Vdc
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)
ID
ID
IDM
75
65
225
Adc
Total Power Dissipation
Derate above 25°C
PD
150
1
Watts
W/°C
TJ, Tstg
– 55 to 175
°C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vpk, IL = 75 Apk, L = 0.177 mH, RG = 25 Ω)
EAS
500
mJ
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
RθJC
RθJA
1.00
62.5
°C/W
TL
260
°C
Operating and Storage Temperature Range
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
Apk
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Designer’s, E–FET and HDTMOS are trademarks of Motorola Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 2
TMOS
Motorola
Motorola, Inc.
1995 Power MOSFET Transistor Device Data
1
MTP75N05HD
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
50
—
—
54.9
—
—
Vdc
mV/°C
—
—
—
—
10
100
—
—
100
nAdc
2.0
—
—
6.3
4.0
—
Vdc
mV/°C
—
7.0
9.5
—
—
—
—
0.86
0.64
gFS
15
—
—
mhos
Ciss
—
2600
2900
pF
Coss
—
1000
1100
Crss
—
230
275
td(on)
—
15
30
tr
—
170
340
td(off)
—
70
140
tf
—
100
200
QT
—
71
100
Q1
—
13
—
Q2
—
33
—
Q3
—
26
—
—
—
0.97
0.88
1.1
—
trr
—
57
—
ta
—
40
—
tb
—
17
—
QRR
—
0.17
—
—
—
3.5
4.5
—
—
—
7.5
—
OFF CHARACTERISTICS
(Cpk ≥ 2.0)(3)
Drain–Source Breakdown Voltage
(VGS = 0 V, ID = 250 µAdc)
Temperature Coefficient (Positive)
V(BR)DSS
Zero Gate Voltage Drain Current
(VDS = 50 Vdc, VGS = 0)
(VDS = 50 Vdc, VGS = 0, TJ = 150°C)
IDSS
Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0)
IGSS
µAdc
ON CHARACTERISTICS(1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc)
Temperature Coefficient (Negative)
(Cpk ≥ 1.5)(3)
Static Drain–Source On–Resistance
(VGS = 10 Vdc, ID = 37.5 Adc)
(Cpk ≥ 3.0)(3)
Drain–Source On–Voltage (VGS = 10 Vdc)
(ID = 75 Adc)
(ID = 37.5 Adc, TJ = 150°C)
VGS(th)
RDS(on)
mW
VDS(on)
Forward Transconductance (VDS = 10 Vdc, ID = 20 Adc)
Vdc
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance
(VDS = 25 Vdc, VGS = 0,
f = 1.0 MHz)
(Cpk ≥ 2.0)(2)
SWITCHING CHARACTERISTICS(2)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
(VDD = 25 Vdc, ID = 75 Adc,
VGS = 10 Vdc,
RG = 9.1 Ω)
Fall Time
Gate Charge
(VDS = 40 Vdc, ID = 75 Adc,
VGS = 10 Vdc)
ns
nC
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
(IS = 75 Adc, VGS = 0)
(IS = 75 Adc, VGS = 0, TJ = 150°C)
(Cpk ≥ 10)(2)
Reverse Recovery Time
(IS = 37.5 Adc, VGS = 0,
dIS/dt = 100 A/µs)
Reverse Recovery Stored Charge
VSD
Vdc
ns
µC
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25″ from package to center of die)
LD
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
LS
nH
nH
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values.
Max limit – Typ
Cpk =
3 x SIGMA
2
Motorola TMOS Power MOSFET Transistor Device Data
MTP75N05HD
TYPICAL ELECTRICAL CHARACTERISTICS(1)
160
160
TJ = 25°C
120
100
80
6V
60
40
5V
20
0
0.5
1
1.5
2
2.5
3
4
3.5
60
TJ = – 55°C
100°C
40
25°C
0
1
2
3
4
5
7
8
140
160
6
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
Figure 1. On–Region Characteristics
Figure 2. Transfer Characteristics
0.012
TJ = 100°C
0.01
25°C
0.008
0.006
– 55°C
0.004
20
40
60
80
100
120
140
0.009
TJ = 25°C
0.008
VGS = 10 V
0.007
15 V
0.006
0.005
0
20
40
60
80
100
120
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
Figure 3. On–Resistance versus Drain Current
and Temperature
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
2
10000
VGS = 0 V
VGS = 10 V
ID = 37.5 A
1.5
I DSS, LEAKAGE (nA)
R DS(on) , DRAIN–TO–SOURCE RESISTANCE
(NORMALIZED)
80
0
5
4.5
VGS = 10 V
0
100
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
0.014
0.002
120
20
RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
0
VDS ≥ 10 V
140
I D , DRAIN CURRENT (AMPS)
I D , DRAIN CURRENT (AMPS)
140
RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
7V
VGS = 10 V
1
1000
TJ = 125°C
100
100°C
10
0.5
25°C
0
– 50
– 25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
125
Figure 5. On–Resistance Variation with
Temperature
150
0
0
5
15
10
20
25 30
35 40
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
45
50
Figure 6. Drain–To–Source Leakage
Current versus Voltage
(1)Pulse Tests: Pulse Width ≤ 250 µs, Duty Cycle ≤ 2%.
Motorola TMOS Power MOSFET Transistor Device Data
3
MTP75N05HD
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are determined by how fast the FET input capacitance can be charged
by current from the generator.
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off–state condition when calculating td(on) and is read at a voltage corresponding to the
on–state when calculating td(off).
The published capacitance data is difficult to use for calculating rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that
At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board–mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.
t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG – VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG – VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
8000
VDS = 0
VGS = 0
TJ = 25°C
C, CAPACITANCE (pF)
7000
6000
Ciss
5000
4000
Crss
Ciss
3000
2000
Coss
1000
0
10
5
0
VGS
5
10
15
20
25
VDS
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
4
Motorola TMOS Power MOSFET Transistor Device Data
QT
10
50
VGS
8
40
Q2
Q1
6
30
4
20
VDS
TJ = 25°C
ID = 75 A
2
0
Q3
25
50
QT, TOTAL GATE CHARGE (nC)
0
10
0
75
1000
t, TIME (ns)
60
12
VDS , DRAIN–TO–SOURCE VOLTAGE (VOLTS)
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
MTP75N05HD
TJ = 25°C
ID = 75 A
VDD = 35 V
VGS = 10 V
100
tr
tf
td(off)
td(on)
10
1
1
10
100
RG, GATE RESISTANCE (OHMS)
Figure 8. Gate–To–Source and Drain–To–Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN–TO–SOURCE DIODE CHARACTERISTICS
The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining
switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to
the storage of minority carrier charge, QRR, as shown in the
typical reverse recovery wave form of Figure 12. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further
increases switching losses. Therefore, one would like a
diode with short t rr and low QRR specifications to minimize
these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high
di/dts. The diode’s negative di/dt during ta is directly controlled by the device clearing the stored charge. However,
the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of tb/ta serves
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.
Compared to Motorola standard cell density low voltage
MOSFETs, high cell density MOSFET diodes are faster
(shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching
the diode will be less due to the shorter recovery time and
lower switching losses.
40
80
60
30
I S , SOURCE CURRENT (AMPS)
I S , SOURCE CURRENT (AMPS)
di/dt = 300 A/µs
TJ = 25°C
VGS = 0 V
70
50
40
30
20
10
STANDARD CELL DENSITY
trr
HIGH CELL DENSITY
trr
tb
ta
20
10
0
– 10
– 20
– 30
0
0
0.1
0.2 0.3
0.4 0.5
0.6 0.7 0.8
0.9
VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
1
Figure 10. Diode Forward Voltage versus Current
Motorola TMOS Power MOSFET Transistor Device Data
– 40
– 120 – 100 – 80
– 60 – 40 – 20
0
t, TIME (ns)
20
40
60
80
Figure 11. Reverse Recovery Time (trr)
5
MTP75N05HD
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance–General Data and Its Use.”
Switching between the off–state and the on–state may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded, and that the transition
time (tr,tf) does not exceed 10 µs. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) – TC)/(RθJC).
A Power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For reli-
able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases non–linearly with an
increase of peak current in avalanche and peak junction temperature.
Although many E–FETs can withstand the stress of drain–
to–source avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.
100
500
VGS = 20 V
SINGLE PULSE
TC = 25°C
EAS, SINGLE PULSE DRAIN–TO–SOURCE
AVALANCHE ENERGY (mJ)
I D , DRAIN CURRENT (AMPS)
1000
10 µs
100 µs
10
1 ms
10 ms
1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
0.1
dc
1
10
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
100
ID = 75 A
400
300
200
100
0
25
Figure 12. Maximum Rated Forward Biased
Safe Operating Area
50
75
100
125
150
TJ, STARTING JUNCTION TEMPERATURE (°C)
175
Figure 13. Maximum Avalanche Energy versus
Starting Junction Temperature
1
r(t), TRANSIENT THERMAL RESISTANCE
(NORMALIZED)
D = 0.5
0.2
0.1
0.1
0.05
P(pk)
0.02
t1
0.01
t2
DUTY CYCLE, D = t1/t2
SINGLE PULSE
0.01
1.0E–05
1.0E–04
1.0E–03
1.0E–02
t, TIME (s)
1.0E–01
RθJC(t) = r(t) RθJC
RθJC = 1.0°C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) – TC = P(pk) RθJC(t)
1.0E+00
1.0E+01
Figure 14. Thermal Response
6
Motorola TMOS Power MOSFET Transistor Device Data
MTP75N05HD
PACKAGE DIMENSIONS
–T–
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
SEATING
PLANE
C
F
T
S
4
A
Q
1 2 3
U
STYLE 5:
PIN 1.
2.
3.
4.
H
K
Z
L
GATE
DRAIN
SOURCE
DRAIN
R
V
J
G
D
N
CASE 221A–06
ISSUE Y
Motorola TMOS Power MOSFET Transistor Device Data
DIM
A
B
C
D
F
G
H
J
K
L
N
Q
R
S
T
U
V
Z
INCHES
MIN
MAX
0.570
0.620
0.380
0.405
0.160
0.190
0.025
0.035
0.142
0.147
0.095
0.105
0.110
0.155
0.018
0.025
0.500
0.562
0.045
0.060
0.190
0.210
0.100
0.120
0.080
0.110
0.045
0.055
0.235
0.255
0.000
0.050
0.045
–––
–––
0.080
MILLIMETERS
MIN
MAX
14.48
15.75
9.66
10.28
4.07
4.82
0.64
0.88
3.61
3.73
2.42
2.66
2.80
3.93
0.46
0.64
12.70
14.27
1.15
1.52
4.83
5.33
2.54
3.04
2.04
2.79
1.15
1.39
5.97
6.47
0.00
1.27
1.15
–––
–––
2.04
7
MTP75N05HD
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8
◊
*MTP75N05HD/D*
Motorola TMOS Power MOSFET Transistor
Device Data
MTP75N05HD/D