Freescale Semiconductor Technical Data Clock Generator for PowerQUICC and PowerPC Microprocessors and Microcontrollers The MPC9817 is a PLL-based clock generator specifically designed for Freescale Semiconductor Microprocessor and Microcontroller applications including the PowerPC and PowerQUICC. This device generates the microprocessor input clock and other microprocessor system and bus clocks at any one of four output frequencies. These frequencies include the popular 33- and 66-MHz PCI bus frequencies. The device offers five low-skew clock outputs plus three reference outputs. The clock input reference is 25 MHz and may be derived from an external source or by the addition of a 25-MHz crystal to the on-chip crystal oscillator. The extended temperature range of the MPC9817 supports telecommunication and networking requirements. Features • • • • • • • • • • 5 LVCMOS outputs for processor and other system circuitry 3 Buffered 25-MHz reference clock outputs Crystal oscillator or external reference input 25-MHz input reference frequency Selectable output frequencies include: 25, 33, 50, or 66 MHz Low cycle-to-cycle and period jitter Package: 20-lead SSOP 3.3-V supply Supports computing, networking, and telecommunications applications Ambient temperature range: –40°C to +85°C MPC9817 Rev 1, 11/2004 MPC9817 MICROPROCESSOR CLOCK GENERATOR SD SUFFIX 20 SSOP PACKAGE CASE 1461-01 EN SUFFIX 20 SSOP PACKAGE Pb-FREE PACKAGE CASE 1461-01 Functional Description The MPC9817 uses a PLL with a 25-MHz input reference frequency to generate a single bank of five configurable LVCMOS output clocks. The output frequency of this bank is configurable to either 25, 33, 50, or 66 MHz by two FSEL pins. The 25-MHz reference may be either an external frequency source or a 25-MHz crystal. The 25-MHz crystal is directly connected to the XTAL_IN and XTAL_OUT pins with no additional components required. An external reference may be applied to the XTAL_IN pin with the XTAL_OUT pin left floating. The input reference, whether provided by a crystal or an external input, is also directly buffered to a second bank of three LVCMOS outputs. These outputs may be used as the clock source for processor I/O applications such as an Ethernet PHY. When FSEL0 and FSEL1 are both configured low, the QA outputs are directly fed from the input reference providing a total of eight low-skew 25-MHz outputs. For all other combinations of FSEL0 and FSEL1 the single-ended LVCMOS outputs provide five low-skew outputs for use in driving a microprocessor or microcontroller clock input as well as other system components. The MPC9817 is packaged in a 20-lead SSOP package. © Freescale Semiconductor, Inc., 2004. All rights reserved. QA0 XTAL_IN Ref OSC XTAL_OUT QA1 PLL 33,50,66 MHz 400 MHz QA2 QA3 FSEL0 QA4 Data Generator FSEL1 25 MHz QREF0 QREF1 QREF2 MR/OE Figure 1. MPC9817 Logic Diagram Table 1. Pin Configurations Pin I/O Type QA0, QA1, QA2, QA3, QA4 Output LVCMOS Clock Outputs QREF0, QREF1, QREF2 Output LVCMOS Reference Output (25 MHz) XTAL_IN Function Input LVCMOS Crystal Oscillator Input Pin Output LVCMOS Crystal Oscillator Output Pin FSEL0, FSEL1 Input LVCMOS Configures Bank A Clock Output Frequency (pull-up) MR/OE Input LVCMOS Enables All Outputs (pull-down) VDD — — 3.3-V Supply GND — — Ground XTAL_OUT Table 2. Function Table Control FSEL0,FSEL1 Default 00 01 10 11 11 25 MHz fed directly from reference input, PLL disabled 33 MHz 50 MHz 66 MHz MPC9817 2 Advanced Clock Drivers Devices Freescale Semiconductor XTAL_IN 1 20 VDD XTAL_OUT 2 19 QA4 FSEL0 3 18 QA3 VDD 4 17 GND FSEL1 5 16 QA2 QREF2 6 15 QA1 GND 7 14 VDD QREF1 8 13 QA0 QREF0 9 12 MR/OE 10 11 GND VDD Figure 2. MPC9817 20-Lead SSOP Package Pinout (Top View) MPC9817 OPERATION Crystal Oscillator The MPC9817 features a fully integrated Pierce oscillator to minimize system implementation costs. Other than the addition of a 25-MHz crystal, no external components are required.The crystal selection should be: 25 MHz, parallel resonant type with a load specification of CL = 10 pF. Crystals with a load specification of CL = 20 pF may be used, however, the reference frequency may be higher than the specified 25 MHz. Externally supplied capacitors on both the XTAL_IN and XTAL_OUT pins may be used to trim the frequency as desired. The crystal should be located as close to the MPC9817 XTAL_IN and XTAL_OUT pins as possible to avoid any board level parasitic. Table 3. Crystal Specifications Parameter Value Crystal Cut Fundamental AT Cut Resonance Parallel Resonance Shunt Capacitance (CL) 5–7 pF Load Capacitance (CO) 10 pF Equivalent Series Resistance (ESR) 20–60 Ω Power Supply Bypassing The MPC9817 should have all VDD pins bypassed with 0.01 capacitors and a minimum of one 1.0 capacitor for the overall package. All capacitors should be located as close to the SSOP pins as possible. External Clock Source An external reference source of 25 MHz may be applied to the XTAL_IN pin. In this mode of operation, the XTAL_OUT pin should be left floating. MPC9817 Advanced Clock Drivers Devices Freescale Semiconductor 3 Table 4. Absolute Maximum Ratings(1) Symbol VDD IIN IOUT TS Characteristics Min Supply Voltage Max Unit –0.3 3.8 V DC Input Current — ±20 mA DC Output Current — ±75 mA –65 125 °C Storage Temperature Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 5. General Specifications Symbol Characteristics Min Typ Max Unit — VDD ÷ 2 — V V VTT Output Termination Voltage MM ESD Protection (machine model) 200 — — HBM ESD Protection (human body model) 2000 — — V LU Latch-Up Immunity 200 — — mA CIN Input Capacitance — 4 — pF θJA Thermal Resistance (junction-to-ambient) — 80.8 — °C/W TC Ambient Temperature 85 °C –40 Condition Inputs Table 6. DC Characteristics (VDD = 3.3 V ± 5%, TA = –40° to +85°C) Symbol Characteristics Min Typ Max Unit Condition VIH Input High Voltage (XTAL_IN) 2.4 — VDD + 0.3 V VIH Input High Voltage 2.0 — VDD + 0.3 V VIL Input Low Voltage — — 0.8 V LVCMOS — — 150 µA VIN = VDDL or GND — — V IOH = –12 mA IOL = 12 mA IIN Input Current (1) VOH Output High Voltage 2.4 VOL Output Low Voltage — — 0.4 V ZOUT Output Impedance — 14 — Ω Maximum Quiescent Supply Current — 8.0 15.0 mA IDD Input threshold = VDD/2 VDD pins 1. Inputs have pull-down resistors affecting the input current. MPC9817 4 Advanced Clock Drivers Devices Freescale Semiconductor Table 7. AC Characteristics(1) (2) (VDD = 3.3 V ± 5%, TA = –40° to +85°C) Symbol Characteristics Min Typ Max Unit Condition Input and Output Timing Specification fref Input Reference Frequency fVCO VCO Frequency Range fMCX Output Frequency (QAx) 25 MHz Input XTAL Input 25 25 — 400 — MHz 25 33 50 66 25 — — — — — MHz MHz MHz MHz MHz PLL locked 10 — — ns @ 25 MHz 47.5 50 52.5 % — — 100 0 ppm ppm FSEL0, FSEL1 = 00 FSEL0, FSEL1 = 01 FSEL0, FSEL1 = 10 FSEL0, FSEL1 = 11 Output Frequency (QREFx) frefPW DC fout Reference Input Pulse Width Output Duty Cycle Crystal(3) Output Frequency Accuracy External Reference MHz MHz With recommended crystal see Table 3 PLL Specifications BW tLOCK PLL Closed Loop Bandwidth(4) 500 Maximum PLL Lock Time kHz 10 ms ps Skew and Jitter Specifications tsk(O) Output-to-Output Skew (within a bank) 100 tsk(O) Output-to-Output Skew (between bank A and bank Ref) 200 tJIT(CC) Cycle-to-Cycle Jitter 150 ps @ 25 MHz Input Reference QA output tJIT(PER) Period Jitter 100 ps @ 25 MHz Input Reference QA output 1 ns 20% to 80% tr, tf 1. 2. 3. 4. Output Rise/Fall Time FSEL0, FSEL1 = 00 AC characteristics are design targets and pending characterization. AC characteristics apply for parallel output termination of 50 Ω to VTT. Based upon recommended crystal specifications as outlined in operation section. –3 dB point of PLL transfer characteristics. Z = 50 Ω Z = 50 Ω Pulse Generator Z = 50 Ω RT = 50 Ω DUT MPC9817 RT = 50 Ω VTT VTT Figure 3. MPC9817 AC Test Reference (LVCMOS Outputs) MPC9817 Advanced Clock Drivers Devices Freescale Semiconductor 5 Table 8. MPC9817 Pin List Pin Description Pin Description 1 XTAL_IN 11 GND 2 XTAL_OUT 12 MR/OE 3 FSEL0 13 QA0 4 VDD 14 VDD 5 FSEL1 15 QA1 6 QREF2 16 QA2 7 GND 17 GND 8 QREF1 18 QA3 9 QREF0 19 QA4 10 VDD 20 VDD MPC9817 6 Advanced Clock Drivers Devices Freescale Semiconductor PACKAGE DIMENSIONS .236 .157 .150 4 D .061 .055 5 PIN 1 ID 18X 1 20 B .025 B 4 4 B A .0125 .344 .337 10 CL 5 11 3 2X .118 .003 H 2X 10 TIPS .010 C H A-B D C SEATING PLANE 20X .004 C A-B D 7 A A 0˚ MIN (.010) BASE METAL R.003 MIN .010 .007 (.008) .010 .0098 .0040 GAUGE PLANE .012 .008 .007 M PLATING C A-B D SECTION A-A 8˚ 0˚ .035 .016 6 SECTION B-B 8 NOTES: 1. DIMENSIONS ARE IN INCHES. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. DATUM PLANE H LOCATED AT MOLD PARTING LINE AND COINCIDENT WITH LEAD, WHERE LEAD EXITS PLASTIC BODY AT BOTTOM OF PARTING LINE. 4. DATUM A, B AND D TO BE DETRMINED WHERE CENTERLINE BETWEEN LEADS EXITS PLASTIC BODY AT DATUM PLANE H. 5. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH OR PROTRUSIONS, BUT DO INCLUDE MOLD MISMATCH AND ARE MEASURED AT THE MOLD PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006 INCHES FOR ENDS AND .008 INCHES FOR SIDES. 6. THIS DIMENSION IS LENGTH OF TERMINAL FOR SOLDERING A SUBSTRATE. 7. FORMED LEADS SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN .004 INCHES AT SEATING PLANE. 8. THIS DIMENSION IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT OF THE PACKAGE BODY. CASE 1461-02 ISSUE O 20 SSOP PACKAGE MPC9817 Advanced Clock Drivers Devices Freescale Semiconductor 7 How to Reach Us: Home Page: www.freescale.com E-mail: [email protected] USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. 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