® OPA641 Wideband Voltage Feedback OPERATIONAL AMPLIFIER FEATURES APPLICATIONS ● GAIN-BANDWIDTH: 1.6GHz ● STABLE IN GAINS ≥ 2 ● COMMUNICATIONS ● MEDICAL IMAGING ● TEST EQUIPMENT ● CCD IMAGING ● LOW DIFFERENTIAL GAIN/PHASE ERRORS: 0.015%/0.006° ● HIGH SLEW RATE: 650V/µs ● FAST 12-BIT SETTLING: 18ns (0.01%) ● HIGH COMMON-MODE REJECTION: 80dB ● ADC/DAC GAIN AMPLIFIER ● HIGH-RESOLUTION VIDEO ● LOW NOISE PREAMPLIFIER ● LOW HARMONICS: –72dBc at 10MHz ● ACTIVE FILTERS DESCRIPTION The OPA641 is an extremely wideband operational amplifier featuring low noise, high slew rate and high spurious free dynamic range. operational amplifier circuit architecture. This allows the OPA641 to be used in all op amp applications requiring high speed and precision. The OPA641 is conservatively compensated for stability in gains of 2 or greater. This amplifier has a fully symmetrical differential input due to its “classical” Low noise, wide bandwidth, and high linearity make this amplifier suitable for a variety of RF, video, and imaging applications. +V S 7, 8 Non-Inverting Input Inverting Input 3 Output Stage 2 Current Mirror 6 Output CC 4, 5 –V S International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1993 Burr-Brown Corporation PDS-1189B Printed in U.S.A. July, 1994 SPECIFICATIONS ELECTRICAL TA = +25°C, VS = ±5V, RL = 100Ω, CL = 2pF, RFB = 402Ω, and all four power supply pins are used unless otherwise noted. OPA641H, P, U PARAMETER CONDITIONS OFFSET VOLTAGE Input Offset Voltage Average Drift HSQ Grade Over Temperature Power Supply Rejection (+VS) (–VS) INPUT BIAS CURRENT Input Bias Current Over Specified Temperature HSQ Grade Over Temperature Input Offset Current Over Specified Temperature HSQ Grade Over Temperature MIN VS = ±4.5 to ±5.5V 56 51 FREQUENCY RESPONSE, RFB = 402Ω Closed-Loop Bandwidth 79 58 VCM = 0V 0.2 0.5 2 2.5 VCM = ±0.5V ±2.5 ±2.5 56 MIN TYP MAX UNITS ±2 ±6 61 54 ±1 ±6 ±3 82 60 mV µV/°C mV dB dB * * 30 * * 1.2 * * 75 1.0 2.0 4.0 µA µA µA µA µA µA 8.0 2.9 2.8 2.8 63 * * * * * nV/√Hz nV/√Hz nV/√Hz nV/√Hz µVr ms 2.0 * pA/√Hz 4 13 * * dB dB * * 80 V V dB * * kΩ || pF MΩ || pF 61 * dB dB * * * * * * * * * * * * * MHz MHz MHz V/µs V/µs ns ns ns % degrees MHz dBc dBc ±2.85 ±2.75 78 * * 65 15 || 1 2 || 1 VO = ±2V, RL = 100Ω VO = ±2V, RL = 100Ω 50 45 58 56 53 48 All Four Power Pins Used 800 78 39 650 550 18 13 5 0.015 0.006 0.1 78 72 No Load RL = 100Ω ±2.6 ±3.0 * ±2.5 * ±2.8 V V ±2.25 ±2.0 ±40 ±25 ±2.5 ±2.3 ±55 ±50 * * V * * ±25 * * ±50 mA mA mA mA Ω 75 0.04 1MHz, G = +2V/V ® OPA641 ±6 30 90 Gain = +2V/V Gain = +5V/V Gain = +10V/V Slew Rate(1) G = +2, 2V Step At Minimum Specified Temperature G = +2, 2V Step Settling Time: 0.01% G = +2, 2V Step 0.1% G = +2, 2V Step 1% G = +2, 2V Step Differential Gain at 3.58MHz, G = +2V/V VO = 0V to 1.4V, RL = 150Ω Differential Phase at 3.58MHz, G = +2V/V VO = 0V to 1.4V, RL = 150Ω Gain Flatness G = +2 Spurious Free Dynamic Range G = +2, f = 5MHz, VO = 2Vp-p G = +2, f = 10MHz, VO = 2Vp-p OUTPUT Voltage Output Over Specified Temperature HSQ Grade Over Temperature Voltage Output Over Specified Temperature HSQ Grade Over Temperature Current Output Over Specified Temperature HSQ Grade Over Temperature Short Circuit Current Output Resistance ±2 ±10 13 20 INPUT IMPEDANCE Differential Common-Mode OPEN-LOOP GAIN, DC Open-Loop Voltage Gain Over Specified Temperature MAX VCM = 0V NOISE Input Voltage Noise Noise Density, f = 100Hz f = 10kHz f = 1MHz f = 1MHz to 500MHz Voltage Noise, BW = 100Hz to 500MHz Input Bias Current Noise Density f = 0.1Hz to 20kHz Noise Figure (NF) RS = 1kΩ RS = 50Ω INPUT VOLTAGE RANGE Common-Mode Input Range Over Specified Temperature Common-Mode Rejection OPA641HSQ, PB, UB TYP 2 * SPECIFICATIONS (CONT) ELECTRICAL TA = +25°C, VS = ±5V, RL = 100Ω, CL = 2pF, RFB = 402Ω, and all four power supply pins are used unless otherwise noted. OPA641H, P, U PARAMETER POWER SUPPLY Specified Operating Voltage Operating Voltage Range Quiescent Current Over Specified Temperature TEMPERATURE RANGE Specification: H, P, PB, U, UB HSQ Thermal Resistance P U H CONDITIONS MIN TMIN to TMAX TMIN to TMAX ±4.5 Ambient Ambient θJA, Junction to Ambient TYP ±5 OPA641HSQ, PB, UB MAX MIN ±5.5 ±22 ±24 * +85 * –55 TYP MAX UNITS * * * V V mA mA * +125 °C °C * ±15 ±19 –40 * * 120 170 120 °C/W °C/W °C/W * * * NOTE: (1) Slew rate is rate of change from 10% to 90% of output voltage step. ABSOLUTE MAXIMUM RATINGS ORDERING INFORMATION OPA641 ( ) ( ) (Q) Supply .......................................................................................... ±5.5VDC Internal Power Dissipation(1) ....................... See Applications Information Differential Input Voltage ............................................................ Total VCC Input Voltage Range .................................... See Applications Information Storage Temperature Range: H, HSQ .......................... –65°C to +150°C P, PB, U, UB ................. –40°C to +125°C Lead Temperature (soldering, 10s) .............................................. +300°C (soldering, SOIC 3s) ....................................... +260°C Junction Temperature (TJ ) ............................................................ +175°C Basic Model Number Package Code H = 8-pin Sidebraze DIP P = 8-pin Plastic DIP U = 8-pin Plastic SOIC Performance Grade Code S = –55°C to +125°C B(1) or No Letter = –40°C to +85°C Reliability Screening Q = Q-Screened (HSQ Model Only) NOTE: (1) Packages must be derated based on specified θ TJ must be observed. JA. Maximum NOTE: (1) The “B” grade of the SOIC package will be designated with a “B”. Refer to the mechanical section for the location. PACKAGE INFORMATION PIN CONFIGURATION Top View DIP/SOIC NC 1 8 +VS2(1) Inverting Input 2 7 +VS1 Non-Inverting Input 3 6 Output –VS1 4 5 –VS2(1) MODEL PACKAGE PACKAGE DRAWING NUMBER(1) OPA641H, HSQ OPA641P, PB OPA641U, UB 8-Pin Cerdip 8-Pin DIP 8-Pin SOIC 157 006 182 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. ELECTROSTATIC DISCHARGE SENSITIVITY NOTE: (1) Making use of all four power supply pins is highly recommended, although not required. Using these four pins, instead of just pins 4 and 7, will lower the effective pin impedance and substantially lower distortion. Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. Burr-Brown Corporation recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 OPA641 TYPICAL PERFORMANCE CURVES TA = +25°C, VS = ±5V, RL = 100Ω, CL = 2pF, RFB = 402Ω, and all four power supply pins are used unless otherwise noted. COMMON-MODE REJECTION vs INPUT COMMON-MODE VOLTAGE AOL, PSR, CMR vs TEMPERATURE 90 90 Common-Mode Rejection (dB) AOL, PSR, CMR (dB) +PSR 80 CMR 70 –PSR 60 AOL 50 –75 85 80 75 70 65 60 55 50 –50 –25 0 25 50 75 100 125 –5 –4 –3 Temperature (°C) 0 1 2 3 4 5 17 Supply Current (±mA) Input Bias Current (µA) –1 SUPPLY CURRENT vs TEMPERATURE INPUT BIAS CURRENT vs TEMPERATURE 20 15 10 –75 –2 Common-Mode Voltage (V) 16 15 14 13 –50 –25 0 25 50 75 100 125 –75 –50 –25 Ambient Temperature (°C) 0 25 50 75 100 125 Ambient Temperature (°C) VOLTAGE NOISE vs FREQUENCY OUTPUT CURRENT vs TEMPERATURE 12 70 Voltage Noise (nV/√Hz) Output Current (±mA) 10 60 –IO 50 +IO 8 6 4 2 40 –60 0 –40 –20 0 20 40 60 80 100 120 100 140 ® OPA641 1k 10k 100k Frequency (Hz) Ambient Temperature (°C) 4 1M 10M TYPICAL PERFORMANCE CURVES (CONT) TA = +25°C, VS = ±5V, RL = 100Ω, CL = 2pF, RFB = 402Ω, and all four power supply pins are used unless otherwise noted. SMALL SIGNAL TRANSIENT RESPONSE (G = +2, RL = 100Ω) RECOMMENDED ISOLATION RESISTANCE vs CAPACITIVE LOAD FOR G = +2 50 40 20 0 Output Voltage (mV) Isolation Resistance (Ω) 40 30 20 10 –20 –40 –60 –80 –100 –120 –140 0 –160 0 20 40 60 80 100 Time (2ns/div) Capacitive Load (pF) LARGE SIGNAL TRANSIENT RESPONSE (G = +2, RL = 100Ω) 1 80 60 40 20 0 0.8 0.4 0 Gain (dB) 0.2 0 –0.2 –45 –90 –0.4 –135 –0.6 –180 –0.8 –1 –225 –100 Time (2ns/div) 1k G = +5 CLOSED-LOOP BANDWIDTH 24 22 20 18 16 4 2 0 100k 1M 10M 100M Frequency (Hz) 1G 1G G = +10 CLOSED-LOOP BANDWIDTH SOIC Bandwidth = 77MHz 14 12 10 8 6 1M Frequency (Hz) 24 22 20 18 16 Gain (dB) Gain (dB) Output Voltage (V) 0.6 Open-Loop Phase (°) AV = +2 OPEN-LOOP SMALL SIGNAL BANDWIDTH 14 12 10 8 6 4 2 0 100k 10G SOIC Bandwidth = 39MHz 1M 10M 100M Frequency (Hz) 1G 10G ® 5 OPA641 TYPICAL PERFORMANCE CURVES (CONT) TA = +25°C, VS = ±5V, RL = 100Ω, CL = 2pF, RFB = 402Ω, and all four power supply pins are used unless otherwise noted. HARMONIC DISTORTION vs TEMPERATURE (G = +2, VO = 2Vp-p, RL = 100Ω, fO = 5MHz) G = +2 CLOSED-LOOP BANDWIDTH –70 Gain (dB) 8 Harmonic Distortion (dBc) 10 SOIC Bandwidth = 879MHz 6 4 2 0 100k 2fO –80 3fO –90 –100 1M 10M 100M Frequency (Hz) 1G –50 –75 10G –25 0 25 50 75 100 125 Temperature (°C) NOTE: Dip Bandwidth = 785MHz HARMONIC DISTORTION vs FREQUENCY (G = +2, VO = 2Vp-p, RL = 100Ω) 5MHz HARMONIC DISTORTION vs OUTPUT SWING –70 Harmonic Distortion (dBc) –40 –60 2fO 3fO –80 3fO –80 2fO –90 –100 –100 10M 1M 0 100M 1.0 10MHz HARMONIC DISTORTION vs OUTPUT SWING –60 –70 2fO 3fO –80 –90 –100 0 1.0 2.0 Output Swing (Vp-p) ® OPA641 2.0 Output Swing (Vp-p) Frequency (Hz) Harmonic Distortion (dBc) Harmonic Distortion (dBc) –20 6 3.0 4.0 3.0 4.0 APPLICATIONS INFORMATION can conduct heat from active circuit package pins into ambient air by convection. DISCUSSION OF PERFORMANCE The OPA641 provides a level of speed and precision not previously attainable in monolithic form. Unlike current feedback amplifiers, the OPA641’s design uses a “Classical” operational amplifier architecture and can therefore be used in all traditional operational amplifier applications. While it is true that current feedback amplifiers can provide wider bandwidth at higher gains, they offer some disadvantages. The asymmetrical input characteristics of current feedback amplifiers (i.e., one input is a low impedance) prevents them from being used in a variety of applications. In addition, unbalanced inputs make input bias current errors difficult to correct. Bias current cancellation through matching of inverting and non-inverting input resistors is impossible because the input bias currents are uncorrelated. Current noise is also asymmetrical and is usually significantly higher on the inverting input. Perhaps most important, settling time to 0.01% is often extremely poor due to internal design tradeoffs. Many current feedback designs exhibit settling times to 0.01% in excess of 10 microseconds even though 0.1% settling times are reasonable. Such amplifiers are completely inadequate for fast settling 12-bit applications. The OPA641’s “Classical” operational amplifier architecture employs true differential and fully symmetrical inputs to eliminate these troublesome problems. All traditional circuit configurations and op amp theory apply to the OPA641. Supply bypassing is extremely critical and must always be used, especially when driving high current loads. Both power supply leads should be bypassed to ground as close as possible to the amplifier pins. Tantalum capacitors (2.2µF) with very short leads are recommended. A parallel 0.01µF ceramic must also be added. Surface mount bypass capacitors will produce excellent results due to their low lead inductance. Additionally, suppression filters can be used to isolate noisy supply lines. Properly bypassed and modulation-free power supply lines allow full amplifier output and optimum settling time performance. Points to Remember 1) Making use of all four power supply pins will lower the effective power supply impedance seen by the input and output stages. This will improve the AC performance including lower distortion. The lowest distortion is achieved when running separated traces to VS1 and VS2. Power supply bypassing with 0.01µF and 2.2µF surface mount capacitors on the topside of the PC board is recommended. It is essential to keep the 0.01µF capacitor very close to the power supply pins. Refer to the DEM-OPA64x Datasheet for the recommended layout and component placement. 2) Whenever possible, use surface mount. Don’t use point-topoint wiring as the increase in wiring inductance will be detrimental to AC performance. However, if it must be used, very short, direct signal paths are required. The input signal ground return, the load ground return, and the power supply common should all be connected to the same physical point to eliminate ground loops, which can cause unwanted feedback. WIRING PRECAUTIONS Maximizing the OPA641’s capability requires some wiring precautions and high-frequency layout techniques. Oscillation, ringing, poor bandwidth and settling, gain peaking, and instability are typical problems plaguing all high-speed amplifiers when they are improperly used. In general, all printed circuit board conductors should be wide to provide low resistance, low impedance signal paths. They should also be as short as possible. The entire physical circuit should be as small as practical. Stray capacitances should be minimized, especially at high impedance nodes, such as the amplifier’s input terminals. Stray signal coupling from the output or power supplies to the inputs should be minimized. All circuit element leads should be no longer than 1/4 inch (6mm) to minimize lead inductance, and low values of resistance should be used. This will minimize time constants formed with the circuit capacitances and will eliminate stray, parasitic circuits. 3) Surface mount on the PC Board. Good component selection is essential. Capacitors used in critical locations should be a low inductance type with a high quality dielectric material. Likewise, diodes used in critical locations should be Schottky barrier types, such as HP5082-2835 for fast recovery and minimum charge storage. Ordinary diodes will not be suitable in RF circuits. 4) Whenever possible, solder the OPA641 directly into the PC board without using a socket. Sockets add parasitic capacitance and inductance, which can seriously degrade AC performance or produce oscillations. 5) Use a small feedback resistor (usually 25Ω) in unity-gain voltage follower applications for the best performance. For gain configurations, resistors used in feedback networks should have values of a few hundred ohms for best performance. Shunt capacitance problems limit the acceptable resistance range to about 1kΩ on the high end and to a value that is within the amplifier’s output drive limits on the low end. Metal film and carbon resistors will be satisfactory, but wirewound resistors (even “non-inductive” types) are absolutely unacceptable in high-frequency circuits. Feedback resistors should be placed directly between the output and the inverting input on the backside of the PC board. This placement allows for the shortest feedback path and the highest bandwidth. See the demonstration board layout at Grounding is the most important application consideration for the OPA641, as it is with all high-frequency circuits. Oscillations at high frequencies can easily occur if good grounding techniques are not used. A heavy ground plane (2 oz. copper recommended) should connect all unused areas on the component side. Good ground planes can reduce stray signal pickup, provide a low resistance, low inductance common return path for signal and power, and ® 7 OPA641 the end of the datasheet. A longer feedback path than this will decrease the realized bandwidth substantially. since extraneous noise, such as power supply noise, can be inadvertently coupled into the amplifier’s inverting input terminal. Remember that additional offset errors can be created by the amplifier’s input bias currents. Whenever possible, match the impedance seen by both inputs as is shown with R3. This will reduce input bias current errors to the amplifier’s offset current. 6) Due to the extremely high bandwidth of the OPA641, the SOIC package is strongly recommended due its low parasitic impedance. The parasitic impedance in the PDIP and CERDIP packages causes the OPA641 to experience about 5dB of gain peaking in unity-gain configurations. This is compared with virtually no gain peaking in the SOIC package in unity-gain. The gain peaking in the PDIP and CERDIP packages is minimized in gains of 4 or greater, however. Surface mount components (chip resistors, capacitors, etc.) also have low lead inductance and are therefore strongly recommended. 7) Avoid overloading the output. Remember that output current must be provided by the amplifier to drive its own feedback network as well as to drive its load. Lowest distortion is achieved with high impedance loads. INPUT PROTECTION Static damage has been well recognized for MOSFET devices, but any semiconductor device deserves protection from this potentially damaging source. The OPA641 incorporates on-chip ESD protection diodes as shown in Figure 2. This eliminates the need for the user to add external protection diodes, which can add capacitance and degrade AC performance. All pins on the OPA641 are internally protected from ESD 8) Don’t forget that these amplifiers use ±5V supplies. Although they will operate perfectly well with +5V and –5.2V, use of ±15V supplies will destroy the part. 9) Standard commercial test equipment has not been designed to test devices in the OPA641’s speed range. Benchtop op amp testers and ATE systems will require a special test head to successfully test these amplifiers. 10) Terminate transmission line loads. Unterminated lines, such as coaxial cable, can appear to the amplifier to be a capacitive or inductive load. By terminating a transmission line with its characteristic impedance, the amplifier’s load then appears purely resistive. 11) Plug-in prototype boards and wire-wrap boards will not be satisfactory. A clean layout using RF techniques is essential; there are no shortcuts. +V CC External Pin FIGURE 2. Internal ESD Protection. by means of a pair of back-to-back reverse-biased diodes to either power supply as shown. These diodes will begin to conduct when the input voltage exceeds either power supply by about 0.7V. This situation can occur with loss of the amplifier’s power supplies while a signal source is still present. The diodes can typically withstand a continuous current of 30mA without destruction. To insure long term reliability, however, diode current should be externally limited to 10mA or so whenever possible. The OPA641 utilizes a fine geometry high speed process that withstands 500V using Human Body Model and 100V using the Machine Model. However, static damage can cause subtle changes in amplifier input characteristics without necessarily destroying the device. In precision operational amplifiers, this may cause a noticeable degradation of offset voltage and drift. Therefore, static protection is strongly recommended when handling the OPA641. If additional offset adjustment is needed, the circuit in Figure 1 can be used without degrading offset drift with temperature. Avoid external adjustment whenever possible R2 RTrim 20kΩ 47kΩ Internal Circuitry –V CC OFFSET VOLTAGE ADJUSTMENT +VCC ESD Protection diodes internally connected to all pins. OPA641 –VCC 10µF R3(1) = R1 || R2 R1 OUTPUT DRIVE CAPABILITY The OPA641 has been optimized to drive 75Ω and 100Ω resistive loads. The device can drive 2Vp-p into a 75Ω load. This high-output drive capability makes the OPA641 an ideal choice for a wide range of RF, IF, and video applications. In many cases, additional buffer amplifiers are unneeded. VIN or Ground Output Trim Range ≅ +VCC R2 RTrim to –VCC R2 RTrim NOTE: (1) R3 is optional and can be used to cancel offset errors due to input bias currents. FIGURE 1. Offset Voltage Trim. ® OPA641 8 Many demanding high-speed applications such as ADC/DAC buffers require op amps with low wideband output impedance. For example, low output impedance is essential when driving the signal-dependent capacitances at the inputs of flash A/D converters. As shown in Figure 3, the OPA641 maintains very low closed-loop output impedance over frequency. Closed-loop output impedance increases with frequency since loop gain is decreasing with frequency. (RS typically 5Ω to 25Ω) RS OPA641 RL CL 100 Output Impedance (Ω) AV = +2V/V FIGURE 4. Driving Capacitive Loads. 10.0 cable (29pF/foot for RG-58) will not load the amplifier when the coaxial cable or transmission line is terminated in its characteristic impedance. 1.0 0.1 COMPENSATION 0.01 The OPA641 is internally compensated and is stable in unity gain with a phase margin of approximately 60°. However, the unity gain buffer is the most demanding circuit configuration for loop stability and oscillations are most likely to occur in this gain. If possible, use the device in a noise gain of two or greater to improve phase margin and reduce the susceptibility to oscillation. (Note that, from a stability standpoint, an inverting gain of –1V/V is equivalent to a noise gain of 2.) Gain and phase response for other gains are shown in the Typical Performance Curves. 0.001 10k 100k 1M 10M 100M Frequency (Hz) FIGURE 3. Small-Signal Output Impedance vs Frequency. THERMAL CONSIDERATIONS The OPA641 does not require a heat sink for operation in most environments. At extreme temperatures and under full load conditions a heat sink may be necessary. The high-frequency response of the OPA641 in a good layout is very flat with frequency. However, some circuit configurations such as those where large feedback resistances are used, can produce high-frequency gain peaking. This peaking can be minimized by connecting a small capacitor in parallel with the feedback resistor. This capacitor compensates for the closed-loop, high frequency, transfer function zero that results from the time constant formed by the input capacitance of the amplifier (typically 2pF after PC board mounting), and the input and feedback resistors. The selected compensation capacitor may be a trimmer, a fixed capacitor, or a planned PC board capacitance. The capacitance value is strongly dependent on circuit layout and closed-loop gain. Using small resistor values will preserve the phase margin and avoid peaking by keeping the break frequency of this zero sufficiently high. When high closedloop gains are required, a three-resistor attenuator (tee network) is recommended to avoid using large value resistors with large time constants. The internal power dissipation is given by the equation PD = PDQ + PDL, where PDQ is the quiescent power dissipation and PDL is the power dissipation in the output stage due to the load. (For ±VCC = ±5V, PDQ = 10V x 24mA = 240mW, max). For the case where the amplifier is driving a grounded load (RL) with a DC voltage (±VOUT) the maximum value of PDL occurs at ±VOUT = ±VCC/2, and is equal to PDL, max = (±VCC)2 /4RL. Note that it is the voltage across the output transistor, and not the load, that determines the power dissipated in the output stage. The short-circuit condition represents the maximum amount of internal power dissipation that can be generated. The variation of output current with temperature is shown in the Typical Performance Curves. CAPACITIVE LOADS The OPA641’s output stage has been optimized to drive low resistive loads. Capacitive loads, however, will decrease the amplifier’s phase margin which may cause high frequency peaking or oscillations. Capacitive loads greater than 5pF should be buffered by connecting a small resistance, usually 5Ω to 25Ω, in series with the output as shown in Figure 4. This is particularly important when driving high capacitance loads such as flash A/D converters. SETTLING TIME Settling time is defined as the total time required, from the input signal step, for the output to settle to within the specified error band around the final value. This error band is expressed as a percentage of the value of the output transition, a 2V step. Thus, settling time to 0.01% requires an error band of ±200µV centered around the final value of 2V. In general, capacitive loads should be minimized for optimum high frequency performance. Coax lines can be driven if the cable is properly terminated. The capacitance of coax ® 9 OPA641 Settling time, specified in an inverting gain of one, occurs in only 18ns to 0.01% for a 2V step, making the OPA641 one of the fastest settling monolithic amplifiers commercially available. Settling time increases with closed-loop gain and output voltage change as described in the Typical Performance Curves. Preserving settling time requires critical attention to the details as mentioned under “Wiring Precautions.” The amplifier also recovers quickly from input overloads. Overload recovery time to linear operation from a 50% overload is typically only 30ns. –70 Harmonic Distortion (dBc) G = +2, VO = 2Vp-p, fO = 5MHz In practice, settling time measurements on the OPA641 prove to be very difficult to perform. Accurate measurement is next to impossible in all but the very best equipped labs. Among other things, a fast flat-top generator and high speed oscilloscope are needed. Unfortunately, fast flat-top generators, which settle to 0.01% in sufficient time, are scarce and expensive. Fast oscilloscopes, however, are more commonly available. For best results, a sampling oscilloscope is recommended. Sampling scopes typically have bandwidths that are greater than 1GHz and very low capacitance inputs. They also exhibit faster settling times in response to signals that would tend to overload a real-time oscilloscope. Figure 6 shows the test circuit used to measure settling time for the OPA641. This approach uses a 16-bit sampling oscilloscope to monitor the input and output pulses. These waveforms are captured by the sampling scope, averaged, and then subtracted from each other in software to produce the error signal. This technique eliminates the need for the traditional “false-summing junction,” which adds extra parasitic capacitance. Note that instead of an additional flat-top generator, this technique uses the scope’s built-in calibration source as the input signal. 2fO –90 3fO –100 10 100 1k 10k Load Resistance (Ω) FIGURE 5. 5MHz Harmonic Distortion vs Load Resistance. The third-order intercept point is an important parameter for many RF amplifier applications. Figure 6 shows the OPA641’s single-tone third-order intercept versus frequency. This curve is particularly useful for determining the magnitude of the third harmonic as a function of frequency, load resistance, and gain. For example, assume that the application requires the OPA641 to operate in a gain of +2V/V and drive 2Vp-p into 100Ω at a frequency of 5MHz. Referring to Figure 6 we find that the intercept point is +38dBm. The magnitude of the third harmonic can now be easily calculated from the expression: Third Harmonic (dBc) = 2(OPI3P – PO) where OPI3P = third-order output intercept, dBm PO = output level/tone, dBm/tone For this case OPI3P = 38dBm, PO = 7dBm, and the third harmonic = 2(38 – 7) = 62dB below the fundamental tone. The OPA641’s low IMD makes the device an excellent choice for a variety of RF signal processing applications. The value for the two-tone third-order intercept is typically 6dB lower than the single-tone value. DIFFERENTIAL GAIN AND PHASE Differential Gain (DG) and Differential Phase (DP) are among the more important specifications for video applications. DG is defined as the percent change in closed-loop gain over a specified change in output voltage level. DP is defined as the change in degrees of the closed-loop phase over the same output voltage change. Both DG and DP are specified at the NTSC sub-carrier frequency of 3.58MHz. DG and DP increase with closed-loop gain and output voltage transition. All measurements were performed using a Tektronix model VM700 Video Measurement Set. Third-Order Intercept Point (dBm) 60 DISTORTION AND NOISE The OPA641’s harmonic distortion characteristics vs frequency and power output in the Typical Performance Curves. Distortion can be further improved by increasing the load resistance (refer to Figure 5). Remember to include the contribution of the feedback resistance when calculating the effective load resistance seen by the amplifier. G = +2V/V 50 40 30 20 10 Although harmonic distortion may decrease with higher load resistances (i.e., higher feedback resistors), the effective output noise will increase due to the higher resistance. Therefore, noise or harmonic distortion may be optimized by picking the appropriate feedback resistor. 1M 10M 100M Frequency (Hz) FIGURE 6. Single-Tone Third-Order Intercept Point vs Frequency. ® OPA641 –80 10 NOISE FIGURE ENVIRONMENTAL (Q) SCREENING The OPA641 voltage and current noise spectral densities are specified in the Typical Performance Curves. For RF applications, however, Noise Figure (NF) is often the preferred noise specification since it allows system noise performance to be more easily calculated. The OPA641’s Noise Figure vs Source Resistance is shown in Figure 7. The inherent reliability of a semiconductor device is controlled by the design, materials and fabrication of the device —it cannot be improved by testing. However, the use of environmental screening can eliminate the majority of those units which would fail early in their lifetimes (infant mortality) through the application of carefully selected accelerated stress levels. Burr-Brown “Q-Screening” provides environmental screening to our standard industrial products, thus enhancing reliability. The screening illustrated in the following table is performed to selected stress levels similar to those of MIL-STD-883. 25 NF = 10 LOG 1 + Noise Figure (dB) 20 en2 + (InRS)2 4KTRS 15 SCREEN Internal Visual 10 Stabilization Bake Temperature Cycling 5 Burn-In Test METHOD Burr-Brown QC4118 Temperature = 150°C, 24 hrs Temperature = –65°C to 150°C, 10 cycles Temperature = 125°C, 160 hrs minimum Centrifuge 0 10 100 1k Source Resistance (Ω) 10k 100k FIGURE 7. Noise Figure vs Source Resistance. 20,000G Hermetic Seal Fine: He leak rate < 5 x 1x0–8 atm cc/s, 30PSiG Gross: per Fluorocarbon bubble test, 60PSiG Electrical Tests As described in specifications tables. External Visual Burr-Brown QC5150 NOTE: Q-Screening is available on the HSQ package only. SPICE MODELS Computer simulation using SPICE is often useful when analyzing the performance of analog circuits and systems. This is particularly true for Video and RF amplifier circuits where parasitic capacitance and inductance can have a major effect on circuit performance. SPICE models are available for the OPA641. Contact Burr-Brown Applications Department to receive a spice diskette. DEMONSTRATION BOARDS Demonstration boards to speed prototyping are available. Refer to the DEM-OPA64X Datasheet for details. ® 11 OPA641 APPLICATIONS 402Ω 402Ω 75Ω Transmission Line 75Ω V OUT OPA641 Video Input 75Ω 75Ω FIGURE 8. Video Gain Amplifier. OPA641 RF 402Ω 200Ω 402Ω RG 200Ω RF 200Ω OPA641 402Ω 402Ω OPA641 Differential Voltage Gain = 10V/V = 1 + 2RF /RG FIGURE 9. Wideband, Fast-Settling Instrumentation Amplifier. 50Ω or 75Ω Transmission Line 50Ω or 75Ω OPA641 50Ω or 75Ω 50Ω or 75Ω RF 402Ω Differential Input RG Differential Output 200Ω RF 402Ω 50Ω or 75Ω Transmission Line OPA641 50Ω or 75Ω 50Ω or 75Ω Differential Voltage Gain = 10V/V = 1 + 2RF /RG FIGURE 10. Differential Gain Amplifier and Driver for 50Ω or 75Ω Systems. ® OPA641 12 50Ω or 75Ω 402Ω +5V (–) 200Ω Differential Input D SingleEnded Output OPA641 200Ω (+) (1) J1 (1) D J2 S S 2N5911 2 402Ω 3 7 OPA641 6 V OUT 4 R1(1) 2kΩ FIGURE 11. Difference Amplifier with Gain. R2(1) 2kΩ –5V High Speed ADC Input NOTE: (1) Select J1, J2 and R1, R2 to set input stage current for optimum performance. FIGURE 13. Low Noise, Wideband FET Input Op Amp. RS Input OPA641 402Ω Input Bias Current: 1pA 499Ω 100Ω FIGURE 12. Gain Amplifier for ADCs (G = +5V/V). ® 13 OPA641