Order this document by MTB1306/D SEMICONDUCTOR TECHNICAL DATA !"% $ # #" TMOS POWER FET 75 AMPERES 30 VOLTS RDS(on) = 0.0065 OHM N–Channel Enhancement–Mode Silicon Gate The D2PAK package has the capability of housing a larger die than any existing surface mount package which allows it to be used in applications that require the use of surface mount components with higher power and lower RDS(on) capabilities. This advanced high–cell density HDTMOS power FET is designed to withstand high energy in the avalanche and commutation modes. This new energy efficient design also offers a drain–to–source diode with fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. • Avalanche Energy Specified • Source–to–Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode • Diode is Characterized for Use in Bridge Circuits • IDSS and VDS(on) Specified at Elevated Temperature • Short Heatsink Tab Manufactured — Not Sheared • Specially Designed Leadframe for Maximum Power Dissipation • Surface Mount Package Available in 16 mm, 13–inch/2500 Unit Tape & Reel, Add T4 Suffix to Part Number CASE 418B–03 D2PAK MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Rating Symbol Value Unit Drain–to–Source Voltage VDSS 30 Vdc Drain–to–Gate Voltage (RGS = 1.0 MΩ) VDGR 30 Vdc Gate–to–Source Voltage — Continuous — Non–Repetitive (tp ≤ 10 ms) VGS VGSM ± 20 ± 20 Vdc Vpk Drain Current — Continuous — Continuous @ 100°C — Single Pulse (tp ≤ 10 µs) ID ID IDM 75 59 225 Adc Total Power Dissipation Derate above 25°C Total Power Dissipation @ TA = 25°C (1) PD 150 1.2 2.5 Watts W/°C Watts TJ, Tstg – 55 to 150 °C Operating and Storage Temperature Range Apk Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 75 Apk, L = 0.1 mH, RG = 25 Ω) EAS Thermal Resistance — Junction–to–Case — Junction–to–Ambient — Junction–to–Ambient (1) RθJC RθJA RθJA 0.8 62.5 50 °C/W TL 260 °C Maximum Lead Temperature for Soldering Purposes, 1/8″ from Case for 5.0 seconds mJ 280 (1) When surface mounted to an FR4 board using the minimum recommended pad size. This document contains information on a new product. Specifications and information herein are subject to change without notice. E–FET and HDTMOS are trademarks of Motorola, Inc. Motorola Motorola, Inc.TMOS 1997 Power MOSFET Transistor Device Data 1 MTB1306 ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 30 — — — — — — 10 100 — — 100 1.0 1.5 2.0 — — 5.8 7.4 6.5 8.5 — — 0.44 — 0.5 0.38 gFS 15 55 — mhos Ciss — 2560 3584 pF Coss — 1305 1827 Crss — 386 772 td(on) — 17 35 tr — 170 340 td(off) — 68 136 tf — 145 290 QT — 50 70 Q1 — 8.3 — Q2 — 25.3 — Q3 — 17.2 — — — 0.75 0.64 1.1 — trr — 84 — ta — 35 — tb — 53 — QRR — 0.13 — OFF CHARACTERISTICS Drain–to–Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125°C) IDSS Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 Vdc) IGSS Vdc µAdc nAdc ON CHARACTERISTICS(1) Gate Threshold Voltage (VDS = VGS, ID = 250 µAdc) VGS(th) Static Drain–to–Source On–Resistance (VGS = 10 Vdc, ID = 38 Adc) (VGS = 5.0 Vdc, ID = 38 Adc) RDS(on) Drain–to–Source On–Voltage (VGS = 10 Vdc, ID = 75 Adc) (VGS = 10 Vdc, ID = 38 Adc, TJ = 150°C) VDS(on) Forward Transconductance (VDS = 3.0 Vdc, ID = 20 Adc) Vdc mW Vdc DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vdc, Vdc VGS = 0 Vdc, Vdc f = 1.0 MHz) Transfer Capacitance SWITCHING CHARACTERISTICS(2) Turn–On Delay Time Rise Time Turn–Off Delay Time (VDD = 15 Vdc, Vd ID = 75 Adc, Ad VGS = 5.0 5 0 Vdc, Vdc RG = 4.7 Ω)) Fall Time Gate Charge Vd , ID = 75 Adc, Ad , ( DS = 24 Vdc, (V VGS = 5.0 Vdc) ns nC SOURCE–DRAIN DIODE CHARACTERISTICS Forward On–Voltage VSD (IS = 20 Adc, VGS = 0 Vdc) (IS = 20 Adc, VGS = 0 Vdc, TJ = 125°C) Reverse Recovery Time Ad , VGS = 0 Vdc, Vd , ((IS = 20 Adc, dIS/dt = 100 A/µs) Reverse Recovery Stored Charge Vdc ns µC (1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%. (2) Switching characteristics are independent of operating junction temperature. 2 Motorola TMOS Power MOSFET Transistor Device Data MTB1306 TYPICAL ELECTRICAL CHARACTERISTICS 150 180 5.0 V 4.0 V TJ = 25°C VDS ≥ 10 V 160 125 ID , DRAIN CURRENT (AMPS) I D , DRAIN CURRENT (AMPS) VGS = 10 V 100 75 50 25 140 120 100 80 60 25°C 40 125°C 20 0 TJ = –55°C 0 0.5 1.0 1.75 0.25 0.75 1.25 1.5 VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) 0 2.0 2.0 0.010 VGS ≥ 10 V 0.009 0.008 TJ = 100°C 0.007 25°C 0.006 0.005 –55°C 0.004 0.003 0.002 0.001 0 20 40 60 100 80 ID, DRAIN CURRENT (AMPS) 140 120 0.009 TJ = 25°C 0.008 VGS = 5.0 V 0.007 0.006 10 V 0.005 0.004 20 30 40 Figure 3. On–Resistance versus Drain Current and Temperature 50 60 70 80 90 100 110 120 130 140 150 ID, DRAIN CURRENT (AMPS) Figure 4. On–Resistance versus Drain Current and Gate Voltage 10,000 2.0 VGS = 10 V ID = 38 A 1.5 I DSS , LEAKAGE (nA) RDS(on) , DRAIN–TO–SOURCE RESISTANCE (NORMALIZED) 4.5 Figure 2. Transfer Characteristics RDS(on) , DRAIN–TO–SOURCE ON–RESISTANCE (OHMS) RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS) Figure 1. On–Region Characteristics 2.5 3.0 3.5 4.0 VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) 1.0 1000 TJ = 125°C 100 100°C 0.5 0 –50 10 –25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (°C) 125 150 Figure 5. On–Resistance Variation with Temperature Motorola TMOS Power MOSFET Transistor Device Data 5.0 10 15 20 25 VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) 30 Figure 6. Drain–To–Source Leakage Current versus Voltage 3 MTB1306 POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (∆t) are determined by how fast the FET input capacitance can be charged by current from the generator. The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off–state condition when calculating td(on) and is read at a voltage corresponding to the on–state when calculating td(off). The published capacitance data is difficult to use for calculating rise and fall because drain–gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG – VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn–on and turn–off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG – VGSP)] td(off) = RG Ciss In (VGG/VGSP) 9000 C, CAPACITANCE (pF) 8000 7000 VDS = 0 V VGS = 0 V Ciss 6000 5000 Crss 4000 3000 Ciss 2000 Coss 1000 Crss 0 –10 –5.0 VGS 5.0 0 10 15 20 25 VDS VGS OR VDS, GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation 4 Motorola TMOS Power MOSFET Transistor Device Data 18 15 7.5 QT 12 VGS 5.0 9.0 Q1 Q2 6.0 2.5 Q3 TJ = 25°C ID = 75 A VDS 3.0 0 0 0 10 50 20 30 40 QG, TOTAL GATE CHARGE (nC) 10,000 VDD = 15 V ID = 75 A VGS = 5.0 V TJ = 25°C 1000 t, TIME (ns) 10 VDS , DRAIN–TO–SOURCE VOLTAGE (VOLTS) VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) MTB1306 tr tf 100 td(off) td(on) 10 1.0 60 Figure 8. Gate–To–Source and Drain–To–Source Voltage versus Total Charge 10 RG, GATE RESISTANCE (OHMS) 100 Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN–TO–SOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 15. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by high di/dts. The diode’s negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to Motorola standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. 20 VGS = 0 V TJ = 25°C IS , SOURCE CURRENT (AMPS) 18 16 14 12 10 8.0 6.0 4.0 2.0 0 0.45 0.50 0.55 0.60 0.65 0.70 0.75 VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS) Figure 10. Diode Forward Voltage versus Current Motorola TMOS Power MOSFET Transistor Device Data 5 MTB1306 Standard Cell Density trr I S , SOURCE CURRENT High Cell Density trr tb ta t, TIME Figure 11. Reverse Recovery Time (trr) SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain–to–source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance–General Data and Its Use.” Switching between the off–state and the on–state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 µs. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) – TC)/(RθJC). A Power MOSFET designated E–FET can be safely used in switching circuits with unclamped inductive loads. For reli- able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non–linearly with an increase of peak current in avalanche and peak junction temperature. Although many E–FETs can withstand the stress of drain– to–source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. 280 100 VGS = 10 V SINGLE PULSE TC = 25°C EAS , SINGLE PULSE DRAIN–TO–SOURCE AVALANCHE ENERGY (mJ) I D , DRAIN CURRENT (AMPS) 1000 1.0 ms 10 ms 10 dc 1.0 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 200 160 120 80 40 0 0.1 10 1.0 VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) Figure 12. Maximum Rated Forward Biased Safe Operating Area 6 ID = 75 A 240 100 25 50 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (°C) 150 Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature Motorola TMOS Power MOSFET Transistor Device Data MTB1306 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 1.0 D = 0.5 0.2 0.1 0.1 P(pk) 0.05 0.02 t1 0.01 t2 DUTY CYCLE, D = t1/t2 SINGLE PULSE RθJC(t) = r(t) RθJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) – TC = P(pk) RθJC(t) 0.01 1.0E–05 1.0E–04 1.0E–03 1.0E–02 t, TIME (s) 1.0E–01 1.0E+00 1.0E+01 Figure 14. Thermal Response di/dt IS trr ta tb TIME 0.25 IS tp IS Figure 15. Diode Reverse Recovery Waveform Motorola TMOS Power MOSFET Transistor Device Data 7 MTB1306 PACKAGE DIMENSIONS C E V –B– 4 A 1 2 3 DIM A B C D E G H J K S V S –T– SEATING PLANE K J G D 3 PL 0.13 (0.005) H M T B NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. INCHES MIN MAX 0.340 0.380 0.380 0.405 0.160 0.190 0.020 0.035 0.045 0.055 0.100 BSC 0.080 0.110 0.018 0.025 0.090 0.110 0.575 0.625 0.045 0.055 MILLIMETERS MIN MAX 8.64 9.65 9.65 10.29 4.06 4.83 0.51 0.89 1.14 1.40 2.54 BSC 2.03 2.79 0.46 0.64 2.29 2.79 14.60 15.88 1.14 1.40 M CASE 418B–03 (D2PAK) ISSUE C Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. 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